DATASHEET
ISL91133
FN8680
Rev 1.00
Jul 12, 2018
High Efficiency 2.3A Boost Regulator with Input-to-Output Bypass
The ISL91133 is an integrated boost switching regulator for
battery powered applications. The device provides a power
supply solution for products using a one cell Li-ion or
Li-polymer battery.
Features
The device is capable of delivering up to 2.3A output current
from VIN = 2.5V and VOUT = 3.3V. The no load quiescent
current is only 108μA in Boost mode and 45μA in Forced
Bypass mode, which significantly reduces the standby
consumption.
• Burst current up to 2.5A (VIN = 2.5V, VOUT = 3.3V,
tON < 600µs, T = 4.6ms)
The ISL91133 offers a Bypass mode operation where the
output is directly connected to the input through a 38mΩ
MOSFET to allow a significantly lower dropout voltage. The
Bypass mode can be entered by an external command, or by
auto bypass. The Forced Bypass mode allows the output
voltage to operate close to the input voltage and improves the
efficiency under these conditions.
The ISL91133 is designed to support 6 fixed output voltages
ranging from 3.15V to 5V. A voltage select pin is available for
each output variant to scale up the output voltage by a small
offset to compensate the load transient droop.
The ISL91133 requires only an inductor and a few external
components to operate. The 2.5MHz switching frequency
further reduces the size of external components.
The ISL91133 is available in a 16 bump, 0.4mm pitch,
1.78mmx1.78mm WLCSP.
• Input voltage range: 2.35V to 5.4V
• Output current: up to 2.3A (VIN = 2.5V, VOUT = 3.3V)
• High efficiency: up to 96%
• 108µA quiescent current minimizes standby consumption in
Boost mode, 45µA in Forced Bypass mode
• 2.5MHz switching frequency minimizes external component
size
• Forced Bypass or Auto Bypass modes with a 38mΩ switch
• PFM mode at light load currents
• Fully protected for overcurrent, over-temperature, and
undervoltage
• Load disconnect when disabled
• Small 1.78mmx1.78mm WLCSP
Applications
• Smartphones and tablet PCs
• Wireless communication devices
• 2G/3G/4G RF power amplifiers
• USB OTG power source
Related Literature
For a full list of related documents, visit our website
• ISL91133 product page
L1
0.47µH
C1
22µF
ISL91133IIMZ
LX
VOUT
VOUT = 3.3V TO VIN
UP TO 2.3A
C2
2x22µF
VIN
R1
EN
BYPS
PG
VSEL
RESET
PGND
AUTO BYPASS
FORCED BYPASS
GND
VOUT HI
VOUT LO
EFFICIENCY (%)
VIN =
2.35V TO 5.4V
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
0.001
4VIN
3VIN
2.7VIN
2.5VIN
0.01
0.1
1
IOUT (A)
FIGURE 1. TYPICAL APPLICATION
FN8680 Rev 1.00
Jul 12, 2018
FIGURE 2. EFFICIENCY vs LOAD CURRENT, VOUT = 3.3V
Page 1 of 14
ISL91133
Block Diagram
Q3
A3
VIN
A4
B3
VOUT
B4
C3
LX
Q2
C4
GATE DRIVERS
AND ANTI
SHOOT-THRU
D2
Q1
D3 PGND
D4
VIN
MONITOR
OSC
THERMAL
SHUTDOWN
Vref
EN A1
VOUT
CLAMP
CONTROL
VSEL B1
CURRENT
DETECT
PG A2
VOUT
ERROR
AMP
Ref
COMP
COMPENSATOR
BYPS C1
B2
C2
D1
GND
FIGURE 3. BLOCK DIAGRAM
FN8680 Rev 1.00
Jul 12, 2018
Page 2 of 14
ISL91133
Pin Configuration
Pin Descriptions
16 BALL WLCSP
TOP VIEW
PIN #
PIN
NAMES
B3, B4
VOUT
DESCRIPTION
Boost output; connect a 2x22µF capacitor to
PGND.
A1
A2
A3
A4
EN
PG
VIN
VIN
C3, C4
LX
B2
B3
B4
D2, D3,
D4
PGND
B1
VSEL
GND
VOUT
VOUT
A3, A4
VIN
C1
C2
C3
C4
B1
VSEL
BYPS
GND
LX
LX
Output selection between LO and HI. While
operating at boost mode, pull this pin HI to select
the high output level. To select the low output
level, pull this pin to LO.
D1
D2
D3
D4
A2
PG
GND
PGND
PGND
PGND
Open-drain output; provides output power-good
status.
A1
EN
Logic input; drive HIGH to enable device.
C1
BYPS
Force bypass input; Pull this pin LO to activate
forced bypass mode, where both Q2 and Q3 are
turned on, the rest of the IC is disabled. When this
pin is HI, auto bypass mode is activated.
B2, C2,
D1
GND
Analog ground pin
Inductor connection
Power ground for high switching current.
Power input; Range: 2.35V to 5.4V. Connect a
22µF capacitor to PGND.
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
VOUT (V)
TEMP RANGE (°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
TAPE AND REEL
(RoHS Compliant)
PKG.
DWG. #
ISL91133IILZ-T
133L
3.15/3.3
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IIMZ-T
133M
3.3/3.5
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IINZ-T
133N
3.5/3.7
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IIOZ-T
133O
3.7/3.77
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IIPZ-T
133P
4.5/4.76
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IIQZ-T
133Q
5.0/5.2
-40 to +85
3k
16 Ball WLCSP
W4x4.16E
ISL91133IIL-EVZ
Evaluation Board for ISL91133IILZ
ISL91133IIM-EVZ
Evaluation Board for ISL91133IIMZ
ISL91133IIN-EVZ
Evaluation Board for ISL91133IINZ
ISL91133IIO-EVZ
Evaluation Board for ISL91133IIOZ
ISL91133IIP-EVZ
Evaluation Board for ISL91133IIPZ
ISL91133IIQ-EVZ
Evaluation Board for ISL91133IIQZ
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free WLCSP packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball
terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free WLCSP packaged products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL91133 product information page. For more information about MSL, see TB363.
FN8680 Rev 1.00
Jul 12, 2018
Page 3 of 14
ISL91133
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 225V
Charge Device Model (Tested per JESD22-C101F). . . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JB (°C/W)
16 Ball WLCSP Package (Notes 4, 5) . . . .
70
14
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range (Boost Only) . . . . . . . . . . . . . . . . . . . . . 2.35V to 5.5V
Max Load Current (VIN = 2.5V, VOUT = 3.3V) . . . . . . . . . . . . . . . . . . . .2.3A DC
Max Load Current (VIN = 2.5V, VOUT = 3.3V, tON = 600µs, T = 4.6ms). .2.5A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JB, the board temp is taken on the board near the edge of the package, on a trace at the middle of one side. See TB379.
Electrical Specifications
temperature range, -40°C to +85°C.
PARAMETER
VIN = VEN = 3V, L1 = 0.47µH, C1 = C2 = 22µF, TA = +25°C. Boldface limits apply across the operating
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6) UNIT
POWER SUPPLY
Input Voltage Range
VIN Undervoltage Lockout Threshold
VIN
VUVLO
2.35
Rising
Falling
2.2
1.9
5.4
V
2.35
V
2.0
V
VIN Supply Current in Boost Mode
IVIN_BOOST
PFM mode, no external load on VOUT
108
150
µA
VIN Supply Current in Auto Bypass Mode
IVIN_BYP1
VIN = 4.2V, VOUT < 4.2V
80
120
µA
VIN Supply in Forced Bypass Mode
IVIN_BYP2
VIN = 3.5V
45
70
µA
EN = GND, VIN = 3.6V
1.3
5
µA
3.15
5.20
V
VIN = 3.6V
-2
+4
%
VOUT Rising
5.4
5.7
V
VIN Supply Current, Shutdown
ISD
OUTPUT VOLTAGE REGULATION
Output Voltage Range, Boost Mode
VOUT
Output Voltage Accuracy
Output Voltage Clamp
Output Voltage Clamp Hysteresis
VCLAMP
IOUT = 100mA
VCLAMP_HS
170
mV
INDUCTOR VALLEY CURRENT LIMIT
Inductor Valley Current Limit
During Soft-Start
IPK_LMT
VIN = 2.6V
3.6
IPK_LMT_SU
4
4.6
A
1.5
A
DC/DC SWITCHING SPECIFICATIONS
Oscillator Frequency
fSW
2.1
2.50
2.9
MHz
BOOST ON-RESISTANCE
P-Channel MOSFET (Q2) ON-Resistance
rDSON_P
VIN = 3.5V, IO = 200mA
0.04
Ω
N-Channel MOSFET (Q1) ON-Resistance
rDSON_N
VIN = 3.5V, IO = 200mA
0.045
Ω
Load Current Threshold, PFM to PWM
VIN = 3.0V, VOUT = 3.3V
500
mA
Load Current Threshold, PWM to PFM
VIN = 3.0V, VOUT = 3.3V
300
mA
PFM/PWM TRANSITION
FN8680 Rev 1.00
Jul 12, 2018
Page 4 of 14
ISL91133
Electrical Specifications
VIN = VEN = 3V, L1 = 0.47µH, C1 = C2 = 22µF, TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6) UNIT
THERMAL SHUTDOWN
Thermal Warning
120
°C
Thermal Shutdown
150
°C
Thermal Shutdown and Thermal Warning
Hysteresis
20
°C
LEAKAGE CURRENT
VO To VIN Reverse Leakage
ILEAK
VIN to VOUT Leakage
LX Pin Leakage Current
INFETLEAK
VIN = 3V, VOUT = 5V, EN = 0
0.3
1.0
µA
VIN = 3V, VOUT = 0V, EN = 0
0.05
1.0
µA
1
µA
VLX = 5V, EN = 0
-1
SOFT-START
Level 1 Linear Start-up Current, Fast
ILIN1
Level 1 Linear Start-up Current, Slow
Level 2 Linear Start-up Current, Fast
ILIN2
Level 1 Linear Start-up Current, Slow
Soft-Start Time EN Hi to Regulation
tSS
ISL91133IILZ, ISL91133IIMZ, ISL91133IINZ,
ISL91133IIOZ
1300
mA
ISL91133IIPZ, ISL91133IIQZ
350
ISL91133IILZ, ISL91133IIMZ, ISL91133IINZ,
ISL91133IIOZ
2400
ISL91133IIPZ, ISL91133IIQZ
700
ISL91133IILZ, ISL91133IIMZ, ISL91133IINZ,
ISL91133IIOZ, 50Ωload
600
µs
ISL91133IIPZ, ISL91133IIQZ, 50Ωload
1200
µs
IOUT = 600mA, VIN = 3.5V
0.038
Ω
100
mV
mV
mA
BYPASS MODE
Bypass P-Channel MOSFET (Q3)
ON-Resistance
rDSON_BP
Auto Bypass Hysteresis
VBYP_Hys
Bypass Mode Current Limit (for
ISL91133IIPZ and ISL91133IIQZ only)
VOCP_BYP
VIN = 5V, measured by VIN-VOUT
150
IPG_LEAK
PG = HIGH
0.05
LOGIC INPUTS/OUTPUT (PG, EN, VSEL, BYPS)
Input Leakage, PG
1
µA
Input HIGH Voltage, EN, VSEL, BYPS
VIH
Input LOW Voltage, EN, VSEL, BYPS
VIL
Pull-down Resistance, EN, VSEL, BYPS
RPD
1.5
MΩ
FAULT Reset Timer
tFRST
20
ms
1.2
V
0.4
V
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Typical values are for TA = +25°C and VIN = 3V.
FN8680 Rev 1.00
Jul 12, 2018
Page 5 of 14
ISL91133
Typical Performance Curves
100
96
EFFICIENCY (%)
EFFICIENCY (%)
98 LOAD = 0.5A
LOAD = 1A
94
LOAD = 1.5A
92
90
88
86
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
98
96
94
92
90
88
86
84
82
80
78
76
74
0.001
3.3VIN
3VIN
2.7VIN
2.5VIN
0.01
0.1
VIN (V)
FIGURE 4. EFFICIENCY vs VIN, VOUT = 3.3V
10
FIGURE 5. EFFICIENCY vs LOAD CURRENT, VOUT = 3.5V
150
4.2VIN
95
90
85
2.7VIN
3VIN
3.3VIN
80
75
3.6VIN
140
SUPPLY CURRENT (µA)
100
EFFICIENCY (%)
1
IOUT (A)
130
120
VOUT = 5V
110
100
90
VOUT = 3.3V
80
70
70
0.001
0.01
0.1
1
60
2.4
2.9
3.4
FIGURE 6. EFFICIENCY vs LOAD CURRENT, VOUT = 5V
VOUT (20mV/DIV)
3.9
4.4
VIN (V)
IOUT (A)
FIGURE 7. SUPPLY CURRENT vs VIN
VOUT (20mV/DIV)
VLX (2V/DIV)
VLX (2V/DIV)
ILX (500mA/DIV)
2.0µs/DIV
FIGURE 8. SWITCHING WAVEFORM PFM MODE, VIN = 2.7V,
ILOAD = 50Ω, VOUT = 3.3V
FN8680 Rev 1.00
Jul 12, 2018
ILX (500mA/DIV)
200ns/DIV
FIGURE 9. SWITCHING WAVEFORM PWM MODE, VIN = 2.7V,
IOUT = 500mA, VOUT = 3.3V
Page 6 of 14
ISL91133
Typical Performance Curves (Continued)
PG (5V/DIV)
VIN (1V/DIV)
EN (5V/DIV)
VOUT (200mV/DIV)
VOUT (1V/DIV)
IIN (500mA/DIV)
ILOAD (1A/DIV)
100µs/DIV
FIGURE 10. START-UP WAVEFORM 50Ω LOAD, VIN = 3V, VOUT = 3.3V
100µs/DIV
FIGURE 11. LOAD STEP RESPONSE, VIN = 2.7V,
ILOAD = 10mA -> 1500mA -> 10mA
VOUT (100mV/DIV)
VIN (1V/DIV)
VOUT (200mV/DIV)
VSET (1V/DIV)
ILOAD (1A/DIV)
100µs/DIV
FIGURE 12. LOAD STEP RESPONSE, VIN = 3V,
IOUT = 10mA -> 1500mA -> 10mA
20µs/DIV
FIGURE 13. VSET TOGGLE RESPONSE, VIN = 3V, VOUT = 3.3V,
LOAD = 0.5A
VOUT (200mV/DIV)
VOUT (200mV/DIV)
3.3V
3.3V
VIN (200mV/DIV)
VIN (200mV/DIV)
400µs/DIV
FIGURE 14. VSET TOGGLE RESPONSE, VIN = 3.1V -> 3.5V -> 3.1V
LOAD = 1A
FN8680 Rev 1.00
Jul 12, 2018
4.0µs/DIV
FIGURE 15. VSET TOGGLE RESPONSE, VIN = 3.1V -> 3.5V,
LOAD = 1A
Page 7 of 14
ISL91133
Typical Performance Curves (Continued)
65
60
55
rDS(ON) (mΩ)
VIN (200mV/DIV)
VOUT (200mV/DIV)
3.3V
NMOSBOOST
50
45
40
PMOSBYPASS
PMOSBOOST
35
30
25
20
2.0
4.0µs/DIV
FIGURE 16. VSET TOGGLE RESPONSE, VIN = 3.5V -> 3.1V, LOAD = 1A
FN8680 Rev 1.00
Jul 12, 2018
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
FIGURE 17. MOS rDS(ON) vs VIN
Page 8 of 14
6.0
ISL91133
Functional Description
Functional Overview
Refer to the “Block Diagram” on page 2. The ISL91133
implements a complete boost switching regulator with PWM
controller, internal switches, references, protection circuitry, and
bypass control.
Internal Supply and References
Referring to the “Block Diagram” on page 2, the ISL91133
provides a power input pin. The VIN pin provides an operating
voltage source required for stable VREF generation. During Bypass
mode, the VIN pin also carries the input power to the output.
Separate ground pins (GND and PGND) are provided to avoid
problems caused by ground shift due to the high switching currents.
Enable Input
A master enable pin, EN, allows the device to be enabled. Driving
EN low invokes a power-down mode, where most internal device
functions, including input and output power-good detection, are
disabled.
POR Sequence and Soft-start
Bringing the EN pin high allows the device to power up. A number
of events occur during the start-up sequence. The internal voltage
reference powers up, and stabilizes. The device then starts
operating.
When the device is enabled, the start-up cycle starts in the Linear
mode. During the linear phase, the bypass FET Q3 is controlled
as a constant current source, delivering a fixed current ILIN1 as
shown in the “Electrical Specifications” table on page 5. If the
output voltage has not reached the VIN - 300mV threshold within
the 512µs time interval during the ILIN1 mode, the ISL91133
enters a level 2 Linear mode, where the bypass MOSFET Q3 is
controlled as a constant current source, delivering a fixed current
ILIN2 as shown in the “Electrical Specifications” table on page 5.
If VOUT still has not reached the VIN - 300mV threshold within
1024µs in the ILIN2 current, a fault condition is triggered.
When VOUT successfully rises to within 300mV from VIN within
either the ILIN2 or ILIN2 period, the boost operation starts. The
boost operation begins with a fixed duty-cycle of 75% with a
reduced current limit (IPK_LMT_SU) as shown in the “Electrical
Specifications” on page 4. The fixed duty-cycle operation
continues until the output voltage reaches 2.3V, then the
closed-loop current mode PWM loop overrides the duty cycle to
regulate the output voltage.
If the output has not reached the target regulation voltage after
64µs, a FAULT condition is triggered.
Due to the soft-start current limits and time constraints, it is
recommended that the output current be limited to below
500mA at power-up, especially when the output capacitor value
is large. If the output current exceeds the start-up capability, a
fault condition is triggered. The regulator shuts down for 20ms,
then soft-start repeats. This Hiccup mode continues until the
output current is reduced to reach the regulated output voltage.
FN8680 Rev 1.00
Jul 12, 2018
Boost Mode Overcurrent Protection
When the inductor peak current in the N-channel MOSFET
reaches the current limit for 16 consecutive switching cycles, the
internal protection circuit is triggered, and switching is stopped
for approximately 20ms. The device then performs a soft-start
cycle. If the external output overcurrent condition exists after the
soft-start cycle, the device again detects 16 consecutive
switching cycles reaching the valley current threshold. The
process repeats as long as the external overcurrent condition is
present. This behavior is called ‘Hiccup mode’.
Short-Circuit Protection
The ISL91133 provides short-circuit protection by monitoring the
output voltage. When output voltage is sensed to be lower than a
certain threshold, the PWM oscillator frequency is reduced in
order to protect the device from damage. The N-channel MOSFET
peak current limit remains active during this state.
Boost Conversion Topology
The ISL91133 integrates one N-channel MOSFET (Q1 in the block
diagram on page 2) and one P-channel MOSFET (Q2) to
implement a synchronous boost converter. A body switch
scheme is employed in Q2 to implement the true shutdown
function when the device is disabled. Otherwise the step-up
converter has a conduction path from the input to the output via
the body diode of the P-channel MOSFET.
PWM Operation
The control scheme of the device is based on the valley current
mode control, and the control loop is compensated internally.
The valley current of the P-channel MOSFET switch is sensed to
limit the maximum current flowing through the switch and the
inductor. The typical current limit is set to 4A.
The control circuit includes a ramp generator, a slope
compensator, an error amplifier and a PWM comparator. The
ramp signal is derived from the inductor current. This ramp signal
is then compared to the error amplifier output to generate the
PWM gating signals for both the N-channel and the P-channel
MOSFETs. The PWM operation is initialized by the clock from the
internal oscillator (typical 2.5MHz). The P-channel MOSFET is
turned on at the beginning of a PWM cycle, the N-channel
MOSFET remains off, and the current starts ramping down. When
the sum of the ramp and the slope compensator output reaches
the error amplifier output voltage, the PWM comparator outputs
a signal to turn off the P-channel MOSFET. At this time, both
MOSFETs remain off during the dead-time interval. After the
dead time, the N-channel MOSFET is turned on and remains on
until the end of this PWM cycle. During this time, the inductor
current ramps up until the next clock. Following a short dead
time, the P-channel MOSFET is turned on again, repeating as
previously described.
PFM Operation
The boost converter is capable of operating in two different
modes. When the inductor current is sensed to cross zero for
eight consecutive times, the converter enters PFM mode. In PFM
mode, each pulse cycle is still synchronized by the PWM clock.
The N-channel MOSFET is turned on at the rising edge of the
clock and turned off when the inductor valley current reaches
Page 9 of 14
ISL91133
typically 20% of the current limit. Then the P-channel MOSFET is
turned on, and it stays on until its current goes to zero.
Subsequently, both N-channel and P-channel MOSFETs are
turned off until the next clock cycle starts, at which time the
N-channel MOSFET is turned on again. When VOUT is 1.5% higher
than the nominal output voltage, the N-channel MOSFET is
immediately turned off and the P-channel MOSFET is turned on
until the inductor current goes to zero. The N-channel MOSFET
resumes operation when VOUT falls back to its nominal value,
repeating the previous operation. The converter returns to
2.5MHz PWM mode operation when VOUT drops to 1.5% below
its nominal voltage.
Based on this PFM mode algorithm, the average value of the
output voltage is approximately 0.75% higher than the nominal
output voltage under PWM operation. This positive offset
improves the load transient response when switching from skip
mode to PWM mode operation. The ripple on the output voltage
is typically 1.5%*VOUT (nominal) when input voltage is
sufficiently lower than output voltage, and it increases as input
voltage approaches output voltage.
PG FLAG
PG is an open-drain output, it provides a flag signal (Hi-Z) to the
system when power-up is successful. The PG also provides an
early warning flag for overcurrent and over-temperature
conditions by turning on the open-drain FET. If a fault condition is
encountered, the PG is deasserted.
To summarize, PG is deasserted if:
1. VOUT drops below the PG low threshold (96% of VOUT).
2. Die temperature has reached the thermal warning threshold
(+120°C typ).
3. A fault condition is encountered.
VIN
rON x IOUT
REGULATED
VOUT
VOUT
VBYP_F
Bypass Operation
The ISL91133 is designed to allow bypass operation when the
input voltage is within close proximity of the output voltage. The
bypass operation is provided by a 38mΩ P-channel MOSFET Q3
connecting between VIN and VOUT. In the bypass mode, Q1 in the
boost circuit is turned off and Q2 is turned on. Thus, the effective
bypass resistance is the parallel combination of the rON of Q3,
and the series of the inductor DCR and rON of Q2.
BYPASS
TIME
BOOST
FIGURE 18. AUTO BYPASS WITH FALLING VIN
There are two ways to enter Bypass mode: Auto Bypass and
Forced Bypass.
AUTO BYPASS
rON x IOUT
Auto bypass is enabled by pulling the BYPS pin HIGH. When VIN is
1.5% higher than the target VOUT regulation and no switching
has occurred for 5µs, the device automatically enters the bypass
mode. Figures 18 and 19 illustrate the time sequence of the auto
bypass mode entry.
FORCED BYPASS
Forced Bypass mode can be activated by pulling the BYPS pin
LOW. Figures 20 and 21 illustrate the time sequence of the
forced bypass entry. If VOUT is VIN when bypass is
requested (BYPS is LOW), to prevent reverse current flowing from
the output to the battery, the ISL91133 first stops the boost
operation and activates an internal discharge circuit to discharge
the output voltage to the VIN level before bypass can take place.
REGULATED
VOUT
VIN
VOUT
VBYP_R
TIME
BOOST
BYPASS
FIGURE 19. AUTO BYPASS WITH RISING VIN
FAULT MODE
The ISL91133 enters a FAULT mode if one of the following
conditions are encountered:
1. During start-up, VOUT does not reach the threshold from
Linear mode to Boost mode within the preset time interval.
2. In Boost mode, peak current limit is reached for longer than
2ms.
FN8680 Rev 1.00
Jul 12, 2018
Page 10 of 14
ISL91133
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
VIN
rON x IOUT
REGULATED
VOUT
TABLE 1. INDUCTOR VENDOR INFORMATION
VOUT
SERIES
INDUCTANCE
(µH)
DIMENSION
(mm)
TDK
TFM201610A
0.47
2.0x1.6x1.0
TOKO
DFE201610R
0.47
2.0x1.6x1.0
CYNTEC
PIFE32251B
0.47
3.2x2.5x1.2
MANUFACTURER
VBYPS
VIN AND VOUT CAPACITOR SELECTION
TIME
TBYP_BST
FIGURE 20. FORCED MODE, BYPASS TO BOOST
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
22µF. The recommended VOUT capacitor value is 10µF to 22µF.
TABLE 2. CAPACITOR VENDOR INFORMATION
DISCHA RG E
PERIO D
T DISCHG
MANUFACTURER
rON x IOUT
REG ULA TED
V OUT
V OUT
SERIES
WEBSITE
AVX
X5R
www.avx.com
Murata
X5R
www.murata.com
Taiyo Yuden
X5R
www.t-yuden.com
TDK
X5R
www.tdk.com
Recommended PCB Layout
V IN
V BYPS
T BST_BYP
TIM E
Correct PCB layout is critical for proper operation of the
ISL91133. Position the input and output capacitors as close to
the IC as possible. Keep the ground connections of the input and
output capacitors as short as possible and on the component
layer to avoid problems that are caused by high switching
currents flowing through PCB vias.
FIGURE 21. FORCED MODE, BOOST TO BYPASS
Thermal Shutdown
A built-in thermal protection feature protects the ISL91133, if the
die temperature reaches +150°C (typical). At this die
temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal-shutdown
mode. When the die temperature falls to +120°C (typical), the
device resumes normal operation.
Applications Information
Component Selection
Refer to the typical application circuit in Figure 1 on page 1, and
the following component selection sections.
INDUCTOR SELECTION
An inductor with high frequency core material (for example,
ferrite core) should be used to minimize core losses and provide
good efficiency. The inductor must be able to handle the peak
switching currents without saturating.
FIGURE 22. LAYOUT RECOMMENDATION
A 0.47µH inductor with ≥3A saturation current rating is
recommended. Select an inductor with low DCR to provide good
FN8680 Rev 1.00
Jul 12, 2018
Page 11 of 14
ISL91133
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
you have the latest revision.
DATE
REVISION
Jul 12, 2018
FN8680.1
Updated Related Literature section.
Updated the ordering information table by adding Tape and Reel quantity column.
Removed About Intersil section and updated Disclaimer.
Sep 5, 2014
FN8680.0
Initial Release
FN8680 Rev 1.00
Jul 12, 2018
CHANGE
Page 12 of 14
ISL91133
Package Outline Drawing
For the most recent package outline drawing, see W4x4.16E.
W4x4.16E
4X4 ARRAY 16 BALLS WITH 0.40 PITCH WAFER LEVEL CHIP SCALE PACKAGE
Rev 0, 2/13
X
1.200
1.780±0.030
Y
D
C
16x 0.265±0.035
1.780±0.030
0.200
B
0.400
A
0.290
1
0.10
TOP VIEW
(4X)
3
4
0.290
BOTTOM VIEW
PIN 1
(A1 CORNER)
0.240
2
PACKAGE
OUTLINE
0.400
0.040 BSC
(BACK SIDE COATING)
0.290
0.540±0.050
0.05
3 NSMD
0.200±0.030
0.265±0.035
Z
Z SEATING
PLANE
TYPICAL RECOMMENDED LAND PATTERN
0.10
0.05
ZXY
Z
SIDE VIEW
NOTES:
FN8680 Rev 1.00
Jul 12, 2018
1.
All dimensions are in millimeters.
2.
Dimension and tolerance conform to ASMEY14.5-1994,
and JESD 95-1 SPP-010.
3.
NSMD refers to non-solder mask defined pad design per TB451.
Page 13 of 14
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