ISL95810UIRT8

DATASHEET ISL95810 FN8090 Rev.3.01 Jun 5, 2020 Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power I2C Bus, 256 Taps The ISL95810 integrates a digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. Features The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by you through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read. The content of the WR controls the position of the wiper. At power-up, the device recalls the contents of the DCP’s IVR to the WR. • I2C serial interface • 256 resistor taps - 0.4% resolution • Wiper resistance: 70Ω typical at 3.3V • Non-volatile storage of wiper position • Standby current 5µA max • Power supply: 2.7V to 5.5V • 50kΩ, 10kΩ total resistance The DCP can be used as a 3-terminal potentiometer or as a 2-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • High reliability - Endurance: 200,000 data changes per bit per register - Register data retention: 50 years at T  +75°C • 8 Ld MSOP and 8 Ld TDFN packaging Related Literature • Pb-free plus anneal available (RoHS compliant) For a full list of related documents, visit our website: • ISL95810 device page VCC RH SDA WIPER REGISTER SCL I2C AND RW CONTROL WP NON-VOLATILE REGISTER RL GND FIGURE 1. BLOCK DIAGRAM FN8090 Rev.3.01 Jun 5, 2020 Page 1 of 14 ISL95810 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING RTOTAL (kΩ) TAPE AND REEL (UNITS) (Note 1) TEMP RANGE (°C) ISL95810WIU8Z APN 10 - -40 to +85 8 Ld MSOP ISL95810WIU8Z-T APN 2.5k -40 to +85 8 Ld MSOP ISL95810WIRT8Z APO - -40 to +85 8 Ld 3x3 TDFN ISL95810WIRT8Z-T APO 6k -40 to +85 8 Ld 3x3 TDFN ISL95810UIU8Z AOK - -40 to +85 8 Ld MSOP ISL95810UIU8Z-T AOK 2.5k -40 to +85 8 Ld MSOP ISL95810UIRT8Z APP - -40 to +85 8 Ld 3x3 TDFN ISL95810UIRT8Z-T APP 2.5k -40 to +85 8 Ld 3x3 TDFN ISL95810UART8Z-T ADR 2.5k -40 to +105 8 Ld 3x3 TDFN 50 PACKAGE (RoHS Compliant) NOTES: 1. See TB347 for details on reel specifications. 2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL95810 device page. For more information about MSL, see TB363. Pinouts 8 LD MSOP TOP VIEW 8 LD TDFN TOP VIEW WP 1 8 VCC SCL 2 7 RH SDA 3 6 GND 4 5 WP 1 8 VCC RL SCL 2 7 RH RW SDA 3 6 RL GND 4 5 RW Pin Descriptions TSSOP PIN SYMBOL 1 WP Hardware write protection. Active low. Prevents any “Write” operation of the I2C interface. 2 SCL I2C interface clock 3 SDA Serial data I/O for the I2C interface 4 GND Ground 5 RW “Wiper” terminal of the DCP 6 RL “Low” terminal of the DCP 7 RH “High” terminal of the DCP 8 VCC Power supply FN8090 Rev.3.01 Jun 5, 2020 DESCRIPTION Page 2 of 14 ISL95810 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at Any Digital Interface Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at Any DCP Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Thermal Resistance (Typical) JA (°C/W) 8 Ld DFN Package (Notes 4, 5) . . . . . . . . . 48 8 Ld MSOP Package (Notes 6, 7) . . . . . . . . 151 JC (°C/W) 6 50 Recommended Operating Conditions Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Extended Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 5. For JC, the case temperature location is the center of the exposed metal pad on the package underside. 6. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board. See TB379. 7. For JC, the case temperature location is taken at the package top center. Analog Specifications Over recommended operating conditions unless otherwise stated. PARAMETER RH to RL Resistance SYMBOL RTOTAL TEST CONDITIONS MIN W, U versions respectively Potentiometer Capacitance (Note 22) Leakage on DCP Pins (Note 22) -20 RW VCC = 3.3V at +25°C Wiper current = VCC/RTOTAL 70 CH/CL/CW ILkgDCP MAX 10, 50 RH to RL Resistance Tolerance Wiper Resistance TYP (Note 8) kΩ +20 % 200 Ω 10/10/25 Voltage at pin from GND to VCC 0.1 UNIT pF 1 µA VOLTAGE DIVIDER MODE (0V at RL; VCC at RH; measured at RW, unloaded) Integral Non-Linearity INL (Note 13) Differential Non-Linearity DNL (Note 12) Monotonic over all tap positions -1 W option -0.75 U option Zero-Scale Error ZSerror (Note 10) Full-Scale Error FSerror (Note 11) Ratiometric Temperature Coefficient TCV (Notes 14, 15 22) W option -0.5 1 LSB (Note 9) -0.75 LSB (Note 9) -0.5 LSB (Note 9) 7 LSB (Note 9) 0 1 U option 0 0.5 2 W option -7 -1 0 U option -2 -0.5 0 DCP Register set to 80 hex ±4 LSB (Note 9) ppm/°C RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) Integral Non-Linearity RINL (Note 19) DCP register set between 20 hex and FF hex. Monotonic over all tap positions Differential Non-Linearity RDNL (Note 12) DCP register set between 20 hex W option -0.75 and FF hex. Monotonic over all tap U option -0.5 positions Roffset (Note 17) W option 0 1 7 MI (Note 16) U option 0 0.5 2 MI (Note 16) Offset Resistance Temperature Coefficient FN8090 Rev.3.01 Jun 5, 2020 TCR (Notes 20, 21, 22) DCP register set between 20 hex and FF hex -1 ±165 1 MI (Note 16) -0.75 MI (Note 16) -0.5 MI (Note 16) ppm/°C Page 3 of 14 ISL95810 Operating Specifications Over the recommended operating conditions unless otherwise specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP (Note 8) MAX UNIT VCC Supply Current (Volatile write/read) ICC1 (Note 24) fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Volatile Write States only) 1 mA VCC Supply Current (Nonvolatile Write) ICC2 (Note 24) fSCL = 400kHz; SDA = Open; (for I2C, Active, Nonvolatile Write State only) 3 mA ISB (Note 24) VCC = +5.5V, I2C Interface in Standby State 5 µA VCC Current (Standby) VCC = +3.6V, I2C Interface in Standby State Leakage Current, at Pins SDA, SCL, and WP Pins DCP Wiper Response Time ILkgDig tDCP (Note 22) Power-On Recall Voltage Vpor VCC Ramp Rate VCCRamp Power-Up Delay tD (Note 22) Voltage at pin from GND to VCC -10 SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs 1.8 2 µA 10 µA 1 µs 2.6 V 0.2 VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state V/ms 3 ms EEPROM SPECIFICATIONS EEPROM Endurance Temperature 75°C EEPROM Retention 200,000 Cycles 50 Years SERIAL INTERFACE SPECIFICATIONS WP, SDA, and SCL Input Buffer LOW Voltage VIL -0.3 0.3*VCC V WP, SDA, and SCL Input Buffer HIGH Voltage VIH 0.7*VCC VCC+0.3 V SDA and SCL Input Buffer Hysteresis Hysteresis (Note 13) 0.05*VCC SDA Output Buffer LOW Voltage, Sinking 4mA VOL (Note 22) WP, SDA, and SCL Pin Capacitance Cpin (Note 22) 10 pF fSCL 400 kHz SCL Frequency 0 V 0.4 V Pulse Width Suppression Time at SDA and SCL Inputs tIN (Note 22) Any pulse narrower than the max spec is suppressed. 50 ns SCL Falling Edge to SDA Output Data Valid tAA (Note 22) SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. 900 ns tBUF (Note 22) SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Measured at the 30% of VCC crossing. 1300 ns tHIGH Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Measured at the 70% of VCC crossing. 600 ns START Condition Setup Time tSU:STA SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns START Condition Hold Time tHD:STA From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 600 ns Input Data Setup Time tSU:DAT From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns Input Data Hold Time tHD:DAT From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. 0 ns STOP Condition Setup Time tSU:STO From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 600 ns STOP Condition Hold Time for Read, or Volatile Only Write tHD:STO From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. 600 ns STOP Condition Hold Time for NonVolatile Write tHD:STO:NV From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. 2 µs Clock HIGH Time FN8090 Rev.3.01 Jun 5, 2020 Page 4 of 14 ISL95810 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) PARAMETER Output Data Hold Time SYMBOL TEST CONDITIONS MIN tDH (Note 22) From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. 0 TYP (Note 8) MAX UNIT ns SDA and SCL Rise Time tR (Note 22) From 30% to 70% of VCC 20 + 0.1 * Cb 250 ns SDA and SCL Fall Time tF (Note 22) From 70% to 30% of VCC 20 + 0.1 * Cb 250 ns 400 Capacitive Loading of SDA or SCL Cb (Note 22) Total on-chip and off-chip 10 SDA and SCL Bus Pull-Up Resistor Off-Chip Rpu (Note 22) Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5kΩ. For Cb = 40pF, max is about 15~20kΩ 1 Non-Volatile Write Cycle Time tWP (Notes 22, 23) pF kΩ 12 20 ms WP Setup Time tSU:WP Before START condition 600 ns WP Hold Time tHD:WP After STOP condition 600 ns NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltage. 9. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 – VCC]/LSB. 12. DNL = {[V(RW)i – V(RW)i-1]/LSB}-1, for i = 1 to 255. i is the DCP register setting. 13. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255. Max  V  RW  i  – Min  V  RW  i  10 6 14. TC V = ----------------------------------------------------------------------------------------------  ----------------- for i = 16 to 240 decimal, T = -40°C to +85°C. Max( ) is the maximum value of the wiper  Max  V  RW  i  + Min  V  RW  i    2 125°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. Max  V  RW  i  – Min  V  RW  i  10 6 15. TC V = ----------------------------------------------------------------------------------------------  ----------------- for i = 16 to 240 decimal, T = -40°C to +105°C. Max( ) is the maximum value of the wiper  Max  V  RW  i  + Min  V  RW  i    2 145°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 16. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0/MI, when measuring between RW and RL. 17. Roffset = R255/MI, when measuring between RW and RH. 18. RDNL = [(Ri – Ri-1)/MI]-1, for i = 32 to 255. 19. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 255. 6  Max  Ri  – Min  Ri   10 20. TC R = ----------------------------------------------------------------  ----------------- for i = 32 to 255, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the  Max  Ri  + Min  Ri    2 125°C minimum value of the resistance over the temperature range. 6  Max  Ri  – Min  Ri   10 21. TC R = ----------------------------------------------------------------  ----------------- for i = 32 to 255, T = -40°C to +105°C. Max( ) is the maximum value of the resistance and Min ( ) is the  Max  Ri  + Min  Ri    2 145°C minimum value of the resistance over the temperature range. 22. This parameter is not 100% tested. 23. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 24. VIL = 0V, VIH = VCC FN8090 Rev.3.01 Jun 5, 2020 Page 5 of 14 ISL95810 SDA vs SCL Timing tF SCL tHIGH tLOW tR tSU:DAT tSU:STA SDA (INPUT TIMING) tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) WP Pin Timing STOP START SCL tHD:STO tHD:STO:NV CLK 1 SDA IN tSU:WP tHD:WP WP FN8090 Rev.3.01 Jun 5, 2020 Page 6 of 14 ISL95810 Typical Performance Curves Vcc = 2.7V, T = -40°C Vcc = 2.7V, T = +25°C Vcc = 2.7V, T = +105°C 160 140 2.0 Vcc = 5.5V, T = -40°C Vcc = 5.5V, T = +25°C Vcc = 5.5V, T = +105°C 1.8 STANDBY ICC (μA) WIPER RESISTANCE (Ω) 180 120 100 80 60 40 T = +25°C T = +85°C T = +105°C 1.4 1.2 1.0 0.8 0.6 0.4 0.2 20 0 1.6 T = -40°C 0.0 0 50 100 150 200 250 2.7 3.2 3.7 4.2 Vcc = 2.7V, T = -40°C Vcc = 2.7V, T = +25°C Vcc = 2.7V, T = +105°C 0.15 0.3 Vcc = 5.5V, T = -40°C Vcc = 5.5V, T = +25°C Vcc = 5.5V, T = +105°C INL (LSB) 0.05 0.00 -0.05 Vcc = 2.7V, T = -40°C Vcc = 2.7V, T = +25°C Vcc = 2.7V, T = +105°C 0.2 0.10 DNL (LSB) 5.2 FIGURE 3. STANDBY ICC vs VCC FIGURE 2. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC / RTOTAL] for 50kΩ 0.20 4.7 VCC (V) TAP POSITION (DEC) Vcc = 5.5V, T = -40°C Vcc = 5.5V, T = +25°C Vcc = 5.5V, T = +105°C 0.1 0.0 -0.1 -0.10 -0.2 -0.15 -0.20 0 50 100 150 200 250 -0.3 0 50 100 FIGURE 4. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 50kΩ ACROSS -40°C to +105°C 0.0 Vcc = 5.5V Vcc = 2.7V -0.1 250 Vcc = 5.5V -0.2 FSERROR (LSB) 0.35 ZSERROR (LSB) 200 FIGURE 5. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 50kΩ 0.40 Vcc = 2.7V 150 TAP POSITION (DEC) TAP POSITION (DEC) 0.30 0.25 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.20 -0.9 0.15 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 6. ZSERROR vs TEMPERATURE FOR 50kΩ FN8090 Rev.3.01 Jun 5, 2020 100 -1.0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 7. FSERROR vs TEMPERATURE FOR 50kΩ Page 7 of 14 ISL95810 Typical Performance Curves 0.4 Vcc = 2.7V, T = -40°C Vcc = 2.7V, T = +25C Vcc = 2.7V, T = +105°C 0.3 (Continued) Vcc = 5.5V, T = -40°C Vcc = 5.5V, T = +25°C Vcc = 5.5V, T = +105°C 0.5 0.3 0.0 -0.1 -0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.3 -0.5 32 82 132 182 -0.6 232 32 82 132 TAP POSITION (DEC) 232 FIGURE 9. INL vs TAP POSITION IN RHEOSTAT MODE FOR 50kΩ ACROSS -40°C to +105°C 30 Vcc = 2.7V, Vcc = 5.5V, Vcc = 2.7V, Vcc = 5.5V, -40 -20 0 20 40 RTOTAL RTOTAL RTOTAL RTOTAL 60 = 50kΩ = 50kΩ = 10kΩ = 10kΩ 80 TEMPERATURE COEFFICIENT (ppm/°C) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 182 TAP POSITION (DEC) FIGURE 8. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50kΩ ACROSS -40°C to +105°C END-TO-END RTOTAL % CHANGE (%) Vcc = 5.5V, T = -40°C Vcc = 5.5V, T = +25°C Vcc = 5.5V, T = +105°C 0.2 0.1 RINL (MI) RDNL (MI) 0.2 -0.4 Vcc = 2.7V, T = -40°C Vcc = 2.7V, T = +25°C Vcc = 2.7V, T = +105°C 0.4 100 Vcc = 2.7V 25 Vcc = 5.5V 20 15 10 5 0 -5 -10 -15 -20 32 82 TEMPERATURE (°C) 132 182 232 TAP POSITION (DEC) FIGURE 10. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 11. TC FOR VOLTAGE DIVIDER MODE IN PPM TEMPERATURE COEFFICIENT (ppm/°C) 250 Vcc = 2.7V Vcc = 5.5V INPUT 200 150 100 OUTPUT 50 0 20 70 120 170 220 TAP POSITION = MID POINT RTOTAL = 9.4k TAP POSITION (DEC) FIGURE 12. TC FOR RHEOSTAT MODE IN PPM FN8090 Rev.3.01 Jun 5, 2020 FIGURE 13. FREQUENCY RESPONSE (2.2MHz) Page 8 of 14 ISL95810 Typical Performance Curves (Continued) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM ffh TO 00h) WIPER MOVEMENT MID POINT FROM 80h TO 7fh FIGURE 14. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0) FIGURE 15. LARGE SIGNAL SETTLING TIME Principles of Operation Memory Description The ISL95810 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory, and a I2C serial interface providing direct communication between a host and the potentiometer and memory. The ISL95810 volatile and non-volatile registers are accessed by I2C interface operations at addresses 0 and 2 decimal. The non-volatile byte at addresses 0 contains the initial value loaded at power-up into the volatile Wiper Register (WR) of the DCP. The byte at address 1 is reserved; the user should not write to it, and its value should be ignored if read. DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). The DCP has its own WR. When the WR of the DCP contains all zeroes (WR: 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR of the DCP contains all ones (WR: FFh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95810 is being powered up, The WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading, the ISL95810 reads the value stored in non-volatile Initial Value Registers (IVRs) and loads it into the WR. Note: The ISL95810 is programmed from the factory with the wiper set to mid-point (128) position: 0x80 The volatile WR, and the non-volatile Initial Value Register (IVR) of the DCP are accessed with the same Address Byte, set to 00 hex in both cases. A volatile byte at address 2 decimal, controls what byte is read or written when accessing DCP registers: the WR, the IVR, or both. When the byte at address 2 is all zeroes, which is the default at power-up: • A read operation to addresses 0 outputs the value of the non-volatile IVR. • A write operation to addresses 0 writes the same value to the WR and IVR of the corresponding DCP. When the byte at address 2 is 80h (128 decimal): • A read operation to addresses 0 outputs the value of the volatile WR. • A write operation to addresses 0 only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. 00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections. FN8090 Rev.3.01 Jun 5, 2020 Page 9 of 14 ISL95810 any command until this condition is met (see Figure 16). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. The ISL95810 is pre-programed with 80h in the IVR. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 2 - Access Control 1 Reserved 0 IVR WR NOTE: WR: Wiper Register, IVR: Initial value Register. I2C Serial Interface The ISL95810 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations; therefore, the ISL95810 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16 on page 10). On power-up of the ISL95810 the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95810 continuously monitors the SDA and SCL lines for the START condition and does not respond to All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An Acknowledge (ACK), is a software convention that indicates a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17 on page 11). The ISL95810 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and responds again after successful receipt of an Address Byte. The ISL95810 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB in the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (see Table 2). TABLE 2. IDENTIFICATION BYTE FORMAT 0 1 0 1 0 (MSB) 0 0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 16. VALID DATA CHANGES, START, AND STOP CONDITIONS FN8090 Rev.3.01 Jun 5, 2020 Page 10 of 14 ISL95810 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA S T A R T IDENTIFICATION BYTE ADDRESS BYTE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 SIGNALS FROM THE ISL95810 S T O P DATA BYTE A C K A C K A C K FIGURE 18. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA SIGNALS FROM THE SLAVE IDENTIFICATION BYTE WITH R/W=0 S T A IDENTIFICATION R BYTE WITH T R/W=1 ADDRESS BYTE 0 1 0 1 0 0 0 0 S T O P A C K 0 1 0 1 0 0 0 1 0 0 0 0 0 0 A C K A C K A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 19. READ SEQUENCE FN8090 Rev.3.01 Jun 5, 2020 Page 11 of 14 ISL95810 Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95810 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95810 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95810 enters its standby state (see Figure 18 on page 11). The byte at address 02h determines if the Data Byte is to be written to volatile and/or non-volatile memory (see “Memory Description” on page 9). Data Protection The WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW) the device ignores Data Bytes of a Write Operation, does not respond to the Data Bytes with an ACK, and instead, goes to its standby state waiting for a new START condition. Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the Last Significant Bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory. Read Operation A Read operation consist of a three byte instruction followed by one or more Data Bytes (see Figure 19 on page 11). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL95810 responds with an ACK. Then the ISL95810 then transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (see Figure 19). The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory (see “Memory Description” on page 9.) A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION Jun 5, 2020 3.01 Added thermal information to document. Sep 6, 2019 3.00 Updated links throughout. Added Related Literature section. Updated ordering information table by removing retired parts, adding tape and reel information, added ISL95810UART8Z-T (-40°C to +105°C temperature option), updating notes, and moving to second page. Updated the typical value for the Resistance Temperature Coefficient from ±45 to ±165 on page 4. Added extended range (-40°C to +105°C temperature option) to the recommended operating conditions section. Updated Notes 8 and 14 on page 6. Added Notes 11 and 17. Updated Figures 1 through 11. Added note to DCP Description section. Updated M8.118 to the latest revision changes are as follows: - Updated to new format by adding land pattern and moving dimensions from table onto drawing. - Corrected lead width dimension in side view 1 from “0.25 - 0.036" to “0.25 - 0.36". Replaced POD L8.3X3B with POD L8.3X3A. Updated disclaimer. FN8090 Rev.3.01 Jun 5, 2020 CHANGE Page 12 of 14 ISL95810 Package Outline Drawings For the most recent package outline drawing, see M8.118. M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN8090 Rev.3.01 Jun 5, 2020 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 13 of 14 ISL95810 For the most recent package outline drawing, see L8.3x3A. L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 5/15 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 PIN #1 INDEX AREA 0.10 C 0.75 ±0.05 6X 0.65 C 0.08 C 1 SIDE VIEW 6 1.50 ±0.10 8 8X 0.30 ±0.05 8X 0.30 ± 0.10 2.30 ±0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: FN8090 Rev.3.01 Jun 5, 2020 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. Page 14 of 14 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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