DATASHEET
ISL98608IIH
FN8724
Rev.2.01
Dec 7, 2021
High Efficiency Single Inductor Positive/Negative Power Supply
Features
The ISL98608IIH is a high efficiency power supply for small
size displays, such as smart phones and tablets requiring
±supply rails. It integrates a boost regulator, LDO, and inverting
charge pump that are used to generate two output rails:
+5V (default) and -6 (default). The ±5V output voltages can be
adjusted from ±4.5V up to ±7V with 50mV steps using the I2C
interface.
• Two outputs:
- VP = +5V (default)
- VN = -5V (default)
• 2.5V to 5.5V input voltage range
• ±4.5 to ±7V wide output range
The device integrates synchronous rectification MOSFETs for
the boost regulator and inverting charge pump, which
maximizes conversion efficiency.
• >89% efficiency with 12mA load between VP and VN
• 18mm2 solution PCB area
The ISL98608IIH integrates all compensation and feedback
components, which minimizes BOM count and reduces the
solution PCB size to 18mm2.
• Fully integrated FETs for synchronous rectification
• Integrated compensation and feedback circuits
• I2C adjustable output voltages and settings
The input voltage range, high efficiency operation and very low
shutdown current make the device ideal for use in single cell
Li-ion battery operated applications.
• Integrated VP/VN discharge resistors
• 1µA shutdown supply current
• Programmable turn-on and turn-off sequencing
The ISL98608IIH is offered in a 1.744mm x1.744mm WLCSP
package, and the device is specified for operation across the
-40°C to +85°C ambient temperature range.
• 1.744mm x1.744mm, 4x4 array WLCSP with 0.4mm pitch
Applications
• TFT-LCD smart phone displays
• Small size/handheld displays
• Hi-Fi audio amplifier supply
Typical Application Circuits
VIN
2.5V TO 5.5V
L1
CIN
VIN
LXP
SCL
VBSTCP
VBST
CVBST
CCP
CVN
-5V
LCD PANEL
CP
SDA
PROCESSOR
ENP
ENN
ISL98608IIH
CN
VN
NEGATIVE SUPPLY
POSITIVE SUPPLY
+5V
VSUB
VP
AGND
PGND
CVP
FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD SMART PHONE DISPLAY
FN8724 Rev.2.01
Dec 7, 2021
Page 1 of 33
© 2015 Renesas Electronics
ISL98608IIH
Typical Application Circuits (Continued)
VIN
2.5V TO 5.5V
L1
VIN
CIN
LXP
SCL
VBSTCP
SDA
VBST
CVBST
PROCESSOR
ENP
ENN
CP
ISL98608IIH
CCP
CN
CVN
NEGATIVE SUPPLY
VN
VSUB
AMPLIFIER
VP
POSITIVE SUPPLY
AGND
PGND
CVP
FIGURE 2. TYPICAL APPLICATION CIRCUIT: HI-FI AUDIO AMPLIFIER POWER SUPPLY
Block Diagram
VIN
LXP
VIN
VBSTCP
CP
VBST
VBST
PWM/
PFM
LOGIC
OSCILLATOR
VN
CN
LOGIC
PGND
VN
+60%
VSUB
SCL
SDA
ENP
ENN
PGND
CURRENT LIMIT
VREF
2
I C CONTROL
UVP
UVP
GM
COMP
COMP
GM
-60%
VREF
DAC
DAC
EN/ SEQUENCING
SETTINGS
LDO
VP
DAC
FIGURE 3. BLOCK DIAGRAM
FN8724 Rev.2.01
Dec 7, 2021
Page 2 of 33
ISL98608IIH
Table of Contents
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Application Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Descriptions and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
17
18
18
19
19
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Display Power Supply Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VP and VN Headroom Voltage and Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Charge Pump Operation (VN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VN and VBST PFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VP/VN Output Hi-Z Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Timing Control Options for VP and VN Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
22
22
23
23
26
28
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
28
29
General Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ISL98608IIH Specific Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ISL98608IIH Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FN8724 Rev.2.01
Dec 7, 2021
Page 3 of 33
ISL98608IIH
Application Circuit Diagram
L1
2.2µH OR 4.7µH
CVBST
4.7µF/10V/0603
OR
10µF/10V/0402
VIN
1
A
B
VIN
C
CVIN
4.7µF/10V/0603
OR
10µF/10V/0402
D
2
PGND
3
LXP
4
VBST
VBSTCP
AGND
ENN
VP
CP
VIN
SDA
SCL
PGNDCP
ENP
VSUB
VN
CVP
4.7µF/10V/0603
OR
10µF/10V/0402
CCP-CN
4.7µF/10V/0603
OR
10µF/10V/0402
PROCESSOR
CN
CVN
4.7µF/10V/0603
OR
10µF/10V/0402
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE DESCRIPTION
(RoHS Compliant)
ISL98608IIHZ-T
608H
ISL98608HEVAL1Z
Evaluation Board
16 Ball (4x4 bump, 0.4mm pitch) WLCSP
PKG.
DWG. #
W4x4.16G
CARRIER TYPE
(Note 1)
TEMP RANGE
Reel, 3k
-40 to +85°C
NOTES:
1. See TB347 for details on reel specifications.
2. These Pb-free WLCSP packaged products employ special Pb-free material sets; molding compounds/die attach materials and SnAgCu - e1 solder ball
terminals, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free WLCSP packaged products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL98608IIH product information. For more information on MSL, see TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL98608
ISL98608IIH
FN8724 Rev.2.01
Dec 7, 2021
VIN
(V)
MAXIMUM OUTPUT CURRENT (mA)
VBST VOLTAGE
(V)
VP VOLTAGE
(V)
VN VOLTAGE
(V)
2.5 to 5
100
5.65
5.5
-5.5
2.5 to 5.5
200
5.4
5
-5
Page 4 of 33
ISL98608IIH
Pin Configuration
ISL98608IIH
(16 BUMP, 4x4 ARRAY, 0.4MM PITCH WLCSP)
TOP VIEW
1.744 mm
1
2
3
A
PGND
LXP
VBST
VBSTCP
B
AGND
ENN
VP
CP
C
VIN
SDA
SCL
PGNDCP
D
ENP
VSUB
1.744 mm
VN
4
CN
Pin Descriptions
PIN NUMBER
PIN NAME
A1
PGND
DESCRIPTION
A2
LXP
Switch node for boost converter. Connect an inductor between the VIN and LXP pins for boost converter
operation.
A3
VBST
Boost Converter Output. The boost converter output supplies the power to the negative charge pump
and LDO. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground.
A4
VBSTCP
B1
AGND
B2
ENN
Power ground for the boost converter.
Charge pump input. This pin must be connected to VBST on the PCB, so that the boost regulator
provides the input voltage supply for the charge pump.
Analog Ground
VBST and VN enable input. (Note 4)
B3
VP
Positive regulator output. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground.
B4
CP
Charge pump flying capacitor positive connection. Place a capacitor between CP and CN.
C1
VIN
Input supply voltage. Connect a 4.7µF/0603 or 10µF/0402 bypass capacitor from VIN to ground.
C2
SDA
Serial data connection for I2C Interface. If this pin not used, connect this pin to VIN.
C3
SCL
Serial data connection for I2C Interface. If this pin not used, connect this pin to VIN.
C4
PGNDCP
Power ground for the VN regulator.
D1
ENP
VBST and VP enable input. (Note 4)
D2
VSUB
Substrate connection. VSUB must be the most negative potential on the IC, connect VSUB to VN.
D3
VN
Negative charge pump output. Connect a 4.7µF/0603 or 10µF/0402 capacitor to ground. Connecting
either two 4.7µF/0603 or 10µF/0402 capacitors to ground will lower the negative charge pump
output voltage ripple.
D4
CN
Charge pump flying capacitor negative connection. Place a capacitor between CP and CN.
NOTE:
4. This pin has 1MΩ (typical) pull-down to AGND.
FN8724 Rev.2.01
Dec 7, 2021
Page 5 of 33
ISL98608IIH
V
Absolute Maximum Ratings
Thermal Information
VBST, VBSTCP, CP, VP to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8.5V
VN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -8.5V
VIN, SCL, SDA, ENN, ENP to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
LXP to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VBST + 0.3V
CN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VN - 0.3V to PGND + 0.3V
Maximum Average Current
Out of VBST Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Into LXP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Into CN, CP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1A
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 3000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101F) . . . . . . . . . . . 1000V
Latch-up (Tested per JESD78D; Class II) . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JB (°C/W)
4x4 Bump 0.4mm pitch WLCSP (Notes 5, 6)
76
18
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +7V
VN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-4.5V to -7V
VBST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.65V to +7.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
6. For JB, the board temperature is taken on the board near the edge of the package, on a copper trace at the center of one side. See TB379,
Electrical Specifications
VIN = 3.7V, unless otherwise noted. Typical specifications are characterized at TA = +25°C unless
otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 7)
MAX
(Note 7) UNIT
TYP
GENERAL
VIN
VIN Supply Voltage Range
2.5
VIN Minimum Supply Voltage (Note 9) At 200mA
IIN
ISHUTDN
VIN Supply Current
ENP = ENN = SDA = SCL = 3.7V
Enabled, LXP not switching
VIN Supply Current when Shutdown
ENP = ENN = SDA = SCL = 0V
VUVLO
Undervoltage Lockout Threshold
VIN rising
VUVLO_HYS
Undervoltage Lockout Hysteresis
5.5
V
3
V
700
µA
1
µA
2.32
2.44
V
216
mV
BOOST REGULATOR (VBST)
VVBST
VBST Output Voltage
Register 0x06 = 0x00, 10mA load
VVBSTA
VBST Output Voltage Accuracy
2.5V < VIN < 4.6V, Register 0x06 = 0x00
VVBSTR
VBST Output Voltage Programmable Programmable in 50mV steps
Range
ILIM_VBST
Boost nFET Current Limit
5.4
V
-2.5
2.5
%
4.65
7.3
V
1.2
1.45
1.7
A
VBST Output Current
2.5V < VIN VUVLO
0.59
0.85
ms
VN = -5V, Register 0x08 = 0x00 no load
-5
NEGATIVE REGULATOR (VN)
VVN
VN Output Voltage
FN8724 Rev.2.01
Dec 7, 2021
V
Page 6 of 33
ISL98608IIH
Electrical Specifications
VIN = 3.7V, unless otherwise noted. Typical specifications are characterized at TA = +25°C unless
otherwise noted. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
VVNR
DESCRIPTION
TEST CONDITIONS
MIN
(Note 7)
MAX
(Note 7) UNIT
TYP
VN Output Voltage Programmable
Range
Programmable in 50mV steps
-7
-4.5
V
VACC_VN
VN Output Voltage Accuracy
VN = -5V, Register 0x08 = 0x00, Register 0x06 = 0x00,
-100mA < ILOAD_VN < 0mA
-2
2
%
fSW_VN
Charge Pump Switching Frequency
CP Frequency = default, 50% duty cycle
1.3
1.6
MHz
Charge Pump Leakage Current
CP pin, CP = 6V, ENN = 0V
10
µA
VN Discharge Resistance
VN = -1V
VN Soft-Start Time
CVN = 10µF (not derated), VN = -5V, Register
0x08 = 0x00, Register 0x05 b7 = 0
IL_CP
RDCH_VN
tSS_VN
1.45
35
Ω
1.96
2.39
ms
POSITIVE REGULATOR (VP)
VVP
VP Output Voltage
VP = 5V, Register 0x09 = 0x00, no load
VVPR
VP Output Voltage Programmable
Range
Programmable in 50mV steps
4.5
7
V
VACC_VP
VP Output Voltage Accuracy
VP = 5V, Register 0x09 = 0x00, Register 0x06 = 0x00,
0mA < ILOAD_VP < 100mA
-2
2
%
VDRP_VP
VP Dropout Voltage
ILOAD_VP = 100mA
100
mV
IL_VP
VP Leakage Current
VP pin, VP = 0V, ENP = 0V
2
µA
VP Discharge Resistance
VP = 1V
VP Soft-Start
CVP = 10µF (not derated), VP = 5V, Register 0x05
b7 = 0
1.23
TOFF
Thermal Shutdown Temperature
Die temperature (rising) when the device will
disable/shutdown all outputs until it cools by THYS°C
150
°C
THYS
Thermal Shutdown Hysteresis
Die temperature below TOFF°C when the device will
re-enable the outputs after shutdown
20
°C
RDCH_VP
tSS_VP
5
V
80
Ω
1.53
ms
PROTECTION
VUVP_VBST
70% of VBST
V
VUVP_VP
VBST Undervoltage Limit
VP Undervoltage Protection
Threshold
60% of VP
V
VUVP_VN
VN Undervoltage Protection
Threshold
60% of VN
V
VUVDELAY
Undervoltage Delay
Undervoltage delay for VBST, VN, VP
100
µs
VIL
Logic Input Low Voltage
ENN, ENP, SCL, SDA
VIH
Logic Input High Voltage
ENN, ENP, SCL, SDA
fCLK
I2C SCL Clock Frequency
(Note 8)
Debounce Time
ENN, ENP
10
µs
Internal Pull-Down Resistance
ENN, ENP
1
MΩ
LOGIC/DIGITAL
td
REN
0.4
V
V
1.1
400
kHz
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. For more detailed information regarding I2C timing characteristics refer to Table 2 on page 17.
9. Parameters established by bench testing and/or design. Not production tested.
FN8724 Rev.2.01
Dec 7, 2021
Page 7 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted.
90
88
84
82
80
VP (V)
EFFICIENCY (%)
86
VIN = 4.35V
VIN = 3.7V
78
VIN = 3V
76
74
72
70
0
0.04
0.08
0.12
0.16
0.2
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
2.5V
5V
3.7V
0
10
20
FIGURE 4. DISPLAY POWER SYSTEM EFFICIENCY, VP/VN = ±5V
VN (V)
40
50
60
REGISTER 0x09(dec)
LOAD (A)
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
30
FIGURE 5. VP OUTPUT VOLTAGE RANGE
CH2 = 200mV/DIV (AC), CH4 = 50mA/DIV
VBST
3.7V
2.5V
VBST OUTPUT CURRENT
5V
0
10
20
30
40
50
60
REGISTER 0x08 (dec)
FIGURE 6. VN OUTPUT VOLTAGE RANGE
40µs/DIV
FIGURE 7. VBST LOAD TRANSIENT, VBST = 5.15V
CH2 = 50mV/DIV (AC), CH3 = 2V/DIV
CH4 = 200mA/DIV
6.1
6.0
VBST (V)
5.9
VBST
5.8
5.7
5.6
LX
5.5
5.4
5.3
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
VIN (V)
FIGURE 8. VBST, VIN HEADROOM TRACKING, VBST = 5.4V
FN8724 Rev.2.01
Dec 7, 2021
INDUCTOR CURRENT
2µs/DIV
FIGURE 9. VBST RIPPLE, 10mA LOAD, VBST = 5.4, VIN = 3V
Page 8 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
CH2 = 50mV/DIV (AC), CH3 = 2V/DIV
CH4 = 200mA/DIV
CH2 = 50mV/DIV (AC), CH3 = 2V/DIV
CH4 = 200mA/DIV
VBST
VBST
LX
LX
INDUCTOR CURRENT
INDUCTOR CURRENT
500ns/DIV
500ns/DIV
FIGURE 10. VBST RIPPLE, 450mA LOAD, VBST = 5.4V, VIN = 3V
FIGURE 11. VBST RIPPLE, 10mA LOAD, VBST = 5.4V, VIN = 3.7V
VBST
CH2 = 50mV/DIV (AC), CH3 = 2V/DIV
CH4 = 200mA/DIV
CH2 = 50mV/DIV (AC), CH3 = 2V/DIV
CH4 = 200mA/DIV
VBST
INDUCTOR CURRENT
INDUCTOR CURRENT
LX
LX
500ns/DIV
500ns/DIV
FIGURE 12. VBST RIPPLE, 10mA LOAD, VBST = 5.65V
FIGURE 13. VBST RIPPLE, 150mA LOAD, VBST = 5.65V
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
FIGURE 14. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,
VIN = 3V
FN8724 Rev.2.01
Dec 7, 2021
20µs/DIV
FIGURE 15. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,
VIN = 3V
Page 9 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
1µs/DIV
FIGURE 16. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,
VIN = 3V
FIGURE 17. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,
VIN = 3V
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
20µs/DIV
FIGURE 18. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,
VIN = 3.7V
FIGURE 19. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,
VIN = 3.7V
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
1µs/DIV
FIGURE 20. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,
VIN = 3.7V
FIGURE 21. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,
VIN = 3.7V
FN8724 Rev.2.01
Dec 7, 2021
Page 10 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VN
VN
20µs/DIV
FIGURE 22. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,
VIN = 4.35V
20µs/DIV
FIGURE 23. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,
VIN = 4.35V
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
1µs/DIV
20µs/DIV
FIGURE 24. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,
VIN = 4.35V
FIGURE 25. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 200mA LOAD,
VIN = 4.35V
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
FIGURE 26. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 5mA LOAD,
VIN = 5V
FN8724 Rev.2.01
Dec 7, 2021
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
20µs/DIV
FIGURE 27. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 20mA LOAD,
VIN = 5V
Page 11 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
CH1 = 20mV/DIV (AC), CH3 = 50mV/DIV (AC)
VP
VP
VN
VN
20µs/DIV
1µs/DIV
FIGURE 28. VP/VN (±5V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD,
VIN = 5V
FIGURE 29. VP/VN (±7V) OUTPUT VOLTAGE RIPPLE, 100mA LOAD
CH1 = 50mV/DIV (AC)
CH3 = 100mV/DIV (AC)
CH4 = 100mA/DIV
VP
CH1 = 50mV/DIV (AC)
CH3 = 100mV/DIV (AC)
CH4 = 100mA/DIV
VP
VN
VN
OUTPUT CURRENT BETWEEN VP AND VN
OUTPUT CURRENT BETWEEN VP AND VN
80µs/DIV
FIGURE 30. VP AND VN LOAD TRANSIENT, VP/VN = ±5V, VIN = 3.7V
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
VP
80µs/DIV
FIGURE 31. VP AND VN LOAD TRANSIENT, VP/VN = ±5V, VIN = 4.35V
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
VP
VN
VN
INDUCTOR CURRENT
INDUCTOR CURRENT
1ms/DIV
1ms/DIV
FIGURE 32. VP AND VN (±5V) SOFT-START AT 2.5V INPUT VOLTAGE,
VP/VN SEQUENCED (Reg 0x04 = 0)
FIGURE 33. VP AND VN (±5V) SOFT-START AT 3.7V INPUT VOLTAGE,
VP/VN SEQUENCED (Reg 0x04 = 0)
FN8724 Rev.2.01
Dec 7, 2021
Page 12 of 33
ISL98608IIH
Typical Performance Curves
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
VP
VP
VN
INDUCTOR CURRENT
VN
INDUCTOR CURRENT
1ms/DIV
1ms/DIV
FIGURE 34. VP AND VN (±5V) SOFT-START AT 5V INPUT VOLTAGE,
VP/VN SEQUENCED (Reg 0x04 = 0)
FIGURE 35. VP AND VN (±5V) SHUTDOWN, VP/VN SEQUENCED
(Reg 0x05 = 0)
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
VP
VP
VN
VN
INDUCTOR CURRENT
INDUCTOR CURRENT
1ms/DIV
1ms/DIV
FIGURE 36. VP AND VN (±5V) SOFT-START AT 2.5V INPUT VOLTAGE,
VP/VN START TOGETHER (Reg 0x04 = 1)
FIGURE 37. VP AND VN (±5V) SOFT-START AT 3.7V INPUT VOLTAGE,
VP/VN START TOGETHER (Reg 0x04 = 1)
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
CH2 = 2V/DIV, CH3 = 2V/DIV, CH4 = 500mA/DIV
VP
VP
VN
VN
INDUCTOR CURRENT
INDUCTOR CURRENT
1ms/DIV
FIGURE 38. VP AND VN (±5V) SOFT-START AT 5V INPUT VOLTAGE,
VP/VN START TOGETHER (Reg 0x04 = 1)
FN8724 Rev.2.01
Dec 7, 2021
1ms/DIV
FIGURE 39. VP AND VN (±5V) SHUTDOWN, VP/VN SHUTDOWN
TOGETHER (Reg 0x05 = 1)
Page 13 of 33
ISL98608IIH
Typical Performance Curves
-4.90
5.10
-4.92
5.08
-4.94
5.06
-4.96
5.04
-4.98
5.02
VP (V)
VN (V)
TA = +25°C, VIN = 3.7V, L1 = 1239AS-H-2R2M (2.5mmx2mm), CVBST = 10µF/0402,
CVP = 10µF/0402, CVN = 2 x 10µF/0402, CCP = 10µF/0402 unless otherwise noted. (Continued)
-5.00
-5.02
-5.04
VIN = 3.7V
-5.06
VIN = 4.35V
VIN = 3V
5.00
4.98
4.96
4.94
-5.08
VIN = 4.35V
VIN = 3.7V
VIN = 3V
4.92
-5.10
0.01
0.05
0.09
0.13
0.17
LOAD (A)
FIGURE 40. VN LOAD REGULATION, -5V
FN8724 Rev.2.01
Dec 7, 2021
0.21
4.90
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21
LOAD (A)
FIGURE 41. VP LOAD REGULATION, 5V
Page 14 of 33
ISL98608IIH
Application Information
50mV resolution. Similar to the VP regulator, the VN regulator
also integrates a discharge resistor and the value of discharge
resistor is 35Ω. The VN is an ideal solution for negative supply
due to low ripple, fast load transient response and higher
efficiency.
Description
The ISL98608IIH is a display PMIC and can be used to supply
power to an LCD display. Figure 42 shows the typical system
application block diagram. For display power, the ISL98608IIH
integrates a boost regulator (VBST), low dropout linear regulator
(VP) and an inverting charge pump regulator (VN). The boost
voltage is generated from a battery voltage ranging from 2.5V to
5.5V and boost regulator output can be programmed from 4.60V
to 7.3V. The VBST regulator integrates low-side NFET and
high-side PFET MOSFETs for synchronous rectification.
Modes of Operation
SHUTDOWN MODE
The ISL98608IIH is in shutdown mode when the enable pins,
namely ENN and ENP are pulled low. When the ENN and ENP
pins are all pulled low, all the regulators are powered off and the
IC is placed in shutdown mode where the current consumed from
the battery is only 1µA (typical).
The output voltage of VBST is the input to the linear regulator
(VP). The VBST output and VP regulator input are connected
internally in the IC. The VP regulator supplies a positive voltage in
the range of +4.5V to +7V with 50mV resolution. An 80Ω
discharge resistor discharges residual voltage when the poweroff sequence is initiated, which helps avoid ghost image issues.
The LDO is an ideal solution for the positive supply due to its low
ripple, fast load transient response, higher efficiency and low
dropout voltage.
OPERATING MODE
The IC is in normal operating mode when the ENN and ENP are
pulled high and the current consumed from the battery is only
1mA (excluding VBST and VN switching current). After the
ENN/ENP signals are pulled high, VBST, VP and VN go through
power-on sequencing. Refer to “Power-On/Off Sequence” on
page 23 for more details.
The VN voltage is generated by a regulated inverting charge
pump topology. VBSTCP is the input to the inverting charge
pump, which should be connected to the VBST pin on the PCB.
The VN regulator supplies negative voltage from -7V to -4.5V with
LCD PANEL/HI-Fi AUDIO AMPLIFIER
2.5V to 5.5V
+
-
VP
VN
VIN
ISL98608IIH
ENN
APPLICATIONS
PROCESSOR
ENP
I2C
FIGURE 42. TYPICAL SYSTEM APPLICATION BLOCK DIAGRAM
FN8724 Rev.2.01
Dec 7, 2021
Page 15 of 33
ISL98608IIH
START
VIN < ~2.0V
YES
NO
I2C Reboot
Reset
Shutdown Mode
NO
VIN >
UVLO(2.3V)
YES
ENP or ENN =
HIGH
NO
YES
VBST EN
bit = HIGH
NO
YES
Soft-Start VBST
ENP and VP
EN bit = HIGH
ENN and VN
EN bit = HIGH
YES
YES
YES
Soft-Start VP
Is VP Soft
Start Active
NO
VN Pre-charging
Optional 2ms delay
2ms delay
Soft-Start VN
Normal VP Mode
YES
ENP and VP
EN bit = HIGH
NO
VP UVP
VN UVP
YES
YES
NO
EN VP Discharge
Normal VN Mode
YES
NO
NO
Optional 2ms delay
UVP = VBST, VP and VN Power-OFF
Wait 2ms
YES
NO
Disable VP
ENN and VN
EN bit = HIGH
ENP and ENN
= LOW
YES
Disable VN and
enagage discharge
NO
VP and VN
disabled?
YES
Disable VBST
Optional 2ms delay : If register 0x02 b is set to
“1” then 2ms delay is performed on both VP and VN.
FIGURE 43. START-UP FUNCTIONAL BLOCK DIAGRAM
FN8724 Rev.2.01
Dec 7, 2021
Page 16 of 33
ISL98608IIH
I2C Digital Interface
STOP condition is signified by a LOW to HIGH transition on the
SDA line while SCL is HIGH. See timing specifications in Table 2.
The ISL98608IIH uses a standard I2C interface bus for
communication. The two-wire interface links a Master(s) and
uniquely addressable Slave devices. The Master generates clock
signals and is responsible for initiating data transfers. The serial
clock is on the SCL line and the serial data (bidirectional) is on
the SDA line. The ISL98608IIH supports clock rates up to 400kHz
(Fast mode) and is backwards compatible with standard 100kHz
clock rates (Standard mode).
The Master always initiates START and STOP conditions. After a
START condition, the bus is considered “busy.” After a STOP
condition, the bus is considered “free.” The ISL98608IIH also
supports repeated STARTs, where the bus will remain busy for
continued transaction(s).
DATA VALIDITY
The data on the SDA line must be stable (clearly defined as HIGH
or LOW) during the HIGH period of the clock signal. The state of
the SDA line can only change when the SCL line is LOW (except to
create a START or STOP condition). See timing specifications in
Table 2.
The SDA and SCL lines must be HIGH when the bus is free - not in
use. An external pull-up resistor (typically 2.2kΩto 4.7kΩ) or
current source is required for SDA and SCL.
The ISL98608IIH meets standard I2C timing specifications, see
Figure 44 and Table 2, which show the standard timing
definitions and specifications for I2C communication.
The voltage levels used to indicate a logical ‘0’ (LOW) and logical
‘1’ (HIGH) are determined by the VIL and VIH thresholds,
respectively, see the “Electrical Specifications” table on page 7.
START AND STOP CONDITION
All I2C communication begins with a START condition (indicating
the beginning of a transaction) and ends with a STOP condition
(signaling the end of the transaction).
BYTE FORMAT
Every byte transferred on SDA must be 8 bits in length. After
every byte of data sent by the transmitter there must be an
Acknowledge bit (from the receiver) to signify that the previous
8 bits were transferred successfully. Data is always transferred
on SDA with the Most Significant Bit (MSB) first. See
“Acknowledge (ACK)” on page 18.
A START condition is signified by a HIGH to LOW transition on the
serial data line (SDA) while the serial clock line (SCL) is HIGH. A
tBUF
VIH
SDA
VIL
tSU:STA
tr
tHD:STA
tf
tr
tSU:STO
tf
VIH
SCL
VIL
START
tSU:DAT
tHD:DAT
STOP
START
FIGURE 44. I2C TIMING DEFINITIONS
TABLE 2. I2C TIMING CHARACTERISTICS
FAST-MODE
PARAMETER
SCL Clock Frequency
STANDARD-MODE
SYMBOL
MIN
MAX
MIN
MAX
UNIT
fSCL
0
400
0
100
kHz
Set-Up Time for a START Condition
tSU:STA
0.6
-
4.7
-
µs
Hold Time for a START Condition
tHD:STA
0.6
-
4.0
-
µs
Set-Up Time for a STOP Condition
tSU:STO
0.6
-
4.0
-
µs
tBUF
1.3
-
4.7
-
µs
Data Set-Up Time
tSU:DAT
100
-
250
-
ns
Data Hold Time
tHD:DAT
0
-
0
-
µs
Rise Time of SDA and SCL (Note 10)
tr
20 + 0.1Cb
300
-
1000
ns
Fall Time of SDA and SCL (Note 10)
tf
20 + 0.1Cb
300
-
300
ns
Capacitive Load on Each Bus Line (SDA/SCL)
Cb
-
400
-
400
pF
Bus Free Time between a STOP and START Condition
NOTE:
10. Cb = Total capacitance of one bus line in pF.
FN8724 Rev.2.01
Dec 7, 2021
Page 17 of 33
ISL98608IIH
ACKNOWLEDGE (ACK)
Each 8-bit data transfer is followed by an Acknowledge (ACK) bit
from the receiver. The Acknowledge bit signifies that the previous
8 bits of data was transferred successfully (master to slave or
slave to master).
When the Master sends data to the Slave (e.g., during a WRITE
transaction), after the 8th bit of a data byte is transmitted, the
Master tri-states the SDA line during the 9th clock. The Slave
device acknowledges that it received all 8 bits by pulling down
the SDA line, generating an ACK bit.
When the Master receives data from the Slave (e.g., during a data
READ transaction), after the 8th bit is transmitted, the Slave
tri-states the SDA line during the 9th clock. The Master
acknowledges that it received all 8 bits by pulling down the SDA
line, generating an ACK bit.
NOT ACKNOWLEDGE (NACK)
A Not Acknowledge (NACK) is generated when the receiver does
not pull-down the SDA line during the acknowledge clock (i.e.,
SDA line remains HIGH during the 9th clock). This indicates to the
Master that it can generate a STOP condition to end the
transaction and free the bus.
A NACK can be generated for various reasons, for example:
• After an I2C device address is transmitted, there is NO receiver
with that address on the bus to respond.
• The receiver is busy performing an internal operation (e.g.,
reset, recall, etc) and cannot respond.
• The Master (acting as a receiver) needs to indicate the end of a
transfer with the Slave (acting as a transmitter).
DEVICE ADDRESS AND R/W BIT
Data transfers follow the format shown in Figures 46 and 47 on
page 19. After a valid START condition, the first byte sent in a
transaction contains the 7-bit Device (Slave) Address plus a
direction (R/W) bit. The Device Address identifies which device
(of up to 127 devices on the I2C bus) the Master wishes to
communicate with.
After a START condition, the ISL98608IIH monitors the first 8 bits
(Device Address Byte) and checks for its 7-bit Device Address in
the MSBs. If it recognizes the correct Device Address, it will ACK
and becomes ready for further communication. If it does not see
its Device Address, it will sit idle until another START condition is
issued on the bus.
FN8724 Rev.2.01
Dec 7, 2021
To access the ISL98608IIH, the 7-bit Device Address is 0x29
(0101001x), located in MSB bits . The eighth bit of the
Device Address byte (LSB bit ) indicates the direction of
transfer, READ or WRITE (R/W). A “0” indicates a WRITE
operation - the Master will transmit data to the ISL98608IIH
(receiver). A “1” indicates a Read operation - the Master will
receive data from the ISL98608IIH (transmitter) (see Figure 45).
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
1
0
0
1
R/W
DEVICE ADDRESS = 0X29
READ = 1
WRITE = 0
FIGURE 45. DEVICE ADDRESS BYTE FORMAT
Write Operation
A WRITE sequence requires an I2C START condition, followed by
a valid Device Address Byte with the R/W bit set to ‘0’, a valid
Register Address Byte, a Data Byte and a STOP condition. After
each valid byte is sent, the ISL98608IIH (slave) responds with an
ACK. When the Write transaction is completed, the Master should
generate a STOP condition. For sent data to be latched by the
ISL98608IIH, the STOP condition should occur after a full byte (8
bits) is sent and ACK. If a STOP is generated in the middle of a
byte transaction, the data will be ignored. See Figure 46 on
page 19 for the ISL98608IIH I2C Write protocol.
Read Operation
A READ sequence requires the Master to first write to the
ISL98608IIH to indicate the Register Address/pointer to read
from. First, Send a START condition, followed by a valid Device
Address Byte with the R/W set to ‘0’ and then a valid Register
Address Byte. Then the Master generates either a Repeat START
condition or a STOP condition followed by a new START condition
and a valid Device Address Byte with the R/W bit set to ‘1’. Then
the ISL98608IIH is ready to send data to the Master from the
requested Register Address.
The ISL98608IIH sends out the Data Byte by asserting control of
the SDA pin while the Master generates clock pulses on the SCL
pin. When transmission of the desired data is complete, the
Master generates a NACK condition followed by a STOP condition
and this completes the I2C Read sequence. See Figure 47 on
page 19 for the ISL98608IIH I2C Read protocol.
Page 18 of 33
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
C
K
DATA
A
C
K
REGISTER
POINTER
A
W
A
DEVICE
ADDRESS
START
SDA
(FROM
MASTER)
C
K
ISL98608IIH
STOP
7 6 5 4 3 2 1 0
DEVICE ADDRESS = 0X29
WRITE
DATA
SDA
(FROM
SLAVE)
A
SCL
(FROM
MASTER)
A
A
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
REGISTER
POINTER
C
K
W
A
DEVICE
ADDRESS
A
START
SDA
(FROM
MASTER)
C
K
FIGURE 46. I2C WRITE TIMING DIAGRAM
STOP
NOTE: First send register pointer to
indicate the READ-back starting location
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0
DEVICE ADDRESS = 0X29
SDA
(FROM
SLAVE)
A
R
SDA
(FROM
SLAVE)
SCL
(FROM
MASTER)
DATA
7 6 5 4 3 2 1 0
STOP
A
DEVICE ADDRESS = 0X29
READ
DATA
C
K
DEVICE
ADDRESS
C
START
K
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
N
A
SDA
(FROM
MASTER)
A
This STOP condition is optional (not
required) to do READ-back. The device
also supports repeated STARTs.
SCL
(FROM
MASTER)
A
WRITE
REGISTER
POINTER
(NO ACK)
A 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A
FIGURE 47. I2C READ TIMING DIAGRAM
Register Descriptions and Addresses
FAULT
The “Register Map” on page 21 contains the detailed register
map, with descriptions and addresses for ISL98608IIH registers.
Each volatile register is one byte (8-bit) in size. When writing data
to adjust register settings using I2C, the data is latched-in after
the 8th bit (LSB) is received.
The “FAULT” register (Register Address 0x04) can be used to read
back the current fault status of the IC. The fault conditions that
can be read back by I2C are VBST undervoltage fault, VP
undervoltage fault, VN undervoltage fault and over-temperature
protection (OTP) fault.
The ISL98608IIH has default register settings that are applied at
IC power-up, and in some cases, updated based on fuse values at
first enable. The default register settings are indicated with BOLD
face text.
If FAULT register bit (OTP status bit) is latched high for an
OTP fault, it can be reset by simultaneously cycling ENP and ENN.
NOTE: To clear/reset all the volatile registers to the default values, power
cycle VIN or clear the register 0x04 bit .
Register Functions
The ISL98608IIH has various registers that can be used to adjust
and control IC operating voltages, modes, thresholds and
sequences.
FN8724 Rev.2.01
Dec 7, 2021
If FAULT register bit (VBST status bit) is latched high for a
VBST undervoltage fault, it can be reset by cycling ENP and ENN
together.
If FAULT register bit (VN status bit) is latched high for a VN
undervoltage fault, it can be reset by cycling ENN.
If FAULT register bit (VP status bit) is latched high for a VP
undervoltage fault, it can be reset by cycling ENP.
Page 19 of 33
ISL98608IIH
All fault bits can be cleared by cycling VIN or with a software
reboot (clearing register 0x04 bit). This will reset the entire
part to default settings and disable all outputs until they have
sequenced up again.
ENABLE
The “ENABLE” register (Register Address 0x05) can be used to
control the enable/disable state of the boost (VBST), positive
LDO (VP) and negative charge pump (VN). This can also be used
to sequence the regulators. Refer to “Enable Timing Control
Options for VP and VN Regulators” on page 26 for details
regarding the control of output regulators using the enable and
I2C control. Using this register the VP and VN pull-down resistor
can be enabled or disabled, soft-start time of VP and VN can be
adjusted and the timing of VP sequencing can be adjusted.
Bit of ENABLE register controls the delay between the ENP
signal going low and the VP regulator power-off. If Bit is set to
0, the VP regulator is disabled 2ms after ENP going low. If Bit
is set to 1, the VP regulator is disabled as soon as ENP goes low.
Bit of ENABLE register controls shutdown behavior of VBST,
VP and VN regulators after OTP or UV event. If Bit is set to 1,
then VBST, VP and VN regulators are shut off after OTP or UV
event. To turn on the regulators, IC should be out of fault
condition and ENP and ENN signals are recycled. Regulators can
also be turned on by recycling the enable bit in the I2C register. If
Bit is set to 0, then regulators will turn back on as soon as
fault condition is removed.
respective soft-start sequence.
Output Voltage Calculation for VBST, VP and VN
The expected output voltage for each regulator can be
determined using Equations 1 through 3. Note, N is the 5-bit
register settings from 0x06, 0x08 and 0x09 in decimal.
The expected VBST voltage can be determined using Equation 1.
VBST V = VBST Default V + N 50mV
(EQ. 1)
Once the maximum VBST voltage is reached, the algorithm will
wrap around to give VBST voltage from 4.65V to 5.1V.
The expected VP voltage can be determined using Equation 2.
ꞏ
VP V = VP Default V + N 50mV
(EQ. 2)
Once the maximum VP voltage is reached, the algorithm will
wrap around to give VP voltage from 4.50V to 4.95V.
The expected VN voltage can be determined using Equation 3.
ꞏ
VN V = VN Default V – N 50mV
(EQ. 3)
Once the minimum VN voltage is reached, the algorithm will
wrap around to give VN voltage from -4.50V to -4.95V.
Example Calculations:
If N = 10 (decimal) VBST(Default) = 5.15V, VP/VN(Default) = ±5V:
VBST V = 5.15V + 10 50mV = 5.65V
Bit controls the VN and VP discharge resistor. If Bit is
programmed to “0”, then it will enable the discharge resistor
where as “1” will disable the discharge resistor.
VP V = 5V + 10 50mV = 5.5V
Bit controls the soft-start time of VN and VP regulators. If
Bit is set to “0”, then soft-start time of VN is 1.8ms and for VP
is 1.2ms whereas when set to “1”, soft-start time of both VP and
VN regulator is 0.7ms.
The default output voltage of VBST, VP, and VN regulators can be
determined by factory configurable settings. The output voltage
can be changed using I2C control when VIN > POR (Power-On
Reset) voltage. When powered up, Registers 0x06, 0x08, and
0x09 read value 0x00 and VBST, VN, VP voltage levels are at
respective default voltage. Using I2C control, the voltage can be
changed by changing the value of Registers 0x06, 0x08, and
0x09. As VIN < POR (Power-On Reset) voltage, Registers 0x06,
0x08, and 0x09 read 0x00.
VBST/VN/VN VOLTAGE
The output voltages of VBST, VP and VN regulators can be
changed using the registers “VBST Voltage”, “VP Voltage” and
“VN Voltage,” respectively. VBST voltage is at Register Address
0x06, VN voltage is at Register Address 0x08 and VP voltage is at
Register Address 0x09. The output voltages of all regulators can
be changed from their default values using I2C.
• The VBST regulator can be programmed from +4.65V to +7.3V
• The VP regulator can be programmed from +4.5V to +7V
• The VN regulator can be programmed from -7V to -4.5V
• All are adjustable with 50mV step size.
VN V = -5V – 10 50mV = -5.5V
VBST CONTROL
In addition to output voltage adjustments, key operation
parameters can be changed using I2C to optimize the
ISL98608IIH performance.
The “VBST CNTRL and VBST/VN Frequency” register (Register
Address 0x0D) can be used to control boost PFM mode, boost
FET slew rate and switching frequency of the boost and charge
pump.
Once the maximum VBST voltage (7.3V) is reached the algorithm
will wrap around to give VBST voltage from 4.65V to 5.1V.
Similarly, when maximum VP and VN voltage are reached (±7V),
the algorithm will wrap around to give VP/VN voltage from ±4.5V
to ±4.95V.
To determine the expected output voltage for a specific register
value, see the following section “Output Voltage Calculation for
VBST, VP and VN”.
NOTE: Output voltage registers should not be changed during their
FN8724 Rev.2.01
Dec 7, 2021
Page 20 of 33
REGISTER
ADDRESS
(HEX)
REGISTER
NAME
R/W
FUNCTION
BIT
BIT
BIT
Not used
Start VP and
VN together
0=
Sequenced
1 = Start
together
BIT
VP UVP
0 = Output
Voltage OK
1 = UVP
Detect if VP
100µs
BIT
BIT
BIT
VN UVP
0 = Output
Voltage OK
1 = UVP
Detect if VN
100µs
VBST UVP
0 = Output
Voltage OK
1 = UVP
Detect if
VBST 100µs
OTP
0 = Temp Ok
1 = OTP
detected,
Temp = +150°C
for >10µs
0x00
VP Enable:
0 = Disable
1 = Enable
VN Enable:
0 = Disable
1 = Enable
VBST Enable:
0 = Disable
1 = Enable
0x27
0x04
FAULT/
STATUS
0x05
ENABLE
R/W IC Enable/
Sequencing
0x06
VBST
VOLTAGE
R/W VBST Voltage Not Used
Adjustment
VBST Voltage
VBST = VBST(Default)V + N x 50mV
Once the maximum voltage is reached the algorithm will wrap around to give 4.65V to 5.1V options
0x00
VN VOLTAGE
R/W VN Voltage
Adjustment
Not Used
VN Voltage
VN = VN(Default)V - N x 50mV
Once the min voltage is reached the algorithm will wrap around to give -4.5V to -4.95V options
0x00
R/W VP Voltage
Adjustment
Not Used
VP Voltage
VP = VP(Default)V + N x 50mV
Once the maximum voltage is reached the algorithm will wrap around to give 4.5V to 4.95V options
0x00
0x08
0x09
0x0D
VP VOLTAGE
VBST control
and VBST/VN
FREQUENCY
R/W[7] Fault Status Reboot
R[6:0] Read-back
1 = Reset all
digital (reverts to
0 once reboot
completes)
0 = Normal
operation
BIT
DEFAULT
VALUE
(HEX)
VP/VN soft-start
times
0 = VP = 1.2ms
VN = 1.8ms
1=
VP = VN = 0.7ms
R/W VBST control Reserved
and VBST/VN
frequency
VP/VN
Discharge
Resistor
0 = Enabled
1 = Disabled
Reserved
Enable
shutdown of
VBST/VP/VN
at OTP or if
any is UV after
start-up.
0 = Disabled
1 = Enabled
Delay VP off Reserved
0 = VP off
2ms after
ENP
1 = VP off
with ENP
Page 21 of 33
Power FET slew rate control PFM mode
0 = Enabled
00 = Slowest
1 = Disabled
01 = Slow
10 = Fast
11 = Fastest
VBST and VN switching frequency
000 = 1.00MHz
001 = 1.07MHz
010 = 1.23MHz
011 = 1.33MHz
100 = 1.45MHz
101 = 1.60MHz
110 = 1.78MHz
111 = 2.00MHz
IC RESET
Cycle VIN or
Bit 0 - cycle
ENN and ENP
Bit 1 - cycle
ENN and ENP
Bit 2 - cycle
ENN
Bit 3 - Cycle
ENP
Cycle VIN or
clear the
register
0x04 bit
Cycle VIN or
clear the
register
0x04 bit
Cycle VIN or
clear the
register
0x04 bit
Cycle VIN or
clear the
register
0x04 bit
0xB4
Cycle VIN or
clear the
register
0x04 bit
ISL98608IIH
FN8724 Rev.2.01
Dec 7, 2021
Register Map
ISL98608IIH
Display Power Supply Function
Description
Regulator Output Enable/Disable
The boost converter, VBST, will be enabled whenever either ENP
or ENN is HIGH and the VBST enable bit in the ENABLE
register is set to ‘1’. To disable the boost (and effectively VP and
VN), ENN and ENP must be LOW, or its enable bit set to ‘0’.
The negative charge pump, VN, is enabled whenever ENN is HIGH
and the VN enable bit in the ENABLE register is set to ‘1’. To
disable, ENN must be LOW, or its enable bit set to ‘0’.
The LDO, VP, is enabled whenever ENP is HIGH and the VP enable
Bit in the ENABLE register is set to ‘1’. To disable ENP must
be LOW, or its enable bit set to ‘0’.
All the ENABLE register bits are set to ‘1’ by default.
Note, ENP and ENN are logic level inputs with HIGH/LOW
thresholds defined by the VIH/VIL specifications, respectively.
These inputs also have 1MΩ (typical) internal pull-down
resistance to ground. If the pins are left at high-impedance, they
will default to a LOW logic state. Refer to the “LOGIC/DIGITAL” on
page 7 of the “Electrical Specifications” table for more
information.
VP and VN Headroom Voltage and Output
Current
The VP and VN headroom voltage is defined as the difference
between the VBST target voltage and maximum of VP and |VN|
target voltages.
The headroom voltage must be set high enough so that both the
VP LDO and VN negative Charge Pump (CP) can maintain
regulation. The VBST voltage must be greater than the absolute
value of the VN regulation voltage (i.e., the headroom voltage has
to be >0V). Primarily, the minimum headroom voltage is a
function of the maximum application load current that the IC will
need to support. Fast output current peaks of only a few
microseconds should not be considered - those instantaneous
current peaks will be supported by the output capacitors and not
by the regulator. Equation 4 shows the minimum headroom
required depending upon the current.
Headroom V Imax A X2.7
(EQ. 4)
Note the headroom voltage should not be set overly high, since
increasing headroom generally yields lower efficiency
performance due to increased conduction losses.
For very low duty cycle where the output voltage of the VBST is
very close to the input voltage, VBST starts to track the input
voltage with a fixed headroom of ~600mV. This feature avoids
the minimum duty cycle limitation from producing increased
ripple on VBST (which feeds through to VP/VN) and ensures
proper regulation of the VBST, VP and VN regulators.
Negative Charge Pump Operation (VN)
The ISL98608IIH uses a negative charge pump with internal
switches to create the VN voltage rail. The charge pump input
voltage VBSTCP comes from the boost regulator output, VBST.
Regulation is achieved through a classic voltage mode
architecture where an internally compensated integrator output
is compared with the voltage ramp to set a duty cycle. The duty
cycle controls the amount of time the output capacitor is charged
during each switching cycle. The maximum duty cycle is 50%.
The charge pump output capacitor (placed on the VN pin) is
pumped through internal current source to minimize system
noise.
VN and VBST PFM
The ISL98608IIH features light-load Pulse Frequency Modulation
(PFM) mode for both the boost regulator and the charge pump, to
maximize efficiency at light loads.
The device always uses PWM mode at heavy loading, but will
automatically switch to PFM mode at light loads to optimize
efficiency. PFM capability is enabled using the respective PFM
mode enable/disable register bits.
VBST PFM
In PFM mode, the boost can be configured to either use a fixed
peak current or to automatically select the optimal peak current
setting. The automatic, or “Auto” mode, is designed to
dynamically adjust the peak current to maintain boost output
voltage ripple at relatively fixed levels across input voltage, while
improving efficiency at low input voltages. This patent pending
architecture adjusts the peak current to keep the sum of inductor
ramp-up and ramp-down times to a constant value of
approximately 1.3*TPWM. This scheme also gives more
consistent ripple part-to-part and keeps PWM/PFM hysteresis
defined in a smaller and more optimal band across operating
voltages. It is recommended to operate the part in this mode.
The VBST PFM mode features an ultrasonic Audio Band
Suppression (ABS) mode, which prevents the switching
frequency from falling below 30kHz to avoid audible noise. When
the time interval between two consecutive switching cycles in
PFM mode is more than 33ms (i.e., 30kHz frequency) the
regulator reduces the peak inductor current, to maintain the
frequency at 30kHz. If this is not sufficient, the regulator will add
low current reverse current cycles.
VN PFM
The charge pump PFM mode works by increasing the minimum
pump on-time, and thereby the charge delivered per cycle, when
the load is low. This allows increased ripple to be traded off
against switching losses.
For most applications, the ISL98608IIH default 400mV
headroom voltage setting provides optimal performance for DC
output current up to 200mA (maximum).
FN8724 Rev.2.01
Dec 7, 2021
Page 22 of 33
ISL98608IIH
VP/VN Output Hi-Z Mode
The ISL98608IIH VP and VN regulator can be configured in a Hi-Z
mode to prevent any leakage current flowing between VP and VN.
Using I2C register 0x05 can be used to disable the
pull-down resistors on VP and VN giving a “Hi-Z” state of output.
Power-On/Off Sequence
The boost regulator used to generate VP/VN, VBST, is activated
when the VIN input voltage is higher than the UVLO threshold,
and either ENP or ENN is high, along with their respective I2C
enable bits. To enable the VBST, Reg 0x05 should be 1
(by default this bit is set to 1). The VP output is activated if ENP is
high, VBST has completed its soft-start and Reg 0x05 is 1
(by default this bit is set to 1). The VN charge pump is activated
2ms after VBST has completed soft-start and the ENN has been
pulled high, whichever comes later. To activate the VN regulator,
Reg 0x05 should also be 1 (by default this bit is set to 1).
Figure 48 shows the power-on sequence for the case when the
ENP and ENN all are tied together and VP/VN rail sequencing is
enabled in register 0x04 by writing “0” and VP soft-start
time is 1.2ms where as VN soft-start time is 1.8ms programmed
from register 0x05 by writing “1”. The VBST soft-starts if the
VIN voltage is higher than the UVLO threshold and either ENN or
ENP is high. When the VBST soft-start is completed, the VP
regulator soft-starts in 1.2ms. The VN power-on occurs 2ms after
VBST soft-start completes. The VN soft-start time takes 1.8ms.
The 2ms power-on delay between VP and VN can be disabled
from register 0x04 by writing “1”.
Figure 49 shows the power-on sequence for the case when the
ENP and ENN all are tied together and VP/VN rail sequencing is
enabled in register 0x04 by writing “0” and VP/VN soft-start
time is programmed to 0.7ms from register 0x05 by writing
“1”. The VBST soft-starts if the VIN voltage is higher than the
UVLO threshold and either ENN or ENP is high. When the VBST
soft-start is completed, the VP regulator soft-starts in 0.7ms. The
VN power-on occurs 2ms after VBST soft-start completes. The VN
soft-start time takes 0.7ms. The 2ms power-on delay between VP
and VN can be disabled from register 0x04 by writing “1”.
Figure 50 shows the power-on sequence for the case when the
ENP and ENN all are tied together and VP/VN rail sequencing is
disabled in register 0x04 by writing “1” and VP/VN soft-start
time is programmed to 1.2ms from register 0x05 by writing
“0”. The VBST soft-starts if the VIN voltage is higher than the
UVLO threshold and either ENN or ENP is high. When the VBST
soft-start is completed, the VP and VN regulator soft-starts in
1.2ms.
FN8724 Rev.2.01
Dec 7, 2021
Figure 51 shows the power-on sequence for the case when the
ENP and ENN all are tied together and VP/VN rail sequencing is
disabled in register 0x04 by writing “1” and VP/VN soft-start
time is programmed to 0.7ms from register 0x05 by writing
“1”. The VBST soft-starts if the VIN voltage is higher than the
UVLO threshold and either ENN or ENP is high. When the VBST
soft-start is completed, the VP and VN regulator soft-starts in
0.7ms.
The VP/VN/VBST soft-start times quoted above (VBST = 0.47ms,
VP = 1.2ms and VN = 1.2ms or 1.8ms) are valid for the default
voltage levels (VSBT = 5.15V, VP = 5V and VN = -5V). These will
change with different voltages, as they are set to give a fixed
dv/dt.
Figure 52 shows the power-on sequence for the case when the
ENP and ENN are controlled by two GPIOs and VP/VN rail
sequencing is enabled from register 0x04 by writing "0".
Also, VP soft-start time is programmed to 1.2ms and VN
soft-start time is programmed to 1.8ms from register 0x05
by writing "0".
ENP or ENN going low will shut down VP or VN, respectively. If
both ENP and ENN are pulled low, then VP, VN and VBST are all
turned off. The VN regulator shuts off when ENN is pulled low. VP
and VBST power-off occurs 2ms after the ENP signal goes low
(Register 0x05 = 0), (see Figure 53). If Register 0x05 = 1,
the VP and VN regulators will power off immediately when ENN
and ENP are pulled low (see Figure 54).
If VIN falls below UVLO while the IC is active, all active regulators
will be turned off at the same time (see Figure 55).
VP AND VN DISCHARGE RESISTOR
The integrated discharge resistors on the VP and VN outputs are
80Ω (typical) and 35Ω (typical), respectively. The VP discharge
resistor is enabled for 2ms (by default) following when ENN goes
low. If ENP is still high, the VP discharge resistor is disabled 2ms
after ENN goes low. The VP discharge resistor will be re-enabled
when ENP goes low. If the same output capacitor (value, size,
rating) is used for VN and VP, the VN rail will discharge faster
than VP if they are both turned off at the same time. This is ideal
for applications that require the VN rail to go down before VP at
power-off.
Page 23 of 33
ISL98608IIH
UVLO
UVLO
VIN
VIN
ENP/ENN
ENP/ENN
0.47ms
VBST
0.47ms
VBST
VBST
POWER-GOOD
VBST
POWER-GOOD
1.2ms
VP
0.7ms
VP
1.8ms
VN
2ms
0.7ms
VN
2ms
FIGURE 48. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR
ENN AND ENP, REGISTER 0x04 = 0 AND
0x05 = 0
FIGURE 49. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR
ENN AND ENP, REGISTER 0x04 = 0 AND
0x05 = 1
UVLO
UVLO
VIN
VIN
ENP/ENN
ENP/ENN
0.47ms
0.47ms
VBST
VBST
POWER-GOOD
VBST
VBST
POWER-GOOD
2ms
VP
VP
VN
VN
1.2ms
FIGURE 50. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR
ENN AND ENP, REGISTER 0x04 = 1 AND
0x05 = 0
FN8724 Rev.2.01
Dec 7, 2021
2ms
0.7ms
FIGURE 51. POWER-ON SEQUENCE – ACTIVATED BY ONE GPIO FOR
ENN AND ENP, REGISTER 0x04 = 1 AND
0x05 = 1
Page 24 of 33
ISL98608IIH
UVLO
VIN
UVLO
VIN
ENN/ENP
ENP
ENN
VBST
0.47ms
NO DISCHARGE RESISTOR ON VBST
2ms
VBST
POWER-GOOD
VBST
VBST
POWER-GOOD
PULL TO GND (80 TYP)
VP
2ms
1.8ms
VN
1.2ms
PULL TO GND (35 TYP)
VN
FIGURE 52. POWER-ON SEQUENCE – ACTIVATED BY TWO GPIOs FOR
ENN AND ENP, REGISTER 0x04 = 0 AND
0x05 = 0
VIN
UVLO
FIGURE 53. POWER-OFF SEQUENCE - ACTIVATED BY TWO GPIOs ENN
AND ENP, REGISTER 0x05 = 0
VIN
UVLO
ENP
ENN/ENP
ENN
VBST
VBST
VBST
POWER-GOOD
VBST
POWER-GOOD
VP
NO DISCHARGE RESISTOR ON VBST
NO DISCHARGE RESISTOR ON VBST
VP
PULL TO GND (80 TYP)
PULL TO GND (35 TYP)
VN
PULL TO GND (80 TYP)
PULL TO GND (35 TYP)
VN
FIGURE 54. POWER-OFF SEQUENCE - ACTIVATED BY TWO GPIOs ENN
AND ENP, REGISTER 0x05 = 1
FN8724 Rev.2.01
Dec 7, 2021
FIGURE 55. POWER-OFF SEQUENCE - ACTIVATED BY VIN FALLING
BELOW UVLO
Page 25 of 33
ISL98608IIH
Enable Timing Control Options for VP and VN
Regulators
There are several ways to control enable sequencing of the VP
and VN regulators: I2C control, and dual or single GPIO control.
I2C CONTROL
By using I2C, the sequencing of the VP and VN regulator can be
controlled by writing to register 0x02. Bit controls the VN
regulator and controls the VP regulator. Setting the bits to
‘1’ will enable the regulator and setting to ‘0’ will shut off/disable
the regulator. Delaying the writes for setting bit and
(using separate I2C transactions) will delay the turn-on/off
sequence of VP and VN accordingly. When using I2C to control
the sequencing, ENN and ENP should be pulled low before writing
to the I2C register to disable the VP and VN regulators and then
ENN and ENP can go high before the I2C is used to enable them.
VP = 2V/DIV
VN = 2V/DIV
+5V
VP
Figure 56 shows a 14ms delay between when VP and VN turn-on.
The 14ms time is an example delay to show the power-on
sequencing possibility through I2C. This delay is set between the
separate I2C writes to set the enable bits in register 0x02. If both
enable bits were set to ‘1’ in the same I2C transaction (same
byte) and ENN and ENP are high, then both VP and VN regulators
will start power-on sequencing at the same time (when the data
is latched at the STOP condition). The VN will come up 2ms after
VP if register 0x02 is low and with VP if high.
Figure 57 shows a 14ms delay between the VP and VN turn-off.
The 14ms time is an example delay to show the power-off
sequencing possibility using I2C.
Figures 58 (zoom in) and 59 (zoom out) show a typical I2C data
transfer to the ENABLE register. In this example, VP and VN
regulators are enabled by writing data 0x07 to register address
0x02. The VP regulator will be enabled first after the I2C STOP
condition, followed by the VN regulator after the internal 2ms
delay.
VP
VP = 2V/DIV
VN = 2V/DIV
+5V
0V
0V
0V
0V
VN
VN
-5V
-5V
4ms/DIV
4ms/DIV
FIGURE 57. OFF SEQUENCE, I2C CONTROL
FIGURE 56. ON SEQUENCE, I2C CONTROL
0V
0x52
0x02
0x07
SCL = 2V/DIV (DC)
SDA = 2V/DIV (DC)
VP = 1V/DIV
VN = 1V/DIV
SCL = 2V/DIV (DC)
SDA = 2V/DIV (DC)
VP = 1V/DIV
VN = 1V/DV
0V
0V
50µs/DIV
FIGURE 58. I2C SEQUENCE AND VP RESPONSE
FN8724 Rev.2.01
Dec 7, 2021
-5V
500µs/DIV
FIGURE 59. I2C SEQUENCE AND VP/VN RESPONSE
Page 26 of 33
ISL98608IIH
SEPARATE ENP AND ENN PINS (2 GPIO CONTROL)
TIE ENP AND ENN TOGETHER (1 GPIO CONTROL)
Using two separate GPIO’s, and controlling the timing between
the ENP and ENN pins, the turn-on/off events can be controlled.
The method to control turn-on/off by GPIO is valid when the
respective enable bits in the ENABLE register at Register Address
0x02 are set to ‘1’ (default). Thus, this method can be used with
no I2C communication.
There is also an option to sequence the VN and VP regulators if
there is only a single GPIO available in the system. The method to
control turn-on/off by GPIO is valid when the respective enable
bits in the ENABLE register at Register Address 0x02 are set to
‘1’ (default). Therefore, this method can be used with no I2C
communication.
Figure 60 shows a 6ms delay (example) between the ENP and
ENN rise.
If the ENP and ENN are tied together and both pulled high and
register 0x02 = “0”, then there is a default delay sequence
in the IC. VP will come up first and after 2ms VN will soft-start.
For turn off, VN will power-off first, and VP starts to shut down
2ms after VN starts to power-off.
Figure 61 shows a 13ms delay (example) between the ENP and
ENN fall.
Figure 62 shows turn-on when the ENN and ENP pins are tied
together. There is a 2ms delay between VP and VN turning on.
Figure 63 shows turn-off when the ENN and ENP are tied
together.
+5V
VP
VP = 2V/DIV (DC)
VN = 2V/DIV (DC)
ENN = 2V/DIV (DC)
ENP = 2V/DIV (DC)
+5V
ENP
VP = 2V/DIV (DC)
VN = 2V/DIV (DC)
ENN = 2V/DIV (DC)
ENP = 2V/DIV (DC)
0V
0V
VN
0V
ENN
-5V
0V
0V
0V
-5V
2ms/DIV
1ms/DIV
FIGURE 60. ON SEQUENCE, 2 GPIO CONTROL
FIGURE 61. OFF SEQUENCE, 2 GPIO CONTROL
+5V
VP
+5V
VP = 2V/DIV (DC)
VN = 2V/DIV (DC)
ENN = 2V/DIV (DC)
ENP = 2V/DIV (DC)
VP
ENP
ENP
0V
0V
VN
0V
0V
0V
ENN
VP = 2V/DIV (DC)
VN = 2V/DIV (DC)
ENN = 2V/DIV (DC)
ENP = 2V/DIV (DC)
1ms/DIV
FIGURE 62. ON SEQUENCE, 1 GPIO CONTROL
FN8724 Rev.2.01
Dec 7, 2021
VN
-5V
ENN
0V
-5V
1ms/DIV
FIGURE 63. OFF SEQUENCE, 1 GPIO CONTROL
Page 27 of 33
ISL98608IIH
Fault Protection and Monitoring
The ISL98608IIH features extensive protections to automatically
handle failure conditions and protect the IC and application from
damage.
OVERCURRENT PROTECTION (OCP)
The overcurrent protection limits the VBST nMOSFET current on a
cycle-by-cycle basis. When the nMOSFET current reaches the
current limit threshold, the nMOSFET is turned off for the
remainder of that cycle. Overcurrent protection does not disable
any of the regulators. Once the fault is removed, the IC will
continue with normal operation.
UNDERVOLTAGE LOCKOUT (UVLO)
Depending on which regulator(s) fault, bit(s) , , or
in the FAULT register will be latched to ‘1’ for VP, VN and VBST
faults, respectively. The bit(s) are reset/cleared by cycling both
ENN and ENP (set LOW, then HIGH) at the same time or by
cycling VIN power.
Undervoltage protection can be disabled by making selection
from register 0x05.
Component Selection
The design of the boost converter is simplified by an internal
compensation scheme, which allows an easy system design
without complicated calculations. Select component values
using the following recommendations.
If the input voltage (VIN) falls below the VUVLO_HYS level of ~2.3V
(typical), the VBST, VP and VN regulators will be disabled. All the
rails will restart with normal soft-start operation when the VIN
input voltage is applied again (rising VIN > VUVLO). Refer to the
“Electrical Specifications” table on page 6 for the UVLO
specifications.
Input Capacitor
Note, the I2C registers (logic) are not cleared/reset to default by
the falling VIN UVLO. The logic states are retained if VIN remains
above 2V (typical). Once VIN falls below 2V, all logic is reset. VIN
should fall below 2V (ideally to GND) before power is reapplied to
ensure a full power cycle/reset of the device.
First, determine the minimum inductor saturation current
required for the application.
OVER-TEMPERATURE PROTECTION (OTP)
The ISL98608IIH has a hysteretic over-temperature protection
threshold set at +150°C (typical). If this threshold is reached, the
VBST, VP and VN regulators are disabled immediately. As soon as
temperature falls by 20°C (typical) then all the regulators
automatically restart.
All register bits, except for Bit of the FAULT register
(Register Address 0x04), remain unaffected during an OTP fault
event. When an OTP event occurs, FAULT register bit is
latched to ‘1’. This bit is reset/cleared by cycling both ENN and
ENP (set LOW, then HIGH) at the same time, or by cycling VIN
power. Bit can also be reset after it is read twice by I2C. A
single I2C read will return the bit value (status) and a second read
will reset only the OTP bit.
Output undervoltage protection is disabled during an OTP event.
Since the output voltages decrease during an OTP event because
the regulators are disabled, this will not trigger a UVP fault.
UNDERVOLTAGE PROTECTION (UVP)
The ISL98608IIH includes output undervoltage protection.
Undervoltage protection disables the regulator whenever the
output voltage of VBST or VP falls below 60% of its set/regulated
voltage, or the output voltage of VN goes above 60% of its
set/regulated voltage, for 100µs or more. If the output voltage
exceeds the 60% condition for less than 100µs, no fault will
occur.
It is recommended that a 10µF X5R/X7R or equivalent ceramic
capacitor is placed on the VIN input supply to ground.
Inductor
The ISL98608IIH operates in Continuous Conduction Mode (CCM)
at higher load current and in Discontinuous Conduction Mode
(DCM) at lighter loads. In CCM, we can calculate the peak
inductor current using Equations 5 through 9.
Given these parameters:
• Input Voltage = VIN
• Output Voltage = VO
• Duty Cycle = D
• Switching Frequency = fSW
• tSW = 1/fSW
Then the inductor ripple can be calculated as:
I P-P = V IN D L f SW
(EQ. 5)
Where D = 1 - (VIN/VO), then rewrite Equation 5:
I P-P = V IN V O – V IN L f SW V O
(EQ. 6)
The average inductor current is equal to the average input
current, where IIAVG can be calculated from the efficiency of the
converter.
I IAVG = V O I O V IN Efficiency
(EQ. 7)
To find the peak inductor current write the expression as:
I Pk = I P-P 2 + I IAVG
(EQ. 8)
Substituting Equations 6 and 7 in Equation 8 to calculate IPk:
I PK = 0.5 V IN V O – V IN L f SW V O + V O I O V IN EFF
(EQ. 9)
FN8724 Rev.2.01
Dec 7, 2021
Page 28 of 33
ISL98608IIH
EXAMPLE FOR VBST REGULATOR
Consider the following parameters in the steady state VLED
boost regulator operating in CCM mode.
VIN = 2.5V
VO = 5.3V
IO = 0.100A
fSW = 1.45MHz
Table 4 shows the recommended capacitors for various
regulators in ISL98608IIH.
Efficiency = 80%
L = 2.2µH
Substituting previous parameters in Equation 9 gives us:
IPk = 0.472A
The VBST regulator can be configured to either use a fixed peak
current or to automatically select the optimal peak current
setting. The automatic mode is designed to dynamically adjust
the peak current to maintain boost output voltage ripple at a
relatively fixed value across input voltage, while improving
efficiency at low input voltages.
In order to avoid the inductor core saturation, the saturation
current of the inductor selected should be higher than the greater
of the peak inductor current (for CCM) and the peak current in
PFM mode and current limit of the regulators. It is recommended
to use an inductor that has saturation current rating higher than
current limit of the boost regulator.
Auto PFM mode provides maximum efficiency using 2.2µH for
the VBST regulator. L = 2.2µH is the optimal value for the VBST
regulator.
Table 3 shows the recommended inductors for the VBST boost
regulator.
TABLE 3. RECOMMENDED INDUCTORS FOR VBST REGULATOR
INDUCTOR PART
NUMBER
INDUCTANCE
(µH)
DCR
(mΩ)
ISAT
(A)
FOOTPRINT
SIZE
VLF302510MT-2R2M
(TDK)
2.2
70
1.23
3025
DFE252012C
(Toko)
2.2
90
2.00
2520
TFM201610G-2R2M
(TDK)
2.2
150
1.20
2016
Output Capacitor
The output capacitor supplies current to the load during transient
conditions and reduces the ripple voltage at the output. Output
ripple voltage consists of two components:
1. The voltage drop due to the inductor ripple current flowing
through the ESR of the output capacitor.
2. Charging and discharging of the output capacitor.
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than the
maximum output voltage.
FN8724 Rev.2.01
Dec 7, 2021
The effective capacitance at the nominal output voltage should
be ≥2.2µF for VBST and VP regulators, and ≥4.4µF for VN. It is
recommended to use a 10µF X5R 10V or equivalent ceramic
output capacitor for both VBST and VP outputs to provide a
minimum of 2.2µF effective capacitance. For the VN output, it is
recommended to use one or two 10µF X5R 10V or equivalent
ceramic output capacitors. Using two VN output capacitors
results in
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