DATASHEET
ISLA214P12
FN7982
Rev.4.0
Jul 6, 2021
High Performance 14-Bit, 125MSPS ADC
The ISLA214P12 is a high performance 14-bit 125MSPS
analog-to-digital converter offering very high dynamic range
and low power consumption. It is part of a pin-compatible
family of 12- to 16-bit A/Ds with maximum sample rates
ranging from 125 to 500MSPS. This allows a design using
the ISLA214P12 to accommodate any of the other
pin-compatible A/Ds with minimal changes.
The ISLA214P12 is very flexible and can be designed into a
wide variety of systems. A Serial Peripheral Interface (SPI) port
allows access to its extensive configurability and provides
digital control over various analog parameters such as input
gain and offset. Digital output data is presented in selectable
LVDS or CMOS formats and can be configured as full-width,
Single Data Rate (SDR) or half-width, Double Data Rate (DDR).
Operating from a 1.8V supply, performance is specified across
the full industrial temperature range (-40°C to +85°C).
Applications
•
•
•
•
•
Features
• Multi-ADC Support
- SPI programmable fine gain and offset control
- Multiple ADC synchronization
- Optimized output timing
• Clock duty cycle stabilizer
• Nap and Sleep modes
• Programmable built-in test patterns
• SDR/DDR LVDS-compatible or LVCMOS outputs
• Data output clock
Key Specifications
• SNR at 125MSPS
- 74.9dBFS fIN = 30MHz
- 70.9dBFS fIN = 363MHz
• SFDR at 125MSPS
Radar array processing
Software defined radio
Broadband communications
High performance data acquisition
Communications test equipment
- 88dBc fIN = 30MHz
- 84dBc fIN = 363MHz
• Total power consumption = 310mW
-
CLKP
TABLE 1. PIN-COMPATIBLE FAMILY
CLOCK
MANAGEMENT
14-BIT
125 MSPS
ADC
VINN
+
–
FN7982 Rev.4.0
Jul 6, 2021
RESETN
AVSS
NAPSLP
VCM
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
CLKOUTP
ISLA216P20
16
200
CLKOUTN
ISLA216P13
16
130
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
D[13:0]P
DIGITAL
ERROR
CORRECTION
SPI
CONTROL
CSB
SCLK
SDIO
SDO
SHA
OVSS
VINP
RLVDS
CLKN
MODEL
OVDD
CLKDIVRSTN
CLKDIVRSTP
AVDD
CLKDIV
-
D[13:0]N
Page 1 of 33
© 2012 Renesas Electronics
ISLA214P12
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration - LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration - CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
20
20
20
20
20
20
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
25
25
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
31
31
31
31
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FN7982 Rev.4.0
Jul 6, 2021
Page 2 of 33
ISLA214P12
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
PACKAGE DESCRIPTION
(RoHS Compliant)
PKG. DWG. #
CARRIER TYPE
TEMP. RANGE
72 Ld QFN
L72.10x10G
Tray
-40°C to +85°C
ISLA214P12IRZ
ISLA214P12 IRZ
ISLA214IR72EV1Z
Evaluation Board - supports 125/130/200/250Msps grades
KMB-001LEVALZ
LVDS Motherboard (Interfaces with ISLA214IR72EV1Z operating in LVDS Output mode)
KMB-001CEVALZ
CMOS Motherboard (Interfaces with ISLA214IR72EV1Z operating in CMOS Output mode)
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), see the ISLA214P12 device page. For more information about MSL, see TB363.
Pin Configuration - LVDS Mode
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
D0P
D0N
D1P
D1N
D2P
D2N
72 LD QFN
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3P
DNC
2
53 D3N
NAPSLP
3
52 D4P
VCM
4
51 D4N
AVSS
5
50 D5P
AVDD
6
49 D5N
AVSS
7
48 CLKOUTP
VINN
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D6P
AVSS 12
43 D6N
AVDD 13
42 D7P
AVSS 14
41 D7N
CLKDIV 15
40 D8P
DNC 16
39 D8N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
37 D9N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
AVDD
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
D13N
D13P
D12N
D12P
OVDD
D11N
D11P
D10N
D10P
RESETN 18
FN7982 Rev.4.0
Jul 6, 2021
38 D9P
Page 3 of 33
ISLA214P12
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 16, 17
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
Tri-Level Clock Divider Control
18
RESETN
Power On Reset (Active Low)
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
28
D13N
LVDS Bit 13(MSB) Output Complement
NC in DDR Mode
29
D13P
LVDS Bit 13 (MSB) Output True
NC in DDR Mode
30
D12N
LVDS Bit 12 Output Complement
DDR Logical Bits 12, 13
31
D12P
LVDS Bit 12 Output True
DDR Logical Bits 12, 13
33
D11N
LVDS Bit 11 Output Complement
NC in DDR Mode
34
D11P
LVDS Bit 11 Output True
NC in DDR Mode
35
D10N
LVDS Bit 10 Output Complement
DDR Logical Bits 10, 11
36
D10P
LVDS Bit 10 Output True
DDR Logical Bits 10, 11
37
D9N
LVDS Bit 9 Output Complement
NC in DDR Mode
38
D9P
LVDS Bit 9 Output True
NC in DDR Mode
39
D8N
LVDS Bit 8 Output Complement
DDR Logical Bits 8, 9
40
D8P
LVDS Bit 8 Output True
DDR Logical Bits 8, 9
41
D7N
LVDS Bit 7 Output Complement
NC in DDR Mode
42
D7P
LVDS Bit 7 Output True
NC in DDR Mode
43
D6N
LVDS Bit 6 Output Complement
DDR Logical Bits 6, 7
44
D6P
LVDS Bit 6 Output True
DDR Logical Bits 6, 7
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
49
D5N
LVDS Bit 5 Output Complement
NC in DDR Mode
50
D5P
LVDS Bit 5 Output True
NC in DDR Mode
51
D4N
LVDS Bit 4 Output Complement
DDR Logical Bits 4, 5
52
D4P
LVDS Bit 4 Output True
DDR Logical Bits 4, 5
53
D3N
LVDS Bit 3 Output Complement
NC in DDR Mode
54
D3P
LVDS Bit 3 Output True
NC in DDR Mode
55
D2N
LVDS Bit 2 Output Complement
DDR Logical Bits 2, 3
56
D2P
LVDS Bit 2 Output True
DDR Logical Bits 2, 3
57
D1N
LVDS Bit 1 Output Complement
NC in DDR Mode
58
D1P
LVDS Bit 1 True
NC in DDR Mode
FN7982 Rev.4.0
Jul 6, 2021
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (Connect to OVSS with 1% 10kΩ)
LVDS Clock Output Complement, True
Page 4 of 33
ISLA214P12
Pin Descriptions - 72 Ld QFN, LVDS Mode
(Continued)
PIN NUMBER
LVDS PIN NAME
59
D0N
LVDS Bit 0 (LSB) Output Complement
LVDS PIN FUNCTION
DDR Logical Bits 0, 1
DDR MODE COMMENTS
60
D0P
LVDS Bit 0 (LSB) Output True
DDR Logical Bits 0, 1
63, 64
ORN, ORP
LVDS Over Range Complement, True
DDR Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Pin Configuration - CMOS Mode
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
D0
68
67
66
65
64
63
62
61
60
59
DNC
SCLK
69
D2
SDIO
70
DNC
AVDD
71
D1
AVDD
72
DNC
AVDD
72 LD QFN
TOP VIEW
58
57
56
55
DNC
1
54 D3
DNC
2
53 DNC
NAPSLP
3
52 D4
VCM
4
51 DNC
AVSS
5
50 D5
AVDD
6
49 DNC
AVSS
7
48 CLKOUT
VINN
8
47 DNC
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D6
AVSS 12
43 DNC
AVDD 13
42 D7
AVSS 14
41 DNC
CLKDIV 15
40 D8
DNC 16
39 DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
FN7982 Rev.4.0
Jul 6, 2021
CLKDIVRSTP
CLKDIVRSTN
30
31
32
33
34
35
36
D10
CLKN
29
DNC
CLKP
28
D11
AVDD
27
DNC
AVDD
26
OVDD
25
D12
24
DNC
23
D13
22
DNC
21
37 DNC
OVDD
20
OVSS
19
AVDD
RESETN 18
38 D9
Page 5 of 33
ISLA214P12
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 16, 17, 28, 30, 33,
35, 37, 39, 41, 43, 47,
49, 51, 53, 55, 57, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
Tri-Level Clock Divider Control
18
RESETN
Power On Reset (Active Low)
22, 23
CLKP, CLKN
24, 25
CMOS PIN FUNCTION
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
Clock Input True, Complement
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29
D13
CMOS Bit 13 (MSB) Output
NC in DDR Mode
31
D12
CMOS Bit 12 Output
DDR Logical Bits 12, 13
34
D11
CMOS Bit 11 Output
NC in DDR Mode
36
D10
CMOS Bit 10 Output
DDR Logical Bits 10, 11
38
D9
CMOS Bit 9 Output
NC in DDR Mode
40
D8
CMOS Bit 8 Output
DDR Logical Bits 8, 9
42
D7
CMOS Bit 7 Output
NC in DDR Mode
44
D6
CMOS Bit 6 Output
DDR Logical Bits 6, 7
46
RLVDS
LVDS Bias Resistor (connect to OVSS with 1% 10kΩ)
48
CLKOUT
CMOS Clock Output
50
D5
CMOS Bit 5 Output
NC in DDR Mode
52
D4
CMOS Bit 4 Output
DDR Logical Bits 4, 5
54
D3
CMOS Bit 3 Output
NC in DDR Mode
56
D2
CMOS Bit 2 Output
DDR Logical Bits 2, 3
58
D1
CMOS Bit 1 Output
NC in DDR Mode
60
D0
CMOS Bit 0 (LSB) Output
DDR Logical Bits 0, 1
64
OR
CMOS Over Range
DDR Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7982 Rev.4.0
Jul 6, 2021
Page 6 of 33
ISLA214P12
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125Msps. Boldface limits apply across the operating temperature range,
-40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
1.95
2.0
2.1
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input Range
VFS
Differential
Input Resistance
RIN
Differential
600
Ω
Input Capacitance
CIN
Differential
4.5
pF
Full temperature
74
ppm/°C
Full Scale Range Temperature Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output Voltage
VCM
0.94
V
Common-Mode Input Current
(per pin)
ICM
2.6
µA/MSPS
Inputs Common-Mode Voltage
0.9
V
CLKP, CLKN Input Swing (Note 7)
1.8
V
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
152
161
mA
1.8V Digital Supply Current (Note 6)
I
OVDD
3mA LVDS (SDR)
68.5
77
mA
Power Supply Rejection Ratio
PSRR
30MHz, 30mVP-P signal on AVDD
40
dB
CMOS (DDR)
310
mW
CMOS (SDR)
313
mW
2mA LVDS (SDR)
369
mW
3mA LVDS (DDR)
360
mW
3mA LVDS (SDR)
397
Total Power Dissipation
Normal Mode
FN7982 Rev.4.0
Jul 6, 2021
PD
428
mW
Page 7 of 33
ISLA214P12
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125Msps. Boldface limits apply across the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Nap Mode
PD
Sleep Mode
PD
Nap/Sleep Mode Wakeup Time
CONDITIONS
MIN
(Note 5)
CSB at logic high
Sample clock running
TYP
MAX
(Note 5)
UNIT
48.6
53
mW
6
10
mW
630
µs
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 105MHz
±0.25
LSB
Integral Nonlinearity
INL
fIN = 105MHz
±2.5
LSB
Minimum Conversion Rate (Note 8)
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio
(Note 9)
Signal-to-Noise and Distortion
(Note 9)
Effective Number of Bits
(Note 9)
Spurious-Free Dynamic Range
(Note 9)
Spurious-Free Dynamic Range
Excluding H2, H3
FN7982 Rev.4.0
Jul 6, 2021
SNR
40
125
fIN = 30MHz
dBFS
74.3
dBFS
fIN = 190MHz
73.3
dBFS
fIN = 363MHz
70.9
dBFS
fIN = 461MHz
69.5
dBFS
fIN = 605MHz
67.8
dBFS
fIN = 30MHz
74.6
dBFS
73.6
dBFS
fIN = 190MHz
72.2
dBFS
fIN = 363MHz
70.6
dBFS
fIN = 461MHz
65.9
dBFS
fIN = 605MHz
61.1
dBFS
fIN = 30MHz
12.10
Bits
11.93
Bits
fIN = 190MHz
11.70
Bits
fIN = 363MHz
11.44
Bits
fIN = 461MHz
10.65
Bits
fIN = 605MHz
9.86
Bits
fIN = 30MHz
88
dBc
83
dBc
fIN = 190MHz
78
dBc
fIN = 363MHz
84
dBc
fIN = 461MHz
68
dBc
fIN = 605MHz
61
dBc
fIN = 30MHz
99
dBc
fIN = 105MHz
95
dBc
fIN = 190MHz
91
dBc
fIN = 363MHz
95
dBc
fIN = 461MHz
94
dBc
fIN = 605MHz
87
dBc
fIN = 105MHz
ENOB
fIN = 105MHz
SFDR
fIN = 105MHz
SFDRX23
MSPS
74.9
fIN = 105MHz
SINAD
MSPS
73.0
70.8
11.47
70
Page 8 of 33
ISLA214P12
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 125Msps. Boldface limits apply across the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Intermodulation Distortion
IMD
MIN
(Note 5)
CONDITIONS
TYP
MAX
(Note 5)
UNIT
fIN = 70MHz
-85
dBFS
fIN = 170MHz
-105
dBFS
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
7. See “Clock Input” on page 19.
8. The DLL Range setting must be changed for low-speed operation.
9. Minimum specification ensured when calibrated at +85°C.
Digital Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
0
1
10
µA
-25
-12
-8
µA
4
12
µA
-600
-415
-300
µA
40
58
75
µA
5
10
µA
INPUTS (Note 10)
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
Input Current High (CLKDIV)
IIH
16
25
34
µA
Input Current Low (CLKDIV)
IIL
-34
-25
-16
µA
Input Voltage High (SDIO, RESETN)
VIH
1.17
Input Voltage Low (SDIO, RESETN)
VIL
Input Capacitance
CDI
V
0.63
4
V
pF
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common-Mode Range
VICM
825
1575
mV
Input Differential Swing (peak-to-peak, single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-Down Resistance
RIpd
100
kΩ
CLKDIVRSTN Input Pull-Up Resistance
RIpu
100
kΩ
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 11)
Output Offset Voltage
VT
3mA mode
VOS
3mA mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
FN7982 Rev.4.0
Jul 6, 2021
OVDD - 0.3
0.1
0.3
V
Page 9 of 33
ISLA214P12
Digital Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
10. The tri-level inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[12/10/8/6/4/2/0]N
ODD
N-L
D[12/10/8/6/4/2/0]P
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1A. LVDS DDR
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
D[13:0]N
D[13:0]P
tPD
DATA
N-L
DATA
N-L+1
DATA
N
FIGURE 1B. LVDS SDR
FIGURE 1. LVDS TIMING DIAGRAMS
FN7982 Rev.4.0
Jul 6, 2021
Page 10 of 33
ISLA214P12
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
ODD
N-L
D[12/10/8/6/4/2/0]
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 2A. CMOS DDR
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
D[13:0]
DATA
N-L
DATA
N-L+1
DATA
N
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
FN7982 Rev.4.0
Jul 6, 2021
Page 11 of 33
ISLA214P12
Switching Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
2.4
3.5
ns
Rising/falling edge
-0.1
0.16
0.5
ns
Rising/falling edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
ns
0.35
ns
30
cycles
L
10
cycles
tOVR
1
cycles
Latency (Pipeline Delay)
Overvoltage Recovery
1.65
DLL recovery time after
Synchronous Reset
(sample clock not interrupted)
SPI INTERFACE (Notes 13, 14)
SCLK Period
t
CLK
Write operation
16
cycles
tCLK
Read operation
16
cycles
CSB to SCLKSetup Time
tS
Read or Write
28
cycles
CSB after SCLK Hold Time
tH
Write
5
cycles
CSB after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK Setup Time
tDS
Write
6
cycles
Data Valid after SCLK Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified across the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
FN7982 Rev.4.0
Jul 6, 2021
Page 12 of 33
ISLA214P12
Typical Performance Curves
All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 125MSPS.
-55
SFDR AT 125MSPS
85
H2 AND H3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
80
75
70
SNR AT 125MSPS
65
60
55
-60
-65
H2 AT 125MSPS
-70
-75
-80
-85
-90
H3 AT 125MSPS
-95
-100
0
100
200
300
400
500
0
600
100
200
INPUT FREQUENCY (MHz)
90
H2 AND H3 MAGNITUDE
SNR AND SFDR
SNR (dBFS)
SFDR (dBc)
50
40
30
SNR (dBc)
20
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
-10
-10
0
-65
HD2 (dBc)
-75
-85
HD3 (dBFS)
-95
-105
HD2 (dBFS)
-115
-60
0
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs AIN
FIGURE 6. HD2 AND HD3 vs AIN
90
-75
H2 AND H3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
600
HD3(dBc)
-55
SFDR (dBFS)
80
10
-60
500
-45
100
60
400
FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 3. SNR AND SFDR vs fIN
70
300
INPUT FREQUENCY (MHz)
85
SFDR
80
75
SNR
70
40
60
80
100
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
FN7982 Rev.4.0
Jul 6, 2021
120
-80
H3
-85
-90
-95
H2
-100
-105
40
50
60
70
80
90
100
SAMPLE RATE (MSPS)
110
120
FIGURE 8. HD2 AND HD3 vs fSAMPLE
Page 13 of 33
ISLA214P12
Typical Performance Curves
All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 125MSPS. (Continued)
1.0
400
0.8
0.6
350
0.4
325
DNL (LSBs)
TOTAL POWER (mW)
375
LVDS
300
275
0.2
0
-0.2
-0.4
250
-0.6
CMOS
225
200
40
60
-0.8
80
100
-1.0
120
0
2000
4000
6000
FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE (SDR) AND
CMOS MODE (DDR)
FIGURE 10. DIFFERENTIAL NONLINEARITY
4
95
SNR (dBFS) AND SFDR (dBc)
3
INL (LSBs)
2
1
0
-1
-2
-3
-4
0
2000
4000
6000
SFDR AIN = -2dBFS
90
85
80
SFDR AIN = -1dBFS
75
70
SNR AIN = -1dBFS
65
60
0.75
8000 10000 12000 14000 16000
0.85
FIGURE 11. INTEGRAL NONLINEARITY
80000
75501
71821
AMPLITUDE (dBFS)
60000
50000
40000
24535
22204
20000
0
1.15
0
STDEV = 0.95 CODES
AIN = -1.0 dBFS
SNR = 74.7 dBFS
SFDR = 84.5 dBc
SINAD = 74.1 dBFS
-20
30000
1.05
FIGURE 12. SNR AND SFDR vs VCM
70000
10000
0.95
INPUT COMMON-MODE (V)
CODES
NUMBER OF HITS
8000 10000 12000 14000 16000
CODES
SAMPLE RATE (MSPS)
-40
-60
-80
-100
0
106
2939
2775 118 1
0
8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179
CODE
FIGURE 13. NOISE HISTOGRAM
FN7982 Rev.4.0
Jul 6, 2021
-120
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 14. SINGLE-TONE SPECTRUM AT 105MHz
Page 14 of 33
ISLA214P12
Typical Performance Curves
All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 125MSPS. (Continued)
0
0
AIN = -1.0 dBFS
SNR = 73.5 dBFS
SFDR = 82.2 dBc
SINAD = 72.9 dBFS
-40
-60
-80
-100
-120
AIN = -1.0 dBFS
SNR = 70.3 dBFS
SFDR = 81.0 dBc
SINAD = 69.9 dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
-40
-60
-80
-100
0
10
20
30
40
50
-120
0
60
10
FREQUENCY (MHz)
50
FIGURE 15. SINGLE-TONE SPECTRUM AT 190MHz
FIGURE 16. SINGLE-TONE SPECTRUM AT 363MHz
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-40
-60
IMD3 = -85 dBFS
-80
-100
-120
60
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
20
30
40
FREQUENCY (MHz)
-40
-60
IMD3 = -105 dBFS
-80
-100
0
10
20
30
40
FREQUENCY (MHz)
50
60
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
FN7982 Rev.4.0
Jul 6, 2021
-120
0
10
20
30
40
FREQUENCY (MHz)
50
60
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
Page 15 of 33
ISLA214P12
Theory of Operation
A user-initiated reset can subsequently be invoked in the event
that the previous conditions cannot be met at power-up.
Functional Description
The ISLA214P12 is based on a 14-bit, 125MSPS A/D converter
core that uses a pipelined successive approximation architecture
(see Figure 19). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal Power-On Reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be followed to for the power-on
calibration to execute successfully.
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20 on page 17. Calibration status
can be determined by reading the cal_status bit (LSB) at 0xB6.
This bit is ‘0’ during calibration and goes to a logic ‘1’ when
calibration is complete. The data outputs produce 0xCCCC during
calibration; this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 125MSPS the nominal calibration time is 560ms, while the
maximum calibration time is 1000ms.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional
• SPI communications must not be attempted
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
2.5-BIT
FLASH
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
FN7982 Rev.4.0
Jul 6, 2021
Page 16 of 33
ISLA214P12
The performance of the ISLA214P12 changes with variations in
temperature, supply voltage, or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance is achieved by
recalibrating the A/D under the environmental conditions at
which it operates.
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
A supply voltage variation of
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