DATASHEET
ISLA224P
FN7570
Rev.2.0
Jul 6, 2021
Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC
The ISLA224P is a family of dual-channel 14-Bit analog-to-digital
converters. Designed with Renesas’ proprietary FemtoCharge™
technology on a standard CMOS process, the family supports
sampling rates of up to 250MSPS. The ISLA224P is part of a
pin-compatible portfolio of 12-bit and 14-bit dual-channel A/Ds
with maximum sample rates ranging from 130MSPS to
250MSPS.
Features
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters such
as gain and offset.
• Programmable built-in test patterns
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA224P is available in a 72-contact QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs clock jitter
• 700MHz bandwidth
• Multi-ADC support
- SPI programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs sleep wake-up time
• Data output clock
Key Specifications
• DDR LVDS-compatible or LVCMOS outputs
• SNR @ 250/200/130MSPS
72.7/73.9/74.7dBFS fIN = 30MHz
70.2/70.7/70.2dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
84/86/86dBc fIN = 30MHz
73/75/79dBc fIN = 363MHz
• Total Power Consumption = 837mW @ 250MSPS
• Selectable clock divider
Applications
• Radar array processing
• Software defined radios
• Broadband communications
• High-performance data acquisition
• Communications test equipment
CLKP
OVDD
CLKDIVRSTN
CLKDIVRSTP
AVDD
CLKDIV
TABLE 1. Pin-Compatible Family
CLKOUTP
CLOCK
MANAGEMENT
CLKN
14-BIT
250 MSPS
ADC
VREF
VCM
VINAN
14-BIT
250 MSPS
ADC
VREF
+
1.25V
–
RESETN
AVSS
NAPSLP
SHA
VINAP
FN7570 Rev.2.0
Jul 6, 2021
D[13:0]P
D[13:0]N
DIGITAL
ERROR
CORRECTION
ORP
ORN
RESOLUTION
SPEED
(MSPS)
ISLA224P25
14
250
ISLA224P20
14
200
ISLA224P13
14
130
ISLA222P25
12
250
ISLA222P20
12
200
ISLA222P13
12
130
OUTFMT
OUTMODE
SPI
CONTROL
OVSS
SHA
CSB
SCLK
SDIO
SDO
VINBP
VINBN
CLKOUTN
MODEL
Page 1 of 34
© 2011 Renesas Electronics
ISLA224P
Table of Contents
Pin Configuration- LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration- CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
20
20
20
20
20
21
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
25
25
26
28
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
32
32
32
32
32
32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7570 Rev.2.0
Jul 6, 2021
Page 2 of 34
ISLA224P
Pin Configuration- LVDS Mode
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
D0P
D0N
D1P
D1N
D2P
D2N
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3P
DNC
2
53 D3N
NAPSLP
3
52 D4P
VCM
4
51 D4N
AVSS
5
50 D5P
VINBP
6
49 D5N
VINBN
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
AVDD
9
46 RLVDS
AVDD
10
45 OVSS
AVSS
11
44 D6P
VINAN
12
43 D6N
VINAP
13
42 D7P
AVSS
14
41 D7N
CLKDIV
15
40 D8P
IPTAT
16
38 D9P
Connect Thermal Pad to AVSS
18
27
28
29
30
31
32
33
D13N
D13P
D12N
D12P
OVDD
D11N
34
35
36
D10P
26
D10N
25
D11P
24
OVDD
CLKP
23
OVSS
22
CLKDIVRSTN
21
CLKDIVRSTP
20
CLKN
19
AVDD
37 D9N
AVDD
RESETN
17
AVDD
DNC
39 D8N
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
1, 2, 17
DNC
Do Not Connect
9, 10, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 8, 11, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
6, 7
VINBP, VINBN
Channel B Analog Input Positive, Negative
12, 13
VINAN, VINAP
Channel A Analog Input Negative, Positive
FN7570 Rev.2.0
Jul 6, 2021
LVDS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Page 3 of 34
ISLA224P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
(Continued)
LVDS PIN FUNCTION
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
24, 25
CLKDIVRSTP, CLKDIVRSTN
28, 29
D13N, D13P
LVDS Bit 13 (MSB) Output Complement, True
30, 31
D12N, D12P
LVDS Bit 12 Output Complement, True
33, 34
D11N, D11P
LVDS Bit 11 Output Complement, True
35, 36
D10N, D10P
LVDS Bit 10 Output Complement, True
37, 38
D9N, D9P
LVDS Bit 9 Output Complement, True
39, 40
D8N, D8P
LVDS Bit 8 Output Complement, True
41, 42
D7N, D7P
LVDS Bit 7 Output Complement, True
43, 44
D6N, D6P
LVDS Bit 6 Output Complement, True
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
LVDS Clock Output Complement, True
49, 50
D5N, D5P
LVDS Bit 5 Output Complement, True
51, 52
D4N, D4P
LVDS Bit 4 Output Complement, True
53, 54
D3N, D3P
LVDS Bit 3 Output Complement, True
55, 56
D2N, D2P
LVDS Bit 2 Output Complement, True
57, 58
D1N, D1P
LVDS Bit 1 Output Complement, True
59, 60
D0N, D0P
LVDS Bit 0 (LSB) Output Complement, True
63, 64
ORN, ORP
LVDS Over Range Complement, True
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7570 Rev.2.0
Jul 6, 2021
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (connect to OVSS with 1%10k)
Page 4 of 34
ISLA224P
Pin Configuration- CMOS Mode
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
D0
DNC
D1
DNC
D2
DNC
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3
DNC
2
53 DNC
NAPSLP
3
52 D4
VCM
4
51 DNC
AVSS
5
50 D5
VINBP
6
49 DNC
VINBN
7
48 CLKOUT
AVSS
8
47 DNC
AVDD
9
46 RLVDS
AVDD
10
45 OVSS
AVSS
11
44 D6
VINAN
12
43 DNC
VINAP
13
42 D7
AVSS
14
41 DNC
CLKDIV
15
40 D8
IPTAT
16
38 D9
Connect Thermal Pad to AVSS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
DNC
D13
DNC
D12
OVDD
DNC
D11
DNC
D10
37 DNC
AVDD
RESETN
17
AVDD
DNC
39 DNC
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions.
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 17, 28, 30, 33, 35, 37, 39,
41, 43, 47, 49, 51, 53, 55, 57,
59, 63
DNC
Do Not Connect
9, 10, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 8, 11, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
FN7570 Rev.2.0
Jul 6, 2021
CMOS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Page 5 of 34
ISLA224P
Pin Descriptions - 72 Ld QFN, CMOS Mode
(Continued)
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
6, 7
VINBP, VINBN
Channel B Analog Input Positive, Negative
12, 13
VINAN, VINAP
Channel A Analog Input Negative, Positive
15
CLKDIV
16
IPTAT
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
29
D13
CMOS Bit 13 (MSB) Output
31
D12
CMOS Bit 12 Output
34
D11
CMOS Bit 11 Output
36
D10
CMOS Bit 10 Output
38
D9
CMOS Bit 9 Output
40
D8
CMOS Bit 8 Output
42
D7
CMOS Bit 7 Output
44
D6
CMOS Bit 6 Output
46
RLVDS
LVDS Bias Resistor (connect to OVSS with 1%10k)
48
CLKOUT
CMOS Clock Output
50
D5
CMOS Bit 5 Output
52
D4
CMOS Bit 4 Output
54
D3
CMOS Bit 3 Output
56
D2
CMOS Bit 2 Output
58
D1
CMOS Bit 1 Output
60
D0
CMOS Bit 0 (LSB) Output
64
OR
CMOS Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7570 Rev.2.0
Jul 6, 2021
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
Page 6 of 34
ISLA224P
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
ISLA224P13IRZ
ISLA224P13 IRZ
ISLA224P20IRZ
ISLA224P20 IRZ
ISLA224P25IRZ
ISLA224P25 IRZ
ISLA224IR72EV1Z
Evaluation Board
PACKAGE
DESCRIPTION
(RoHS Compliant)
PKG. DWG. #
CARRIER TYPE
TEMP. RANGE
72 Ld QFN
L72.10x10G
Tray
-40°C to +85°C
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), see respective device information page for ISLA224P13, ISLA224P20, ISLA224P25. For more information on
MSL, see TB363.
FN7570 Rev.2.0
Jul 6, 2021
Page 7 of 34
ISLA224P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C.
ISLA224P25
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
1.95
2.0
ISLA224P20
MAX
MIN
(Note 5) (Note 5)
TYP
ISLA224P13
MAX
MIN
(Note 5) (Note 5)
TYP
MAX
(Note 5)
UNITS
2.0
2.2
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
VFS
Differential
2.2
1.95
2.0
2.2
1.95
Input Resistance
RIN
Differential
600
600
600
Input Capacitance
CIN
Differential
4.5
4.5
4.5
pF
Full Temp
108
82
75
ppm/°C
Full Scale Range Temp.
Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output
Voltage
VCM
0.94
0.94
0.94
V
Common-Mode Input
Current (per pin)
ICM
2.6
2.6
2.6
µA/MSPS
Inputs Common Mode
Voltage
0.9
0.9
0.9
V
CLKP,CLKN Input Swing
1.8
1.8
1.8
V
-7.0
-1.7
7.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
375
389
344
376
293
312
mA
1.8V Digital Supply
Current (Note 6)
I
OVDD
3mA LVDS
90
100
85
93
75
83
mA
Power Supply Rejection
Ratio
PSRR
30MHz, 50mVP-P signal
on AVDD
-65
-65
-65
dB
Total Power Dissipation
FN7570 Rev.2.0
Jul 6, 2021
Page 8 of 34
ISLA224P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA224P25
PARAMETER
Normal Mode
SYMBOL
PD
Nap Mode
PD
Sleep Mode
PD
Nap/Sleep Mode
Wakeup Time
CONDITIONS
MIN
(Note 5)
TYP
2mA LVDS
810
3mA LVDS
837
CMOS
780
CSB at logic high
Sample Clock Running
ISLA224P20
MAX
MIN
(Note 5) (Note 5)
TYP
ISLA224P13
MAX
MIN
(Note 5) (Note 5)
750
880
772
TYP
MAX
(Note 5)
640
844
662
705
UNITS
mW
711
590
mW
mW
87
96
83
93
77
85
mW
6
11
6
11
6
10
mW
200
400
630
µs
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 105MHz
No Missing Codes
Integral Nonlinearity
INL
fIN = 105MHz
Minimum Conversion
Rate (Note 7)
fS MIN
Maximum Conversion
Rate
fS MAX
Signal-to-Noise Ratio
(Note 8)
SNR
Signal-to-Noise and
Distortion
(Note 8)
Effective Number of Bits
(Note 8)
FN7570 Rev.2.0
Jul 6, 2021
2.0
-0.99
±4.0
250
fIN = 30MHz
±0.4
±0.4
130
73.6
72.7
LSB
LSB
40
73.9
72.0
0.99
±3.0
40
200
72.5
-0.99
±3.0
72.7
70.6
0.99
MSPS
MSPS
74.7
dBFS
74.3
dBFS
fIN = 190MHz
71.8
72.8
72.9
dBFS
fIN = 363MHz
70.2
70.7
70.2
dBFS
fIN = 461MHz
69.3
69.3
68.8
dBFS
fIN = 605MHz
67.9
68.0
68.0
dBFS
fIN = 30MHz
72.1
73.5
74.2
dBFS
72.8
dBFS
fIN = 105MHz
ENOB
±0.5
40
fIN = 105MHz
SINAD
-0.99
68.8
71.0
69.8
72.7
70.0
fIN = 190MHz
70.0
71.5
71.4
dBFS
fIN = 363MHz
68.0
69.1
69.5
dBFS
fIN = 461MHz
66.0
66.3
65.7
dBFS
fIN = 605MHz
63.8
62.1
60.3
dBFS
fIN = 30MHz
11.68
11.92
12.03
Bits
fIN = 105MHz
11.14 11.50
11.30 11.78
11.34 11.80
Bits
fIN = 190MHz
11.34
11.58
11.57
Bits
fIN = 363MHz
11.00
11.19
11.25
Bits
fIN = 461MHz
10.67
10.72
10.62
Bits
fIN = 605MHz
10.31
10.02
9.72
Bits
Page 9 of 34
ISLA224P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA224P25
PARAMETER
SYMBOL
Spurious-Free Dynamic
Range
(Note 8)
SFDR
CONDITIONS
MIN
(Note 5)
fIN = 30MHz
fIN = 105MHz
TYP
ISLA224P20
MAX
MIN
(Note 5) (Note 5)
84
71
79
TYP
ISLA224P13
MAX
MIN
(Note 5) (Note 5)
86
72
82
71
TYP
MAX
(Note 5)
UNITS
86
dBc
79
dBc
fIN = 190MHz
75
77
76
dBc
fIN = 363MHz
73
75
79
dBc
fIN = 461MHz
69
71
70
dBc
fIN = 605MHz
67
64
62
dBc
Spurious-Free Dynamic SFDRX23 fIN = 30MHz
Range Excluding H2, H3
fIN = 105MHz
(Note 8)
88
95
99
dBc
91
93
96
dBc
fIN = 190MHz
88
91
92
dBc
fIN = 363MHz
86
85
89
dBc
fIN = 461MHz
88
82
87
dBc
fIN = 605MHz
87
81
83
dBc
fIN = 70MHz
87
87
86
dBFS
fIN = 170MHz
96
102
100
dBFS
fIN = 10MHz
90
100
105
dBFS
fIN = 121MHz
90
93
100
dBFS
10-12
10-12
700
700
Intermodulation
Distortion
IMD
Channel to Channel
Isolation
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
0
1
10
µA
-25
-12
-7
µA
4
12
µA
-415
-300
µA
INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (CLKDIV) (Note 9)
IIH
16
Input Current Low (CLKDIV)
IIL
-34
Input Capacitance
CDI
FN7570 Rev.2.0
Jul 6, 2021
-600
1.17
V
0.63
V
25
34
µA
-25
-16
µA
3
pF
Page 10 of 34
ISLA224P
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
LVDS INPUTS (CLKDIVRSTP,CLKDIVRSTN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak to peak, single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
k
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
k
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 10)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
D[13:0]N
D[13:0]P
tPD
A DATA
N-L
B DATA
N-L
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA
N
B DATA
N
FIGURE 3. LVDS
FN7570 Rev.2.0
Jul 6, 2021
Page 11 of 34
ISLA224P
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
A DATA
N-L
D[13:0]
B DATA
N-L
A DATA
N-L+1
B DATA
N-L+1
B DATA
N-1
A DATA
N
B DATA
N
FIGURE 4. CMOS
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
Latency (Pipeline Delay)
FN7570 Rev.2.0
Jul 6, 2021
L
1.65
2.4
3.5
ns
Rising/Falling Edge
-0.1
0.16
0.5
ns
Rising/Falling Edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
DLL recovery time after
Synchronous Reset
ns
0.35
ns
52
µs
10
cycles
Page 12 of 34
ISLA224P
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
Overvoltage Recovery
MIN
(Note 5)
CONDITION
MAX
(Note 5)
TYP
tOVR
UNITS
1
cycles
SPI INTERFACE (Notes 11, 12)
t
SCLK Period
CLK
Write Operation
7
cycles
tCLK
Read Operation
16
cycles
CSB to SCLKSetup Time
tS
Read or Write
28
cycles
CSB after SCLK Hold Time
tH
Write
5
cycles
CSB after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK Setup Time
tDS
Write
6
cycles
Data Valid after SCLK Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
-65
85
SFDR AT 250MSPS
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR AT 130MSPS
80
75
70
SNR AT 250MSPS
65
60
SNR AT 130MSPS
0
100
200
300
400
INPUT FREQUENCY (MHz)
FIGURE 5. SNR AND SFDR vs fIN
FN7570 Rev.2.0
Jul 6, 2021
500
600
HD3 AT 250MSPS
-70
HD3 AT 130MSPS
-75
-80
-85
HD2 AT 250MSPS
-90
HD3 AT 130MSPS
-95
-100
-105
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
FIGURE 6. HD2 AND HD3 vs fIN
Page 13 of 34
ISLA224P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
-30
100
SFDR(dBFS)
80
SNR AND SFDR
HD2 AND HD3 MAGNITUDE
90
70
SNR (dBfs)
60
50
SFDR (dBc)
40
SNR (dBc)
30
HD2(dBc)
-40
HD3 (dBc)
-50
-60
-70
-80
HD2(dBFS)
-90
-100
20
10
-60
-50
-40
-30
-20
-10
-110
-60
0
-50
INPUT AMPLITUDE (dBFS)
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
FIGURE 8. HD2 AND HD3 vs AIN
FIGURE 7. SNR AND SFDR vs AIN
90
-75
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
HD3 (dBFS)
85
80
SFDR
75
SNR
70
70
90
110
130
150
170
190
210
230
-85
-90
H2
-95
-100
-105
250
H3
-80
70
90
110
SAMPLE RATE (MSPS)
FIGURE 9. SNR AND SFDR vs fSAMPLE
130
150
170
190
SAMPLE RATE (MSPS)
210
230
250
FIGURE 10. HD2 AND HD3 vs fSAMPLE
1.0
0.8
775
0.6
725
0.4
DNL (LSBs)
TOTAL POWER (mW)
825
675
LVDS
625
575
0
-0.2
-0.4
525
-0.6
CMOS
475
425
40
0.2
-0.8
60
80
100 120 140 160 180
SAMPLE RATE (MSPS)
200
220
240
FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS AND CMOS MODES
FN7570 Rev.2.0
Jul 6, 2021
-1.0
0
2000
4000
6000
8000 10000 12000 14000 16000
CODES
FIGURE 12. DIFFERENTIAL NONLINEARITY
Page 14 of 34
ISLA224P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
80
3
78
SNR (dBFS) AND SFDR (dBc)
4
INL (LSBs)
2
1
0
-1
-2
-3
-4
0
2000
4000
6000
8000
76
74
72
70
68
66
64
62
60
0.75
10000 12000 14000 16000
0.85
0.95
1.05
INPUT COMMON MODE (V)
CODES
FIGURE 13. INTEGRAL NONLINEARITY
FIGURE 14. SNR AND SFDR vs VCM
80000
0
67595
60000
50000
40000
31240
30000
31658
20000
10000
0
0
2
25 871
4401
6397
63 62
6
0
-60
-80
-120
0
8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187
CODE
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 16. SINGLE-TONE SPECTRUM @ 105MHz
0
0
AIN = -1.0 dBFS
SNR = 71.1 dBFS
-20 SFDR = 74.65 dBc
SINAD = 69.1 dBFS
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
-100
FIGURE 15. NOISE HISTOGRAM
-40
-60
-80
-100
-120
AIN = -1.0 dBFS
SNR = 72.9 dBFS
SFDR = 77.3 dBc
SINAD = 71.3 dBFS
-20
57109
AMPLITUDE (dBFS)
NUMBER OF HITS
70000
1.15
AIN = -0.98 dBFS
SNR = 69.41 dBFS
-20 SFDR = 74.46 dBc
SINAD = 67.62 dBFS
-40
-60
-80
-100
0
20
40
60
80
FREQUENCY (MHz)
100
FIGURE 17. SINGLE-TONE SPECTRUM @ 190MHz
FN7570 Rev.2.0
Jul 6, 2021
120
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 18. SINGLE-TONE SPECTRUM @ 363MHz
Page 15 of 34
ISLA224P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-40
-60
-80
IMD3 = 87dBFS
-40
-60
IMD3 = 96dBFS
-80
-100
-100
-120
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 19. TWO-TONE SPECTRUM
(F1 = 70MHz, F2 = 71MHz AT -7dBFS)
Theory of Operation
Functional Description
The ISLA224P25 is based upon a 14-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (see Figure 21). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 20. TWO-TONE SPECTRUM
(F1 = 170MHz, F2 = 171MHz AT -7dBFS)
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 22. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the
nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
FN7570 Rev.2.0
Jul 6, 2021
Page 16 of 34
ISLA224P
CLOCK
GENERATION
INP
SHA
INN
1.25V
2.5-BIT
2.5-BIT
FLASH
FLASH
+
–
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1- BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 21. A/D CORE BLOCK DIAGRAM
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
A supply voltage variation of
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