LP3929

LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection December 14, 2007 LP3929 High Speed Bi-Directional Level Shifter and Ultra LowDropout CMOS Voltage Regulator and Line Protection General Description The LP3929 is designed for portable and wireless applications requiring level translation and power supply generation in a compact footprint. The device level translates 1.8 V LVCMOS on the host (A) side to 2.85 V LVCMOS levels on the card (B) side for a miniSD / SD 4-bit bi-directional data bus. Independent direct control of the CMD, Data0 and Data1-3 paths support mini SD state machine requirements. A shutdown pin is provided for the level shifters and regulator. The f_CLK_A is a feedback clock to the host which can be used to overcome level shifter bus delay. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 200 mA from a 3.05 V to 5.5 V input. It is stable with small 1.0 µF ±30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. The card (B port) side channels have integration of ASIP (Application Specific Integrated Passives) - on chip integrated pull-up, pull-down, series resistors and capacitors for EMC filtering. It is designed to tolerate IEC61000-4-2 level 4 ESD: ±15 kV air discharge, ±8 kV direct contact. Key Specifications Level Shifter: ■ 6-signal Level Shifter (5 bi-directional and 1 uni-direction) ■ 3 ns (typ) propagation delay ■ Channel-to-channel skew < 1 ns (max) Low-Dropout Regulator: ■ 3.05 V to 5.5 V input range ■ 2.85 V at 200 mA ■ Fast Turn-On time: 30 µs (typ) ■ 110 mV (max) dropout with 200 mA load ■ Thermal shutdown at 160°C (typ) Protection Block (B Side): ■ Robust IEC ESD Protection: ±15 kV Air Gap, ±8 kV Direct Contact ■ ASIP / EMI Filtering Features ■ Ultra small micro SMD 24 bump package ■ 6-signal level translation 1.8 V to 2.85 V ■ LDO stable with ceramic and high quality tantalum capacitors Typical Application Circuit 20186801 © 2007 National Semiconductor Corporation 201868 www.national.com LP3929 Block Diagram 20186802 www.national.com 2 LP3929 Package Outline and Connection Diagrams 20186812 Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” will designate the date code. The “TT” is a NSC internal code for die traceability; engineering sample parts will be marked as "ES". Both will vary considerably. The pin 1 marking identifier is the location of corner bump A1. Top View - TME24 Device Marking 20186811 Top View - Bump Underneath 24 Bump micro SMD Package See NSC Package Number TME24AAA Ordering Information For 24 Bump micro SMD Package Output Voltage Grade 2.85 V STD LP3929 Supplied As 250 Units, Tape & Reel LP3929TME-AACQ LP3929 Supplied As 3000 Units, Tape & Reel LP3929TMEX-AACQ Tape and Reel Information 20186810 Top View: Tape and Reel Information 3 www.national.com LP3929 Pin Descriptions Pin Name D0_A D1_A D2_A D3_A CMD_A CLK_A fCLK_A DIR_0 micro SMD Bump Identifier D1 E1 A1 B1 D2 C1 E2 A3 Port / Direction Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Input Host / Output Host / Input Type Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull High Z Push-Pull High Z Function 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V Input CLK Channel (Note 14) 1.8 V Output CLK Channel 1.8 V Input Direction Control D0 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) DIR_1-3 E3 Host / Input High Z 1.8 V Input Direction Control D1-D3 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) CMD_DIR A2 Host / Input High Z 1.8 V Input Direction Control CMD Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) EN C2 Host / Input High Z Device Enable with high impedance pull-down resistor (200 kΩ): VDDA = Device Active (on), VSS = Device Disabled (off) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) D1_B D2_B D3_B CMD_B CLK_B VBAT VDDA VDDB VSS VSS WP CD E5 A5 B5 D4 C5 A4 B3 B4 C3 C4 E4 D3 Host / Card Input Host / Card Input Pull-up Pull-up Card / Bidirectional Card / Bidirectional Card / Bidirectional Card / Bidirectional Card / Output Host / Input Host / Input Card / Output Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Power Power Power 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-down to VSS (470 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (15 kΩ) 2.85 V Output CLK Channel 3.05 V to 5.5 V 1.71 V to 1.92 V, 1.8 V (typ) 2.85 V (LDO output) Ground Ground Pull-up to VDDA (100 kΩ) Pull-up to VDDA (100 kΩ) D0_B D5 Card / Bidirectional Push-Pull www.national.com 4 LP3929 TABLE 1. Operation Modes Inputs EN L H H H H H H H H CMD_DIR X L L L L H H H H DIR_0 X L L H H L L H H DIR_1-3 X L H L H L H L H Level shifter / LDO = off (Shutdown Mode) All channels (D0-D3 and CMD): B → A Direction A → B Direction: D1-D3, B → A Direction: CMD and D0 A → B Direction: D0, B → A Direction: CMD and D1-D3 A → B Direction: D0-D3, B → A Direction: CMD A → B Direction: CMD, B → A Direction: D0-D3 A → B Direction: CMD and D1-D3, B → A Direction: D0 A → B Direction: CMD and D0, B → A Direction: D1-D3 All channels (D0-D3 and CMD): A → B Direction Mode H = VDDA, L = VSS 5 www.national.com LP3929 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VBAT) Supply Voltage (VDDA) LVCMOS A Port Input Voltage LVCMOS A Port I/O Voltage LVCMOS A Port I/O Voltage Junction Temperature Storage Temperature Lead Temperature (Note 13) Pad Temperature (Note 13) Derate micro SMD Package above 25°C −0.3V to +6.0V −0.3V to +3.3V −0.3V to VDDA + 0.3V −0.3V to VDDA + 0.3V −0.3V to VDDB + 0.3V 150°C −65°C to +150°C 235°C 235°C 22.9 mW/°C Maximum Power Dissipation Capacity at 25°C micro SMD ESD Rating HBM - MIL-STD-883E 3015.7 std. MM - JESD22-A115-A std. CDM - 500V (JESD22-C 101) Std. IEC61000-4-2 std., 330Ω, 150pF, Air Gap, B Side (Note 2) IEC61000-4-2 std., 330Ω, 150pF, Direct Contact, B Side (Note 2) 2.8 W ± 2kV ± 200V ± 500V ± 15kV ± 8kV Operating Conditions VBAT to VSS VDDA to VSS Ambient Temperature 3.05V to 5.5V 1.71V to 1.92V −30°C to +85°C Electrical Characteristics Symbol VIH Parameter Input Voltage High Level Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 4) Conditions Min 0.65×VDDA VDDA = 1.71V VDDA = 1.92V 1.1115 1.248 0 VDDA = 1.71V VDDA = 1.92V 0 0 −1 EN = VSS EN = VDDA −1 −1 −1 1.26 VSS 0.65×VDDB 0 VIH = VDDB D0_B to D2_B D3_B CMD_B −2 0 −5 − 80 −1 − 300 0.2 6.5 0.3 −40 0.1 − 200 45 − 20 0.75×VDDB 0.25×VDDB 0 0 0 0 1.8 0 Typ Max 1.92 1.92 1.92 0.30×VDDA 0.513 0.576 +1 +1 +10 +1 VDDA 0.45 VDDB 0.35×VDDB +2 + 13 +5 0 +1 − 20 Units V V V V V V µA µA µA µA V V V V µA µA µA µA µA µA µA µA V V LVCMOS A (Host) Port (VDDA = 1.71V to 1.92V) VIL Input Voltage Low Level IIH Input Current High Level VIH = VDDA IIL VOH VOL VIH VIL IIH Input Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level VIL = VSS IOH = −4 mA IOL = 4 mA LVCMOS B (Card) Port (VDDB = 2.85V) IIL Input Current Low Level VIL = VSS D0_B to D2_B D3_B CMD_B IOS + IOS − VOH VOL Short Circuit Current Output Voltage High Level Output Voltage Low Level VOUTlow = VDDB VOUThigh = VSS IOH = − 2 mA IOL = 2 mA www.national.com 6 LP3929 Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 4) Symbol Supply Current IDD IDDZ COUT Supply Current Supply Current — Shutdown Output Capacitance (Note 15) All Channels Static: A → B mode, LDO unloaded EN = VSS B (card) port VBAT VDDA VBAT VDDA 4 95 0.1 0.2 15 7 200 2 2 20 mA µA µA µA pF Parameter Conditions Min Typ Max Units Level Shifter AC Switching Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25°C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30°C to +85°C. (Notes 3, 5, 15, 16) Symbol tPLH Parameter Propagation Delay A to B or B to A Propagation Delay CLK_A to fCLK_A tPHL Propagation Delay A to B or B to A Propagation Delay CLK_A to fCLK_A tRISE tFALL tSKEW tEN tDIS tTA Rise Time A Side Output Figure 2 Rise Time B Side Output with ASIP Figure 2 Fall Time A Side Output Figure 2 Fall Time B Side Output with ASIP Figure 2 Skew between D0–D3, CLK and CMD outputs (either edge) Enable Time Disable Time Level-Shifter Direction Switch Response (Turn Around) Time Conditions CLB = 15 pF, CLA = 20 pF, 50%-50% CLA = 20 pF, 50%-50% CLB = 15 pF, CLA = 20 pF, 50%-50% CLA = 20 pF, 50%-50% CLA = 20 pF, 20%-70% CLB = 15 pF, 20%-70% CLA = 20 pF, 20%-70% CLB = 15 pF, 20%-70% Min Typ 3 5 3 5 1.1 1.6 1.0 1.9