RF3V49092

RF3V49092, RF3S49092SM Data Sheet November 1999 File Number 4600.1 20A/10A, 12V, 0.060/0.140 Ohm, Logic Level, Complementary Power MOSFET These complementary power MOSFETs are manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V to 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49092. Features • 20A, 12V (N-Channel) 10A, 12V (P-Channel) • rDS(ON) = 0.060Ω (N-Channel) rDS(ON) = 0.140Ω (P-Channel) • Temperature Compensating PSPICE® Model • On-Resistance vs Gate Drive Voltage Curves • Peak Current vs Pulse Width Curve • UIS Rating Curve Symbol S2 Ordering Information PART NUMBER RF3V49092 RF3S49092SM PACKAGE TS-001AA MO-169AB BRAND F3V49092 F3S49092 G2 D1 NOTE: When ordering, use the entire part number. For ordering the MO-169AB in tape and reel, add the suffix 9A to the part number, i.e., RF3S49092SM9A. G1 S1 Packaging JEDEC TS-001AA (ALTERNATE) S1 G1 D S2 G2 G2 S2 JEDEC MO-169AB D G1 S1 4-30 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-727-9207 | Copyright © Intersil Corporation 1999 RF3V49092, RF3S49092SM Absolute Maximum Ratings TC = 25oC Unless Otherwise Specified N-CHANNEL 12 12 ±10 20 Refer to Peak Current Curve Refer to UIS Curve 50 0.33 -55 to 175 300 260 P-CHANNEL -12 -12 ±10 10 Refer to Peak Current Curve Refer to UIS Curve 50 0.33 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed (Figures 5, 26) . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figures 6, 27). . . . . . . . . . . . . EAS Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . .Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications (N-Channel) PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TC = 25oC, Unless Otherwise Specified TEST CONDITIONS ID = 250µA, VGS = 0V, (Figure 13) VGS = VDS, ID = 250µA, (Figure 12) VDS = 12V, VGS = 0V VGS = ±10V ID = 20A, VGS = 5V, (Figure 9, 11) VDD = 6V, ID ≈ 20A, RL = 0.24Ω, VGS = 5V, RGS = 25Ω (Figure 10) TC = 25o C TC = 150o C MIN 12 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 9.6V, ID = 20A, RL = 0.42Ω (Figure 15) TS-001AA, and MO-169AB TYP 18 60 50 60 20 12 0.9 750 700 275 MAX 1 50 ±100 0.060 100 140 25 15 1.2 3.00 62 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W SYMBOL BVDSS VGS(TH) IDSS Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RθJC RθJA VDS = 10V, VGS = 0V, f = 1MHz (Figure 14) N-Channel Source to Drain Diode Specifications PARAMETER Source to Drain Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 20A ISD = 20A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 100 UNITS V ns 4-31 RF3V49092, RF3S49092SM Electrical Specifications (P-Channel) PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TC = 25o C, Unless Otherwise Specified TEST CONDITIONS ID = 250µA, VGS = 0V, (Figure 34) VGS = VDS, ID = 250µA, (Figure 33) VDS = -12V, VGS = 0V VGS = ±10V ID = 10A, VGS = -5V, (Figures 30, 32) VDD = -6V, ID ≈ 10A, RL = 0.62Ω, VGS = -5V, RGS = 25Ω (Figure 31) TC = 25o C TC = 150o C MIN -12 -1 VGS = 0V to -10V VGS = 0V to -5V VGS = 0V to -1V VDD = -9.6V, ID = 10A, RL = 1.0Ω (Figure 36) TS-001AA, and MO-169AB TYP 25 65 40 45 19 10 0.8 775 550 150 MAX -1 -50 ±100 0.140 115 110 24 14 1.1 3.00 62 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W SYMBOL BVDSS VGS(TH) IDSS Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-5) Qg(TH) CISS COSS CRSS RθJC RθJA VDS = -10V, VGS = 0V, f = 1MHz (Figure 35) P-Channel Source to Drain Diode Specifications PARAMETER Source to Drain Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = -10A ISD = -10A, dISD/dt = -100A/µs MIN TYP MAX -1.5 100 UNITS V ns Typical Performance Curves (N-Channel) 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 ID , DRAIN CURRENT (A) 25 20 15 10 5 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 4-32 RF3V49092, RF3S49092SM Typical Performance Curves (N-Channel) DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 10-1 100 101 (Continued) 1 ZθJC, NORMALIZED THERMAL IMPEDANCE SINGLE PULSE 0.01 10-5 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 IDM, PEAK CURRENT CAPABILITY (A) TJ = MAX RATED, TC = 25oC 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I ID, DRAIN CURRENT (A) = I25 175 - TC 150 10 5ms 10ms 100ms 1s DC 100 VGS = 5V OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 -5 10 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 10 0 101 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 50 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 100 IAS, AVALANCHE CURRENT (A) 50 VGS = 10V VGS = 5V VGS = 4.5V STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 1 10 0.1 tAV, TIME IN AVALANCHE (ms) 100 ID , DRAIN CURRENT (A) 40 VGS = 4V 30 20 VGS = 3V 10 PULSE DURATION = 80µs, TC = 25oC DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 6 7 NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 4-33 RF3V49092, RF3S49092SM Typical Performance Curves (N-Channel) 50 25oC VDD = 6V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 175oC ID, DRAIN CURRENT (A) 40 -55oC (Continued) 200 I D = 5A 150 I D = 10A 100 I D = 20A 30 20 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 6 7 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 140 120 SWITCHING TIME (ns) 100 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 6V, ID = 20A, RL = 0.24Ω tr 1.6 PULSE DURATION = 80µs, VGS = 5V, ID = 20A DUTY CYCLE = 0.5% MAX 1.4 t D(OFF) 80 60 40 20 t D(ON) 0 0 10 20 30 40 50 tf 1.2 1.0 0.8 0.6 -80 -40 RGS, GATE TO SOURCE RESISTANCE (Ω) 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 ID = 250µA 1.0 1.1 0.8 1.0 0.6 -80 -40 0 40 80 120 160 200 0.9 -80 -40 TJ, JUNCTION TEMPERATURE (oC) 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4-34 RF3V49092, RF3S49092SM Typical Performance Curves (N-Channel) 1200 (Continued) 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 9.6V 8 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz 900 CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 600 CISS COSS 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A ID = 5A 0 5 15 10 Qg, GATE CHARGE (nC) 20 25 CRSS 300 2 0 0 0 2 4 6 8 10 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE Test Circuits and Waveforms (N-Channel) VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS tON td(ON) VDS VDS VGS RL + tOFF td(OFF) tr tf 90% 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS 4-35 RF3V49092, RF3S49092SM Test Circuits and Waveforms (N-Channel) VDS RL VDD VDS VGS = 10V VGS + (Continued) Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V DUT Ig(REF) FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS Typical Performance Curves (P-Channel) 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 ID , DRAIN CURRENT (A) -10 -15 -5 0 25 50 100 125 75 TC, CASE TEMPERATURE (oC) 150 175 FIGURE 22. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 23. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 1 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 10-1 100 101 SINGLE PULSE 0.01 10-5 t, RECTANGULAR PULSE DURATION (s) FIGURE 24. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-36 RF3V49092, RF3S49092SM Typical Performance Curves (P-Channel) -100 TJ = MAX RATED, TC = 25oC (Continued) -200 IDM, PEAK CURRENT CAPABILITY (A) -100 ID, DRAIN CURRENT (A) TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I VGS = -10V VGS = -5V = I25 175 - TC 150 -10 5ms 10ms 100ms 1s DC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 -1 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 25. FORWARD BIAS SAFE OPERATING AREA FIGURE 26. PEAK CURRENT CAPABILITY -100 IAS, AVALANCHE CURRENT (A) -40 VGS = -10V I D, DRAIN CURRENT (A) PULSE DURATION = 80µs, TC = 25oC DUTY CYCLE = 0.5% MAX -30 STARTING TJ = 25oC -10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] -1 0.01 10 0.1 1 tAV, TIME IN AVALANCHE (ms) 100 -20 VGS = -5V VGS = -4.5V -10 VGS = -4V VGS = -3V 0 0 -1 -2 -3 -4 -5 -6 -7 VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 28. SATURATION CHARACTERISTICS FIGURE 27. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY -40 VDD = -6V ID, DRAIN CURRENT (A) 25oC 175oC rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 500 ID = -3A 400 I D = -6A 300 ID = -10A -30 - 55oC -20 200 -10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 -2 -4 -6 -8 -10 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 0 -4 -6 -8 -2 VGS, GATE TO SOURCE VOLTAGE (V) -10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 29. TRANSFER CHARACTERISTICS FIGURE 30. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-37 RF3V49092, RF3S49092SM Typical Performance Curves (P-Channel) 120 100 SWITCHING TIME (ns) 80 60 tD(OFF) 40 tD(ON) 20 0 tf NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = -6V, ID = -10A, RL = 0.62Ω tr (Continued) 1.6 PULSE DURATION = 80µs, VGS = -5V, ID = -10A DUTY CYCLE = 0.5% MAX 1.4 1.2 1.0 0 10 20 30 40 50 0.8 -80 -40 RGS, GATE TO SOURCE RESISTANCE (Ω) 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 31. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE FIGURE 32. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = -250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 ID = -250µA 1.0 1.1 0.8 1.0 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 33. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1200 CISS C, CAPACITANCE (pF) 900 COSS 600 CRSS 300 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD FIGURE 34. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = -9.6V -8 -6 -4 WAVEFORMS IN DESCENDING ORDER: ID = -10A ID = -6A ID = -3A 0 3 9 6 Qg, GATE CHARGE (nC) 12 15 -2 0 0 -2 -4 -6 -8 VDS, DRAIN TO SOURCE VOLTAGE (V) -10 0 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 35. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 36. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 4-38 RF3V49092, RF3S49092SM Test Circuits and Waveforms (P-Channel) VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01Ω IAS tP BVDSS VDS FIGURE 37. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 38. UNCLAMPED ENERGY WAVEFORMS tON td(ON) VDS RL VGS 0 tr 10% tOFF td(OFF) tf 10% VDD VGS RGS + VDS VGS 0 90% 90% DUT 10% 50% PULSE WIDTH 90% 50% FIGURE 39. SWITCHING TIME TEST CIRCUIT FIGURE 40. RESISTIVE SWITCHING WAVEFORMS VDS RL 0 VGS= -1V VGS VDD + Qg(TH) VDS -VGS Qg(-5) VDD Qg(TOT) 0 Ig(REF) VGS= -5V DUT Ig(REF) VGS= -10V FIGURE 41. GATE CHARGE TEST CIRCUIT FIGURE 42. GATE CHARGE WAVEFORMS 4-39 RF3V49092, RF3S49092SM Soldering Precautions The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 1. Always preheat the device. 2. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 3. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 4. The peak temperature in the soldering process should be at least 30oC higher than the melting point of the solder chosen. 5. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 6. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 7. During cooling, mechanical stress or shock should be avoided. 4-40 RF3V49092, RF3S49092SM PSPICE Electrical Model SUBCKT RF3V49092 2 1 3; CA 12 8 9.77e-10 CB 15 14 9.19e-10 CIN 6 8 7.81e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 14.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 12 GATE 1 N-Channel Model rev 9/6/94 DPLCAP 10 5 LDRAIN DRAIN 2 DBREAK RDRAIN ESG + EVTO 9 20 + 18 8 LGATE RGATE 6 8 VTO + 11 16 21 6 MOS1 RIN CIN 8 RSOURCE EBREAK MOS2 17 18 + DBODY 7 LSOURCE 3 SOURCE S1A 13 8 S1B CA + EGS 6 8 14 13 S2A 15 S2B 13 CB EDS + 14 5 8 IT RBREAK 17 18 RVTO 19 VBAT + RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.91e-3 RGATE 9 20 2.74 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.3215 .MODEL DBDMOD D (IS = 7.00e-13 RS = 2.15e-2 TRS1 = 0.5e-3 TRS2 = 3.68e-6 CJO = 1.28e-9 TT = 1.8e-8) .MODEL DBKMOD D (RS = 1.28e-1 TRS1 = 1.69e-3 TRS2 = -2.0e-6) .MODEL DPLCAPMOD D (CJO = 0.84e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.63 KP = 11.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.15e-4 TC2 = 3.13e-7) .MODEL RDSMOD RES (TC1 = 7.00e-4 TC2 = 5.00e-6) .MODEL RVTOMOD RES (TC1 = -2.155e-3 TC2 = -2.7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -4.05) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF= -6.05) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.72 VOFF= 4.28) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.28 VOFF= -0.72) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options ; IEEE Power Electronics Specialist Conference Records, 1991. 4-41 RF3V49092, RF3S49092SM PSPICE Electrical Model SUBCKT RF3V49092 2 1 3 ; CA 12 8 8.75e-10 CB 15 14 8.65e-10 CIN 6 8 7.65e-10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD DPLCAP P-Channel Model rev 11/8/94 ESG 10 8 6 + 5 LDRAIN DRAIN 2 RDRAIN EBREAK 5 11 17 18 -23.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 7.36e-3 RGATE 9 20 6.1 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 4.56e-2 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD GATE 1 + 16 VTO EVTO 20 + 8 18 LGATE RGATE 9 6 MOS1 RIN CIN 8 RSOURCE 7 DBREAK + 21 EBREAK 17 18 MOS2 11 DBODY LSOURCE 3 SOURCE S1A 12 S1B CA + EGS 6 8 13 8 14 13 S2A 15 S2B 13 CB EDS + 14 5 8 IT RBREAK 17 18 RVTO 19 VBAT + VBAT 8 19 DC 1 VTO 21 6 -0.558 .MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8) .MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5) .MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.61e-4 TC2 = -1.09e-6) .MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6) .MODEL RVTOMOD RES (TC1 = -1.82e-3 TC2 = 1.47e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 4-42