RFD7N10LE

RFD7N10LE, RFD7N10LESM Data Sheet October 1999 File Number 3598.3 7A, 100V, 0.300 Ohm, N-Channel, Logic Level, Power MOSFETs These N-Channel power MOSFETs are manufactured using a modern process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V to 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49046. Features • 7A, 100V • rDS(ON) = 0.300Ω • Temperature Compensating PSPICE® Model • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER RFD7N10LE RFD7N10LESM PACKAGE TO-251AA TO-252AA 7N10L 7N10LE BRAND Symbol D G NOTE: When ordering, use the entire part number. Add suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD7N10LESM9A. S Packaging JEDEC TO-251AA SOURCE DRAIN GATE GATE SOURCE JEDEC TO-252AA DRAIN (FLANGE) DRAIN (FLANGE) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFD7N10LE, RFD7N10LESM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg RFD7N10LE, RFD7N10LESM 100 100 +10, -8 7 Refer to Peak Current Curve Refer to UIS Curve 47 0.318 -55 to 175 300 260 UNITS V V V A W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250µA, VGS = 0V VGS = VDS, ID = 250µA VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC MIN 100 1 VGS = 0 to 10V VGS = 0 to 5V VGS = 0 to 1V VDS = 25V, VGS = 0V f = 1MHz VDD = 80V ID = 7A, RL = 11.4Ω TO-251 and TO-252 Package TYP 10 65 23 18 125 67 3.7 360 70 20 MAX 3 1 250 10 0.300 110 60 150 80 4.5 3.15 100 UNITS V V µA µA µA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RθJC RθJA VGS = +10, -8V ID = 7A, VGS = 5V VDD = 50V, ID = 7A RL = 7.1Ω, VGS = 5V RGS = 2.5Ω Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 7A ISD = 7A, dISD/dt = 100A/µs MIN TYP MAX 1.5 130 UNITS V ns 2 RFD7N10LE, RFD7N10LESM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0 25 50 75 100 125 150 175 6 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) Unless Otherwise Specified 8 4 2 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZθJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 0.01 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM X ZθJC X RθJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 20 14 10 100µs IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) 20 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 14 VGS = 5V 10 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 ( 200 5 10-3 10-2 175 - TC ) 150 10-1 101 100 102 t, PULSE WIDTH (ms) 103 104 1ms 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED 0.1 1 10ms VDSS MAX = 100V 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 3 RFD7N10LE, RFD7N10LESM Typical Performance Curves 20 IAS , AVALANCHE CURRENT (A) 14 10 STARTING TJ = 25oC STARTING TJ = 150oC ID , DRAIN CURRENT (A) Unless Otherwise Specified (Continued) 15 VGS = 10V VGS = 5V VGS = 4.5V 10 VGS = 4V 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 0 1.5 4.5 3.0 6.0 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 3V If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.001 0.01 0.1 1 0 tAV, TIME IN AVALANCHE (ms) 7.5 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS 15 NORMALIZED ON RESISTANCE ID, DRAIN CURRENT (A) VDD = 15V -55oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3.0 25oC 175oC 2.5 2.0 1.5 1.0 0.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 7A 10 5 0 0 1 2 3 4 5 6 7 VGS , GATE TO SOURCE VOLTAGE (V) 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 1.5 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA 2.0 ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.5 1.0 1.0 0.5 0.5 0 -80 -40 0 40 80 120 160 200 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4 RFD7N10LE, RFD7N10LESM Typical Performance Curves 600 Unless Otherwise Specified (Continued) 100 VDD = BVDSS 75 VDD = BVDSS 3.75 5.00 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD CISS 400 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS 2.50 200 COSS CRSS 0 0 5 10 15 20 25 VDS , DRAIN TO SOURCE VOLTAGE (V) 25 RL = 14.28Ω IG(REF) = 0.24mA VGS = 5V 1.25 0 0 20 --------------------I G ( ACT ) I G ( REF ) t, TIME (µs) 80 --------------------I G ( ACT ) I G ( REF ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON VDS VDS VGS RL + tOFF td(OFF) tr tf 90% td(ON) 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 5 RFD7N10LE, RFD7N10LESM PSPICE Electrical Model SUBCKT RFD7N10LE 2 1 3; CA 12 8 7.5e-10 CB 15 14 7.6e-10 CIN 6 8 4.03e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 6/2/93 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.7e-9 LSOURCE 3 7 3.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9.4e-2 RGATE 9 20 3.3 RLDRAIN 2 5 10 RLGATE 1 9 37 RLSOURCE 3 7 34 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.3e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3 S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*17.3),3.5))} .MODEL DBODYMOD D (IS = 1.2e-12 RS = 1.2e-2 TRS1 = 1.2e-3 TRS2 = 1.03e-6 CJO = 6.7e-10 TT = 6.9e-8 M = 0.77) .MODEL DBREAKMOD D (RS = 9.9e-1 TRS1 = 1e-3 TRS2 = -2e-5) .MODEL DPLCAPMOD D (CJO = 4.3e-10 IS = 1e-30 M = 0.9 N = 10) .MODEL MMEDMOD NMOS (VTO = 1.88 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.3) .MODEL MSTROMOD NMOS (VTO = 2.13 KP = 12.4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.59 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 8.1e-3 TC2 = 2.4e-5) .MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = 2e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.5e-3 TC2 = -4.3e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1.5e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.5 VOFF= -2.5) VON = -2.5 VOFF= -4.5) VON = -0.3 VOFF= 0.2) VON = 0.2 VOFF= -0.3) NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991. 6 + - EBREAK 11 7 17 18 116.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 DBODY MWEAK MMED RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES RFD7N10LE, RFD7N10LESM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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