RFG40N10LE

RFG40N10LE, RFP40N10LE, RF1S40N10LESM Data Sheet October 1999 File Number 4061.5 40A, 100V, 0.040 Ohm, Logic Level N-Channel Power MOSFETs These N-Channel enhancement mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49163. Features • 40A, 100V • rDS(ON) = 0.040Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Ordering Information PART NUMBER RFG40N10LE RFP40N10LE RF1S40N10LESM PACKAGE TO-247 TO-220AB TO-263AB BRAND FG40N10L FP40N10L F40N10LE Symbol D G NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A. S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) JEDEC TO-220AB SOURCE DRAIN GATE JEDEC TO-263AB DRAIN (FLANGE) GATE SOURCE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFG40N10LE, RFP40N10LE, RF1S40N10LESM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG40N10LE, RFP40N10LE, RF1S40N10LESM 100 100 ±10 40 Refer to Peak Current Curve Refer to UIS Curve 150 1.00 -55 to 175 300 260 UNITS V V V A Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RθJC RθJA All Packages TO-247 TO-220AB and TO-263AB VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 80V, ID = 40A, RL = 2.0Ω (Figures 20, 21) TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 13) VGS = VDS, ID = 250µA (Figure 12) VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC VGS = ±10V ID = 40A, VGS = 5V VDD = 50V, ID = 40A, RL = 1.25Ω, VGS = 5V, RGS = 2.5Ω (Figures 10, 18, 19) MIN 100 1 TYP 22 140 70 65 145 85 3 3000 500 200 MAX 3 1 250 10 0.040 200 165 180 105 4 1.0 30 80 UNITS V V µA µA µA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Case Thermal Resistance Junction-to-Ambient VDS = 25V, VGS = 0V, f = 1MHz (Figure 14) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL VSD trr ISD = 40A ISD = 40A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 205 UNITS V ns 2 RFG40N10LE, RFP40N10LE, RF1S40N10LESM Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 ID, DRAIN CURRENT (A) Unless Otherwise Specified 50 40 30 20 10 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1 ZθJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 100 101 PDM FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 500 IDM, PEAK CURRENT CAPABILITY (A) TC = 25oC TJ = 175oC 500 VGS = 10V VGS = 5V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:  175 – TC  I = I 25  ----------------------- 150   ID, DRAIN CURRENT (A) 100 100µs 1ms 10ms 100 10 THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) TC = 25oC 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 100 200 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 3 RFG40N10LE, RFP40N10LE, RF1S40N10LESM Typical Performance Curves 500 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC Unless Otherwise Specified (Continued) 80 ID, DRAIN CURRENT (A) 100 VGS = 10V VGS = 5V VGS = 4V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 60 40 VGS = 3V 20 VGS = 2.5V 10 STARTING TJ = 150oC 1 0.001 0.01 0.1 1 10 0 0 1.5 3.0 4.5 6.0 tAV, TIME IN AVALANCHE (ms) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) 80 VDD = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -55oC 25oC rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) 175oC 100 ID = 10A 75 ID = 40A ID = 80A 60 40 50 ID = 20A 25 PULSE DURATION = 80µs, VDD = 15V DUTY CYCLE = 0.5% MAX. 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 20 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 700 600 SWITCHING TIME (ns) 500 400 300 200 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VDD = 50V, ID = 40A, RL= 1.25Ω td(OFF) 2.50 PULSE DURATION = 80µs, DUTY CYCLE = 0.5% MAX. VGS = 5V, ID = 40A 2.00 tr 1.50 tf 1.00 td(ON) 100 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE (Ω) 0.50 0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4 RFG40N10LE, RFP40N10LE, RF1S40N10LESM Typical Performance Curves 1.50 VGS = VDS, ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE Unless Otherwise Specified (Continued) 1.50 ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.25 1.25 1.00 1.00 0.75 0.75 0.50 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0.50 -80 -40 160 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 200 FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 3500 CISS 2800 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 100 VDD = BVDSS 75 RL = 2.5Ω IG(REF) = 1.7mA VGS = 5V PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I G ( REF ) I G ( REF ) VDD = BVDSS 3.75 5.00 VGS , GATE TO SOURCE VOLTAGE (V) 2100 VDS , DRAIN TO SOURCE VOLTAGE (V) 50 2.50 1400 25 1.25 700 COSS CRSS 0 0 0 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 --------------------I G ( ACT ) t, TIME (µs) 80 --------------------I G ( ACT ) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS 5 RFG40N10LE, RFP40N10LE, RF1S40N10LESM Test Circuits and Waveforms (Continued) tON VDS VDS VGS RL + tOFF td(OFF) tr tf 90% td(ON) 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS RL VDD VDS Qg(10) OR Qg(5) + Qg(TOT) VGS VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES VDD DUT Ig(REF) VGS VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH) Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS 6 RFG40N10LE, RFP40N10LE, RF1S40N10LESM PSPICE Electrical Model SUBCKT 40N10LE 2 1 3 ; CA 12 8 3.50e-9 CB 15 14 3.50e-9 CIN 6 8 1.70e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 8/15/95 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 5.17e-9 LSOURCE 3 7 2.13e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.04e-2 RGATE 9 20 2.15 RLDRAIN 2 5 10 RLGATE 1 9 51.7 RLSOURCE 3 7 21.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3 S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))} .MODEL DBODYMOD D (IS = 1.96e-12 RS = 3.87e-3 TRS1 = 9.93e-4 TRS2 = 4.97e-6 CJO = 1.53e-9 TT = 7.41e-8 M = 0.50) .MODEL DBREAKMOD D (RS = 3.12e-1 TRS1 = 1.07e-3 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 1.97e-9 IS = 1e-30 M = 0.87) .MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15) .MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.50 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.5 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.74e-4 TC2 = -3.71e-7) .MODEL RDRAINMOD RES (TC1 = 9.71e-3 TC2 = 2.90e-5) .MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6) .MODEL RVTEMPMOD RES (TC1 = -1.52e-3 TC2 = -1.21e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.00 VOFF= -1.50) VON = -1.50 VOFF= -6.00) VON = -0.50 VOFF= 0.0) VON = 0.0 VOFF= -0.50) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 7 + - EBREAK 11 7 17 18 120.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 DBODY MWEAK MMED RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES RFG40N10LE, RFP40N10LE, RF1S40N10LESM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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