RFP3055LE

RFD3055LE, RFD3055LESM, RFP3055LE Data Sheet November 1999 File Number 4044.3 11A, 60V, 0.107 Ohm, Logic Level, N-Channel Power MOSFETs These N-Channel enhancement-mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49158. Features • 11A, 60V • rDS(ON) = 0.107Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D Ordering Information PART NUMBER RFD3055LE RFD3055LESM RFP3055LE PACKAGE TO-251AA TO-252AA TO-220AB BRAND F3055L G F3055L FP3055LE S NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252 variant in tape and reel, e.g. RFD3055LESM9A. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) JEDEC TO-251AA SOURCE DRAIN GATE JEDEC TO-252AA DRAIN (FLANGE) GATE SOURCE 6-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999 RFD3055LE, RFD3055LESM, RFP3055LE Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD3055LE, RFD3055LESM, RFP3055LE 60 60 ±16 11 Refer to Peak Current Curve Refer to UIS Curve 38 0.25 -55 to 175 300 260 UNITS V V V A Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg W W/oC oC oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RθJC RθJA TO-220AB TO-251AA, TO-252AA VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDS = 25V, VGS = 0V, f = 1MHz (Figure 14) VDD = 30V, ID = 8A, Ig(REF) = 1.0mA (Figures 20, 21) TEST CONDITIONS ID = 250µA, VGS = 0V VGS = VDS, ID = 250µA VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC VGS = ±16V ID = 8A, VGS = 5V (Figure 11) VDD ≈ 30V, ID = 8A, VGS = 4.5V, RGS = 32Ω (Figures 10, 18, 19) MIN 60 1 TYP 8 105 22 39 9.4 5.2 0.36 350 105 23 MAX 3 1 250 ±100 0.107 170 92 11.3 6.2 0.43 3.94 62 100 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF oC/W oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 8A ISD = 8A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.25 66 UNITS V ns 6-2 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) ID, DRAIN CURRENT (A) VGS = 10V 10 VGS = 4.5V Unless Otherwise Specified 15 5 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1 THERMAL IMPEDANCE ZθJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101 SINGLE PULSE 0.01 10-5 10-4 FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE 100 200 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 ID, DRAIN CURRENT (A) IDM, PEAK CURRENT (A) 100 10 100µs 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1ms 10ms VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 10-1 100 101 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200 10 10-5 t, PULSE WIDTH (s) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY 6-3 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves 100 IAS, AVALANCHE CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 10 STARTING TJ = 150oC Unless Otherwise Specified (Continued) 15 VGS = 10V ID, DRAIN CURRENT (A) 12 VGS = 5V VGS = 4V 9 VGS = 3.5V 6 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3 TC = 25oC 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS = 3V 4 1 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 0 NOTE: Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS 15 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 150 ID = 3A ID = 11A ID = 5A 120 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 12 ID, DRAIN CURRENT (A) 9 6 TJ = 25oC 90 3 TJ = 175oC 0 2 3 TJ = -55oC 60 4 5 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 150 tr 100 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 4.5V, VDD = 30V, ID = 8A SWITCHING TIME (ns) 2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 tf 50 td(OFF) td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE (Ω) 1.0 VGS = 10V, ID = 11A 0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 6-4 RFD3055LE, RFD3055LESM, RFP3055LE Typical Performance Curves 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE Unless Otherwise Specified (Continued) 1.2 ID = 250µA 1.0 1.1 0.8 1.0 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS , GATE TO SOURCE VOLTAGE (V) 1000 CISS = CGS + CGD C, CAPACITANCE (pF) 10 VDD = 30V 8 100 COSS ≅ CDS + CGD 6 4 2 VGS = 0V, f = 1MHz 10 0.1 CRSS = CGD 60 WAVEFORMS IN DESCENDING ORDER: ID = 11A ID = 5A ID = 3A 0 2 4 6 Qg, GATE CHARGE (nC) 8 10 0 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01Ω 0 tAV FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS 6-5 RFD3055LE, RFD3055LESM, RFP3055LE Test Circuits and Waveforms (Continued) tON VDS VDS VGS RL + tOFF td(OFF) tr tf 90% td(ON) 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 18. SWITCHING TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS VDS RL VDD VDS Qg(10) OR Qg(5) + Qg(TOT) VGS VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES VDD DUT Ig(REF) VGS VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH) Ig(REF) 0 FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS 6-6 RFD3055LE, RFD3055LESM, RFP3055LE PSPICE Electrical Model .SUBCKT RFD3055LE 2 1 3 ; CA 12 8 3.9e-9 CB 15 14 4.9e-9 CIN 6 8 3.25e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev 1/30/95 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.42e-9 LSOURCE 3 7 2.57e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.7e-2 RGATE 9 20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 54.2 RLSOURCE 3 7 25.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.50e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3 S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))} .MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6) .MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81) .MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4 VOFF= -2.5) VON = -2.5 VOFF= -4) VON = -0.5 VOFF= 0) VON = 0 VOFF= -0.5) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 6-7 + - EBREAK 11 7 17 18 67.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 DBODY MWEAK MMED RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES RFD3055LE, RFD3055LESM, RFP3055LE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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