RFP70N03, RF1S70N03SM
Data Sheet July 1999 File Number
3404.4
70A, 30V, 0.010 Ohm, N-Channel Power MOSFETs
These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49025.
Features
• 70A, 30V • rDS(ON) = 0.010Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve (Single Pulse) • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Ordering Information
PART NUMBER RFP70N03 RF1S70N03SM PACKAGE TO-220AB TO-263AB BRAND RFP70N03 F1S70N03
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-263AB
DRAIN (FLANGE)
DRAIN (FLANGE)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFP70N03, RF1S70N03SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified 30 30 ±20 70 200 Figures 5, 13, 14 150 1.0 -55 to 175 300 260 UNITS V V V A A W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 10) VGS = VDS, ID = 250µA (Figure 9) VDS = 30V, VGS = 0V VDS = 30V, VGS = 0V, TC = 150oC MIN 30 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 24V, ID ≅ 70A, RL = 0.343Ω Ig(REF) = 1.0mA (Figure 12) (Figure 3) TO-220, TO-263 TYP 20 20 40 25 215 120 6.5 3300 1750 750 MAX 4 1 50 100 0.010 80 125 260 145 8.0 1.0 62 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RθJC RθJA
VGS = ±20V ID = 70A, VGS = 10V (Figure 8) VDD = 15V, ID ≅ 70A, RL = 0.214Ω, VGS = 10V, RGS = 2.5Ω
VDS = 25V, VGS = 0V, f = 1MHz (Figure 11)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 70A ISD = 70A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
2
RFP70N03, RF1S70N03SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 60 50 40 30 20 10 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 0.8 0.6 0.4 0.2 0 80 70
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
ZθJC, NORMALIZED THERMAL IMPEDANCE
100 0.5
0.2 10-1 0.1 0.05 0.02 0.01 SINGLE PULSE 10-2 -5 10 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-0 101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300 IAS, AVALANCHE CURRENT (A) 100µs 300 IDM STARTING TJ = 25oC STARTING TJ = 150oC
100 ID, DRAIN CURRENT (A)
1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 1
100
10
If R = 0 tAV = (L) (IAS)/(1.3 x RATED BVDSS - VDD) 10 If R ≠ 0 tAV = (L/R) ln [(IAS x R)/(1.3 x RATED BVDSS - VDD) +1] 0.01 0.10 1 10 tAV, TIME IN AVALANCHE (ms)
1
VDSS(MAX) = 30V 10 50
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
3
RFP70N03, RF1S70N03SM Typical Performance Curves
200 VGS = 10V VGS = 8V VGS = 7V 160 ID, DRAIN CURRENT (A) DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 6V 80 VGS = 5V 40 VGS = 4V 0 0 0 1.5 3.0 4.5 6.0 7.5 0 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 160
(Continued)
200
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V
-55oC 25oC
120
120
175oC
80
40
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
NORMALIZED GATE THRESHOLD VOLTAGE
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 70A
2.0 VGS = VDS , ID = 250µA 1.6
1.5
1.2
1.0
0.8
0.5
0.4
0 -80
-40
0
40
80
120
160
200
0 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.6 C, CAPACITANCE (pF)
7000 6000 5000
CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
1.2
4000 3000 2000 1000
CRSS
0.8
COSS
0.4
0 -80
-40
0
40
80
120
160
200
0
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (oC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
4
RFP70N03, RF1S70N03SM Typical Performance Curves
VDS, DRAIN SOURCE VOLTAGE (V)
(Continued)
10.0 VDD = BVDSS VDD = BVDSS VGS, GATE SOURCE VOLTAGE (V)
30.0
22.5
7.5
15.0 0.75BVDSS 0.75BVDSS 0.50BVDSS 0.50BVDSS 0.25BVDSS 0.25BVDSS RL = 0.43Ω Ig(REF) = 3.0mA VGS = 10V I g ( REF ) t, TIME (µs) I g ( REF )
5.0
7.5
2.5
0
0
20 -------------------I g ( ACT )
80 -------------------I g ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01Ω
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. SWITCHING WAVEFORMS
5
RFP70N03, RF1S70N03SM Test Circuits and Waveforms
VDS RL VDD VDS VGS = 20V VGS
+
(Continued)
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORM
6
RFP70N03, RF1S70N03SM PSPICE Electrical Model
.SUBCKT RFP70N03 2 1 3 ; *NOM TEMP = 25oC CA 12 8 6.09e-9 CB 15 14 6.05e-9 CIN 6 8 3.40e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 30.7e-6 RGATE 9 20 0.890 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBDMOD D (IS=7.91e-12 RS=3.87e-3 TRS1=2.71e-3 TRS2=2.50e-7 CJO=4.84e-9 TT=4.51e-8) .MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5) .MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7) .MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6) .MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
CA + EGS 6 -8 S1A 12 13 8 S1B S2A 15 14 13 S2B 13 CB 14 + 5 EDS 8 IT 19 VBAT + 5 10 ESG 6 +8 + GATE 1 LGATE 9 20 RGATE EVTO 18 8 DPLCAP 16 MOS2 21 MOS1 CIN 8 RSOURCE 11 EBREAK RIN 17 18 + DBODY RDRAIN DBREAK DRAIN 2 LDRAIN
rev 9/16/92
-
6
VTO
-
+
7 LSOURCE 3 SOURCE 18 RVTO
17
RBREAK
-
-
7
RFP70N03, RF1S70N03SM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
8
RFP70N03, RF1S70N03SM
Data Sheet July 1999 File Number
3404.4
70A, 30V, 0.010 Ohm, N-Channel Power MOSFETs
These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49025.
Features
• 70A, 30V • rDS(ON) = 0.010Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve (Single Pulse) • 175oC Operating Temperature • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Ordering Information
PART NUMBER RFP70N03 RF1S70N03SM PACKAGE TO-220AB TO-263AB BRAND RFP70N03 F1S70N03
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-263AB
DRAIN (FLANGE)
DRAIN (FLANGE)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFP70N03, RF1S70N03SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified 30 30 ±20 70 200 Figures 5, 13, 14 150 1.0 -55 to 175 300 260 UNITS V V V A A W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250µA, VGS = 0V (Figure 10) VGS = VDS, ID = 250µA (Figure 9) VDS = 30V, VGS = 0V VDS = 30V, VGS = 0V, TC = 150oC MIN 30 2 VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 24V, ID ≅ 70A, RL = 0.343Ω Ig(REF) = 1.0mA (Figure 12) (Figure 3) TO-220, TO-263 TYP 20 20 40 25 215 120 6.5 3300 1750 750 MAX 4 1 50 100 0.010 80 125 260 145 8.0 1.0 62 UNITS V V µA µA nA Ω ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 10V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RθJC RθJA
VGS = ±20V ID = 70A, VGS = 10V (Figure 8) VDD = 15V, ID ≅ 70A, RL = 0.214Ω, VGS = 10V, RGS = 2.5Ω
VDS = 25V, VGS = 0V, f = 1MHz (Figure 11)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time SYMBOL VSD trr ISD = 70A ISD = 70A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
2
RFP70N03, RF1S70N03SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 60 50 40 30 20 10 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 0.8 0.6 0.4 0.2 0 80 70
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
ZθJC, NORMALIZED THERMAL IMPEDANCE
100 0.5
0.2 10-1 0.1 0.05 0.02 0.01 SINGLE PULSE 10-2 -5 10 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 10-0 101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300 IAS, AVALANCHE CURRENT (A) 100µs 300 IDM STARTING TJ = 25oC STARTING TJ = 150oC
100 ID, DRAIN CURRENT (A)
1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 1
100
10
If R = 0 tAV = (L) (IAS)/(1.3 x RATED BVDSS - VDD) 10 If R ≠ 0 tAV = (L/R) ln [(IAS x R)/(1.3 x RATED BVDSS - VDD) +1] 0.01 0.10 1 10 tAV, TIME IN AVALANCHE (ms)
1
VDSS(MAX) = 30V 10 50
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
3
RFP70N03, RF1S70N03SM Typical Performance Curves
200 VGS = 10V VGS = 8V VGS = 7V 160 ID, DRAIN CURRENT (A) DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 6V 80 VGS = 5V 40 VGS = 4V 0 0 0 1.5 3.0 4.5 6.0 7.5 0 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 160
(Continued)
200
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V
-55oC 25oC
120
120
175oC
80
40
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
NORMALIZED GATE THRESHOLD VOLTAGE
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 70A
2.0 VGS = VDS , ID = 250µA 1.6
1.5
1.2
1.0
0.8
0.5
0.4
0 -80
-40
0
40
80
120
160
200
0 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250µA 1.6 C, CAPACITANCE (pF)
7000 6000 5000
CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
1.2
4000 3000 2000 1000
CRSS
0.8
COSS
0.4
0 -80
-40
0
40
80
120
160
200
0
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (oC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
4
RFP70N03, RF1S70N03SM Typical Performance Curves
VDS, DRAIN SOURCE VOLTAGE (V)
(Continued)
10.0 VDD = BVDSS VDD = BVDSS VGS, GATE SOURCE VOLTAGE (V)
30.0
22.5
7.5
15.0 0.75BVDSS 0.75BVDSS 0.50BVDSS 0.50BVDSS 0.25BVDSS 0.25BVDSS RL = 0.43Ω Ig(REF) = 3.0mA VGS = 10V I g ( REF ) t, TIME (µs) I g ( REF )
5.0
7.5
2.5
0
0
20 -------------------I g ( ACT )
80 -------------------I g ( ACT )
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01Ω
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. SWITCHING WAVEFORMS
5
RFP70N03, RF1S70N03SM Test Circuits and Waveforms
VDS RL VDD VDS VGS = 20V VGS
+
(Continued)
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V
DUT Ig(REF)
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORM
6
RFP70N03, RF1S70N03SM PSPICE Electrical Model
.SUBCKT RFP70N03 2 1 3 ; *NOM TEMP = 25oC CA 12 8 6.09e-9 CB 15 14 6.05e-9 CIN 6 8 3.40e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 30.7e-6 RGATE 9 20 0.890 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBDMOD D (IS=7.91e-12 RS=3.87e-3 TRS1=2.71e-3 TRS2=2.50e-7 CJO=4.84e-9 TT=4.51e-8) .MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5) .MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7) .MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6) .MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
CA + EGS 6 -8 S1A 12 13 8 S1B S2A 15 14 13 S2B 13 CB 14 + 5 EDS 8 IT 19 VBAT + 5 10 ESG 6 +8 + GATE 1 LGATE 9 20 RGATE EVTO 18 8 DPLCAP 16 MOS2 21 MOS1 CIN 8 RSOURCE 11 EBREAK RIN 17 18 + DBODY RDRAIN DBREAK DRAIN 2 LDRAIN
rev 9/16/92
-
6
VTO
-
+
7 LSOURCE 3 SOURCE 18 RVTO
17
RBREAK
-
-
7
RFP70N03, RF1S70N03SM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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