TW6869-TA1-CR

8-in-1 Video Decoders with PCI Express Media Bridge TW6869 The TW6869 is a highly integrated solution that supports multi-channel video and audio capture via PCIe x1 interface for PC DVR system and video analytic application. It contains high quality eightchannel NTSC/PAL/SECAM video decoders that convert analog composite video signal to digital component YCbCr data, and utilize adaptive 4H comb filter for separating luminance and chrominance to reduce cross noise artifacts. TW6869 contains a high performance proprietary DMA controller that fully optimizes the utilization of PCIe x1 bandwidth and enables it to transfer video and audio data at a high throughput rate that closely approaches the theoretical limit of PCIex1 interface. TW6869 is able to simultaneously decode and transfer 8 real time D1 video, or up to 32 channel nonreal time D1, plus 8 channel audio. TW6869 decreases the complexity and workload of client-side software development, and significantly reduces the strains on PC hardware and resources. TW6869 also includes a software development kit (SDK) with Windows and Linux compliant drivers and reference application software. Features Video Decoders  Accepts all NTSC(M/N/4.43) / PAL(B/D/G/H/I/K/L/M/N/60) standards with auto detection  Integrated eight video analog anti-alias filters and 10-bit CMOS ADCs  IF compensation filter for improvement of color demodulation  Color Transient Improvement (CTI)  White peak AGC control  Programmable hue, saturation, contrast, brightness and sharpness  High quality proprietary fast video locking system for non-real-time application  High performance adaptive 4H comb filters for all NTSC and PAL standards 1 FN7867.1 February 29, 2012    Audio Codecs Integrated eight audio ADCs 8/16 bit audio word length Sample audio with 8/16/32/44.1/48kHz DMA Controller  Highly-efficient DMA design can support up to 8 real time D1 video and 8 real time audio channels, or up to 32 non-real- time video with optimization of full PCIex1 bandwidth  Multiple video format output support: UYVY/Y422, YUYV/YUY2, IYU1/Y411, Y41P, YUV420, RGB555 and RGB565  Integrated internal video and audio generator simplifies system test and development  Built-in motion detection engine for each video channel  Hardware-friendly design enables smooth data transfer and virtually eliminates unwanted big-block data jamming among PC devices, resulting in optimized PC internal bandwidth consumption PCIe Configurations  PCI Express Base Specification 1.1 Compliant  Flexible PCIe packet size configuration: 128 byte, 256 byte and 512 byte options Applications  PC-based DVR system  Video analytic system 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. TW6869 Block Diagram Analog Video 32-CH Analog Audio 8-CH AIN1 … AIN8 VIN1 … VIN32 … … 8-Ch Video Decoder 8-Ch Audio ADC & Codec Data Power Mgmt. XTAL PLL GPIO GPIO & Ext. Controller XADM Bus Video Process Motion Detection FIFO Control Unit Video DMA Controller Audio DMA Controller LBC RADM CXPL Core PCIe PHY PCI-e Finger 2 Internal Video & Audio Generator CDM TW6869 Pin Descriptions ANALOG INTERFACE PINS (40) 3 NAME NUMBER TYPE DESCRIPTION VIN1A 139 A Composite video inputs VIN1B 140 A Composite video inputs VIN1C 141 A Composite video inputs VIN1D 142 A Composite video inputs VIN2A 4 A Composite video inputs VIN2B 3 A Composite video inputs VIN2C 2 A Composite video inputs VIN2D 1 A Composite video inputs VIN3A 7 A Composite video inputs VIN3B 8 A Composite video inputs VIN3C 9 A Composite video inputs VIN3D 10 A Composite video inputs VIN4A 16 A Composite video inputs VIN4B 15 A Composite video inputs VIN4C 14 A Composite video inputs VIN4D 13 A Composite video inputs VIN5A 42 A Composite video inputs VIN5B 41 A Composite video inputs VIN5C 40 A Composite video inputs VIN5D 39 A Composite video inputs VIN6A 33 A Composite video inputs VIN6B 34 A Composite video inputs VIN6C 35 A Composite video inputs VIN6D 36 A Composite video inputs VIN7A 30 A Composite video inputs VIN7B 29 A Composite video inputs VIN7C 28 A Composite video inputs VIN7D 27 A Composite video inputs VIN8A 21 A Composite video inputs VIN8B 22 A Composite video inputs VIN8C 23 A Composite video inputs TW6869 NAME NUMBER TYPE DESCRIPTION VIN8D 24 A Composite video inputs AIN1 133 A Analog audio inputs AIN2 134 A Analog audio inputs AIN3 135 A Analog audio inputs AIN4 136 A Analog audio inputs AIN5 48 A Analog audio inputs AIN6 47 A Analog audio inputs AIN7 46 A Analog audio inputs AIN8 45 A Analog audio inputs NAME NUMBER TYPE TX_M 87 O TX_P 88 O RX_P 90 I RX_M 91 I REXT 93 IO REFCLK_P 95 I REFCLK_M 96 I PCI EXPRESS INTERFACE (7) DESCRIPTION High-Speed Differential Transmit Pair High-Speed Differential Receive Pair Reference Resistor Connection. 190Ω 1% precision resistor to ground Differential Reference Clock Input SYSTEM CONTROL PINS (50) 4 NAME NUMBER TYPE DESCRIPTION XTALI 109 IO System reference clock crystal input (27MHz) XTALO 110 IO System reference clock crystal output PERST_N 84 I System reset. TEST[1:0] 53,52 I Test mode selection, tie to ground GPIO[42:0] 129,128,127,126,125, 124,123,122,121,118, 117,116,115,114,113, 108,107,106,105,104, 103,102,101,81,80,79 ,78,77,76,75,70,69,68 ,67,66,65,64,63,62,59 ,58,57,56 IO T_SEL 54 I GPIO control ports NC TW6869 NAME NUMBER TYPE R_SEL 55 I DESCRIPTION NC POWER / GROUND PINS (47) 5 NAME NUMBER TYPE DESCRIPTION VP 85,98 P Low-Voltage Supply (1.2V) VPH 86,97 P High-Voltage I/O Supply (3.3V) GD 89,92,94 G Digital Ground VDD33 51,71,82,100,119 P Digital I/O Power, 3.3V VSS33 50,72,83,99,120 G Digital Ground VDD12 19,61,74,111,131 P Digital Core Power, 1.2V VSS12 18,60,73,112,130 G Digital Core Ground VDDA 132,49 P Analog Power for Audio ADC, 3.3V VSSA 137,44 G Analog Ground for Audio ADC VDDV 138,5,6,17,20,31,32,43 P Analog Power for Video ADC, 3.3V VSSV 143,144,11,12,25,26,37,38 G Analog Ground for Video ADC TW6869 Pin Configuration 6 AIN2 AIN1 VDDA1 VDD12 VSS12 GP42 GP41 GP40 GP39 GP38 GP37 GP36 GP35 GP34 VSS33 VDD33 GP33 GP32 GP31 GP30 GP29 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 XTALO AIN3 135 XTALI AIN4 136 109 VSSA1 137 VDD12 VDDV1 138 110 VIN1A 139 111 VIN1B 140 GP28 VIN1C 141 VSS12 VIN1D 142 112 VSSV1 143 113 VSSV2 144 144 TQFP PIN DIAGRAM (TOP -> BOTTOM VIEW) VIN2D 1 108 GP27 VIN2C 2 107 GP26 VIN2B 3 106 GP25 VIN2A 4 105 GP24 VDDV2 5 104 GP23 VDDV3 6 103 GP22 VIN3A 7 102 GP21 VIN3B 8 101 GP20 VIN3C 9 100 VDD33 VIN3D 10 99 VSS33 VSSV3 11 98 VP VSSV4 12 97 VPH VIN4D 13 96 REFCLK_M VIN4C 14 95 REFCLK_P VIN4B 15 94 GD VIN4A 16 93 REXT VDDV4 17 92 GD VSS12 18 91 RX_M VDD12 19 90 RX_P VDDV8 20 89 GD VIN8A 21 88 TX_P VIN8B 22 87 TX_M VIN8C 23 86 VPH VIN8D 24 85 VP VSSV8 25 84 PERST_N VSSV7 26 83 VSS33 VIN7D 27 82 VDD33 VIN7C 28 81 GP19 VIN7B 29 80 GP18 VIN7A 30 79 GP17 VDDV7 31 78 GP16 VDDV6 32 77 GP15 VIN6A 33 76 GP14 VIN6B 34 75 GP13 VIN6C 35 74 VDD12 VIN6D 36 73 VSS12 TW6869 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 VDDV5 VSSA2 AIN8 AIN7 AIN6 AIN5 VDDA2 VSS33 VDD33 TEST0 TEST1 T_SEL R_SEL GP0 / TCK GP1 / TMS GP2 / TDI GP3 / TDO VSS12 VDD12 GP4 GP5 GP6 GP7 GP8 GP9 GP10 GP11 72 42 VIN5A VSS33 41 VIN5B 71 40 VIN5C 70 39 VIN5D GP12 38 VSSV5 VDD33 37 VSSV6 TQFP-144L 20x20 TW6869 Ordering Information PART NUMBER (NOTE 1) TW6869-TA1-CR PART MARKING PACKAGE (PB-FREE) PKG. DWG. # TW6869 TA1-CR 144 LEAD TQFP (20mmx20mm) Q144.20X20C TW6869-TA1-CRH TW6869 TA1-CR (Note 2) 144 LEAD TQFP (20mmx20mm) Q144.20X20C NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. “H” version supports Industrial Temperature operation. See Supply Current and Power Dissipation table on page 115. 7 TW6869 Table of Contents Video Decoder ...................................................................................................................................... 9 Video Input Formats ............................................................................................................................... 9 Analog Frontend ................................................................................................................................... 10 Decimation Filter ................................................................................................................................. 11 Automatic Gain Control and Clamping ............................................................................................. 12 Sync Processing ................................................................................................................................... 12 Y/C Separation ..................................................................................................................................... 13 Color Decoding ..................................................................................................................................... 14 Chrominance Demodulation .......................................................................................................... 14 ACC (Automatic Color Gain Control) ............................................................................................. 15 Chrominance Processing .................................................................................................................... 15 Chrominance Gain, Offset and Hue Adjustment ......................................................................... 15 CTI (Color Transient Improvement) ............................................................................................... 15 Luminance Processing ........................................................................................................................ 15 Video Cropping ..................................................................................................................................... 16 Video Scaler .......................................................................................................................................... 17 Audio Codec ........................................................................................................................................ 19 Audio Detection .................................................................................................................................... 19 DMA Controller ................................................................................................................................... 20 Internal Video & Audio Generator ..................................................................................................... 20 Control Unit ......................................................................................................................................... 20 GPIO & Ext. Controller ........................................................................................................................ 20 PCI Express EndPoint Controller ....................................................................................................... 20 PCI Express PHY ................................................................................................................................. 20 Host Interface ......................................................................................................................................... 20 Register Description ............................................................................................................................ 27 DMA Controller ................................................................................................................................. 27 Video Decoder & Audio Codec (CH0 ~ CH3) ................................................................................ 70 (Starting from 0x100) ..................................................................................................................... 70 Video Decoder & Audio Codec (CH4~CH7) .................................................................................. 97 PCIe Endpoint Controller................................................................................................................. 98 Parametric Information ...................................................................................................................... 114 Absolute Maximum Ratings ........................................................................................................... 114 Recommended Operating Conditions ........................................................................................... 114 DC Electrical Parameters................................................................................................................ 114 Supply Current and Power Dissipation .......................................................................................... 115 Video Decoder Parameter 1 ........................................................................................................... 115 Video Decoder Parameter 2 ........................................................................................................... 116 Analog Audio Parameters .............................................................................................................. 117 Audio Decimation Filter Response ................................................................................................ 117 Application Schematic ........................................................................................................................ 118 Package Dimension ............................................................................................................................ 119 Revision History ................................................................................................................................... 120 8 TW6869 Functional Description Video Decoder VIDEO INPUT FORMATS The TW6869 has built-in automatic standard discrimination circuitry. The circuit uses burst-phase, burstfrequency and frame rate to identify NTSC, PAL or SECAM color signals. The standards that can be identified are NTSC (M), NTSC (4.43), PAL (B, D, G, H, I), PAL (M), PAL (N), PAL (60) and SECAM (M). Each standard can be included or excluded in the standard recognition process by software control. The exceptions are the base standard NTSC and PAL, which are always enabled. The identified standard is indicated by the Standard Selection (SDT) register. Automatic standard detection can be overridden by software controlled standard selection. TW6869 supports all common video formats as shown in Table 1. TABLE 1. VIDEO INPUT FORMATS SUPPORTED BY THE TW6869 FORMAT LINES FSC COUNTRY NTSC-M 525 60 3.579545MHz U.S., many others NTSC-Japan (1) 525 60 3.579545MHz Japan PAL-B, G, N 625 50 4.433619MHz Many PAL-D 625 50 4.433619MHz China PAL-H 625 50 4.433619MHz Belgium PAL-I 625 50 4.433619MHz Great Britain, others PAL-M 525 60 3.575612MHz Brazil PAL-CN 625 50 3.582056MHz Argentina SECAM 625 50 4.406MHz 4.250MHz France, Eastern Europe, Middle East, Russia PAL-60 525 60 4.433619MHz China NTSC (4.43) 525 60 4.433619MHz Transcoding Notes: (1). NTSC-Japan has 0 IRE setup. 9 FIELDS TW6869 ANALOG FRONTEND The TW6869 contains four 10-bit ADC (Analog to Digital Converters) to digitize the analog video inputs. The ADC can be put into power-down mode by the V_ADC_PWDN register. The TW6869 also contains an antialiasing filter to prevent out-of-band frequency in analog video input signal. Therefore, there is no need for external components in the analog input pin except for an AC coupling capacitor and a termination resistor. Figure 1 shows the frequency response of the anti-aliasing filter. 0 -5 -10 Gain (dB) -15 -20 -25 -30 -35 -40 0 0.2 0.4 0.6 0.8 1 1.2 Frequency (Hertz) 1.4 1.6 FIGURE 1. THE FREQUENCY RESPONSE OF ANTI-ALIASING FILTER 10 1.8 2 7 x 10 TW6869 Decimation Filter The digitized composite video data is over-sampled to simplify the design of the analog filter. The decimation filter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image when down-sampled. Figure 2 shows the characteristic of the decimation filter. 0 -5 Magnitude Response (dB) -10 -15 -20 -25 -30 -35 -40 -45 -50 0 2 4 6 8 Frequency (Hertz) 10 FIGURE 2. THE CHARACTERISTIC OF THE DECIMATION FILTER 11 12 6 x 10 TW6869 AUTOMATIC GAIN CONTROL AND CLAMPING All four analog channels have built-in clamping circuits that restore the signal DC level. The Y channel restores the back porch of the digitized video to a level of 60. This operation is automatic through internal feedback loop. The Automatic Gain Control (AGC) of the Y channel adjusts input gain so that the sync tip is at a desired level. Programmable white peak protection logic is included to prevent saturation in the case of abnormal signal proportion between sync and white peak level. SYNC PROCESSING The sync processor of TW6869 detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-video or component signal. The processor contains a digital phaselocked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals, such as those from VCR fast forward or backward. The vertical sync separator detects the vertical synchronization pattern in the input video signals. In addition, the actual sync determination is controlled by a detection window to provide more reliable synchronization. An option is available to provide faster responses for certain applications. The field status is determined at vertical synchronization time. The field logic can also be controlled to toggle automatically while tracking the input. 12 TW6869 Y/C SEPARATION The color-decoding block contains the luma/chroma separation for the composite video signal and multistandard color demodulation. For NTSC and PAL standard signals, the luma/chroma separation can be done either by comb filter or notch/band-pass filter combination. For SECAM standard signals, adaptive notch/band-pass filter is used. The default selection for NTSC/PAL is comb filter. In the case of comb filter, the TW6869 separates luma (Y) and chroma (C) of a NTSC/PAL composite video signal using a proprietary 4H adaptive comb filter. The filter uses a four-line buffer. Adaptive logic combines the upper-comb and the lower-comb results based on the signal changes among the previous, current and next lines. This technique leads to excellent Y/C separation with small cross luma and cross color at both horizontal and vertical edges Due to the line buffer used in the comb filter, there are always two lines processing delay at the output except for the component input mode, which has only one line delay. If notch/band-pass filter is selected, the characteristics of the filters are shown in the filter curve section. Figure 3 shows the frequency response of the notch filter for each system NTSC and PAL. Figure 4 shows the frequency response of Chroma Band Pass Filter Curves. 5 0 -5 NTSC PAL -10 Gain (dB) -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 Frequency (Hertz) 6 7 FIGURE 3. THE CHARACTERISTICS OF LUMINANCE NOTCH FILTER FOR PAL 13 8 6 x 10 TW6869 0 -5 Magnitude Response (dB) -10 PAL/SEAM -15 NTSC -20 -25 -30 -35 -40 -45 -50 0 1 2 3 4 5 Frequency (Hertz) 6 7 8 9 6 x 10 FIGURE 4. CHROMA BAND PASS FILTER CURVES COLOR DECODING Chrominance Demodulation The color demodulation for NTSC and PAL standard is done by first quadrature mixing the chroma signal to the base band. A low-pass filter is then used to remove carrier signal and yield chroma components. The lowpass filter characteristic can be selected for optimized transient color performance. For the PAL system, the PAL ID or the burst phase switching is identified to aid the PAL color demodulation. For SECAM, the color information is FM modulated onto a different carrier. The demodulation process therefore consists of FM demodulator and de-emphasis filter. During the FM demodulation, the chroma carrier frequency is identified and used to control the SECAM color demodulation. The sub-carrier signal for use in the color demodulator is generated by direct digital synthesis PLL that locks onto the input sub-carrier reference (color burst). This arrangement allows any sub-standard of NTSC and PAL to be demodulated easily with single crystal frequency. Figure 5 shows the frequency response of Chrominance Low-Pass Filter Curves. 14 TW6869 0 CBW=3 -5 CBW=2 -10 CBW=1 -15 CBW=0 Gain (dB) -20 High Lo w -25 Med -30 -35 -40 -45 -50 0 1 2 3 Frequency (Hertz) 4 5 6 6 x 10 FIGURE 5. CHROMINANCE LOW-PASS FILTER CURVES ACC (Automatic Color Gain Control) The Automatic Chroma Gain Control (ACC) compensates for reduced amplitudes caused by high-frequency loss in video signal. In the NTSC/PAL standard, the color reference signal is the burst on the back porch. It is measured to control the chroma output gain. The range of ACC control is –6db to +24db. CHROMINANCE PROCESSING Chrominance Gain, Offset and Hue Adjustment When decoding NTSC signals, TW6869 can adjust the hue of the chroma signal. The hue is defined as a phase shift of the subcarrier with respect to the burst. This phase shift of NTSC decoding can be programmed through a control register. For the PAL standard, the PAL delay line is provided to compensate any hue error; therefore, there is no hue adjustment available. The color saturation can be adjusted by changing the gain of Cb and Cr signals for all NTSC, PAL and SECAM formats. The Cb and Cr gain can be adjusted independently for flexibility. CTI (Color Transient Improvement) The TW6869 provides the Color Transient Improvement function to further enhance the image quality. The CTI enhance the color edge transient without any overshoot or under-shoot. LUMINANCE PROCESSING The TW6869 adjusts brightness by adding a programmable value (in register BRIGHTNESS) to the Y signal. It adjusts the picture contrast by changing the gain (in register CONTRAST) of the Y signal. The TW6869 also provide programmable peaking function to further enhance the video sharpness. The peaking control has built-in coring function to prevent enhancement of noise. 15 TW6869 Figure 6 shows the characteristics of the peaking filter for four different gain modes and different center frequencies. 16 14 Magnitude Response (dB) 12 10 8 6 4 2 0 0 1 2 3 4 Frequency (Hertz) 5 6 7 6 x 10 FIGURE 6. THE CHARACTERISTIC OF LUMINANCE PEAKING FILTER VIDEO CROPPING Cropping allows only subsection of a video image to be output. The active video region is determined by HDELAY, HACTIVE, VDELAY and VACTIVE register as illustrated in Figure 6. The VACTIVE signal can be programmed to indicate the number of active lines to be displayed in a video field, and the HACTIVE signal can be programmed to indicate the number of active pixels to be displayed in a video line. The start of the field or frame in the vertical direction is indicated by the leading edge of VSYNC. The start of the line in the horizontal direction is indicated by the leading edge of the HSYNC. The start of the active lines from vertical sync edge is indicated by the VDELAY register. The start of the active pixels from the horizontal edge is indicated by the HDELAY register. The sizes and location of the active video are determined by HDELAY, HACTIVE, VDELAY, and VACTIVE registers. These registers are 8-bit wide, the lower 8-bits is, respectively, in HDELAY_LO, HACTIVE_LO, VDELAY_LO, and VACTIVE_LO. Their upper 2-bit shares the same register CROP_HI. The Horizontal delay register (HDELAY) determines the number of pixels delay between the leading edge of HSYNC and the leading edge of the HACTIVE. Note that this value is referenced to the un-scaled pixel number. The Horizontal active register (HACTIVE) determines the number of active pixels to be output or scaled after the delay from the sync edge is met. This value is also referenced to the un-scaled pixel number. Therefore, if the scaling ratio is changed, the active video region used for scaling remain unchanged as set by the HACTIVE register, but the valid pixels output are equal or reduced due to down scaling. In order for the cropping to work properly, the following equation should be satisfied. HDELAY + HACTIVE < Total number of pixels per line For NTSC output at 13.5MHz pixel rate, the total number of pixels is 858. For PAL output at 13.5MHz rate, the total number of pixels is 864. HACTIVE should be set to 720. The Vertical delay register (VDELAY) determines the number of lines delay between the leading edge of the VSYNC and the start of the active video lines. It indicates number of lines to skip at the start of a frame before asserting the VACTIVE signal. This value is referenced to the incoming scan lines before the vertical scaling. The number of scan lines is 525 for the 60Hz systems and 625 for the 50Hz systems. The Vertical 16 TW6869 active register (VACTIVE) determines the number of lines to be used in the vertical scaling. Therefore, the number of scan lines output is equal or less than the value set in this register depending on the vertical scaling ratio. In order for the vertical cropping to work properly, the following equation should be observed. VDELAY + VACTIVE < Total number of lines per field FIGURE 7. THE EFFECT OF CROPPING REGISTERS VIDEO SCALER The TW6869 can independently reduce the output video image size in both horizontal and vertical directions using arbitrary scaling ratios up to 1/16 in each direction. The horizontal scaling employs a dynamic 6-tap 32-phase interpolation filter for luma and a 2-tap 8-phase interpolation filter for chroma because of the limited bandwidth of the chroma data. The vertical scaling uses simple line dropping algorithm. Therefore, the use of non-integer vertical scaling ration is not recommended. Downscaling is achieved by programming the horizontal scaling ratio register (HSCALE) and vertical scaling ratio register (VSCALE). When outputting unscaled video, the TW6869 will output CCIR601 compatible 720 pixels per line or any number of pixels per line as specified by the HACTIVE register. The standard output for Square Pixel mode is 640 pixels for 60Hz system and 768 pixels for 50Hz systems. If the number of output pixels required is smaller than 720 in CCIR601 compatible mode or the number specified by the HACTIVE register, the 12-bit HSCALE register, which is the concatenation of two 8-bit registers SCALE_HI and HSCALE_LO, is used to reduce the output pixels to the desired number. Following is an example using pixel ratio to determine the horizontal scaling ratio. These equations should be used to determine the scaling ratio to be written into the 12-bit HSCALE register assuming HACTIVE is programmed with 720 active pixels per line: 17 NTSC: HSCALE = [720/Npixel_desired] * 256 PAL: HSCALE = [(720/Npixel_desired)] * 256 TW6869 Where: Npixel_desired is the nominal number of pixel per line. For example, to output a CCIR601 compatible NTSC stream at SIF resolution, the HSCALE value can be found as: HSCALE = [(720/320)] * 256 = 576 = 0x0240 However, to output a SQ compatible NTSC stream at SIF resolution, the HSCALE value should be found as: HSCALE = [(640/320)] * 256 = 512 = 0x200 In this case, with total resolution of 768 per line, the HACTIVE should have a value of 640. The vertical scaling determines the number of vertical lines output by the TW6869. The vertical scaling register (VSCALE) is a 12-bit register, which is the concatenation of a 4-bit register SCALE_HI and an 8-bit register VSCALE_LO. The maximum scaling ratio is 16:1. The following equations should be used to determine the scaling ratio to be written into the 12-bit VSCALE register assuming VACTIVE is programmed with 240 or 288 active lines per field. 60Hz system: VSCALE = [240/ Nline_desired] * 256 50Hz system: VSCALE = [288/ Nline_desired] * 256 Where: Nline_desired is the number of active lines output per field. The scaling ratios for some popular formats are listed in Table 2. Figure 8 shows the Horizontal Scaler PreFilter Curves. TABLE 2. HSCALE AND VSCALE VALUE FOR SOME POPULAR VIDEO FORMATS. SCALING RATIO 1:1 2:1 (CIF) 4:1 (QCIF) 18 FORMAT NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 NTSC SQ NTSC CCIR601 PAL SQ PAL CCIR601 TOTAL RESOLUTION OUTPUT RESOLUTION HSCALE VALUES VSCALE (FRAME) 780x525 858x525 944x625 864x625 390x262 429x262 472x312 432x312 195x131 214x131 236x156 216x156 640x480 720x480 768x576 720x576 320x240 360x240 384x288 360x288 160x120 180x120 192x144 180x144 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400 0x0100 0x0100 0x0100 0x0100 0x0200 0x0200 0x0200 0x0200 0x0400 0x0400 0x0400 0x0400 TW6869 0 Magnitude Response (dB) -5 -10 HFLT[1:0]=1 HFLT[1:0]=2 -15 -20 HFLT[1:0]=3 -25 -30 -35 -40 0 0.05 0.1 0.15 0.2 0.25 0.3 Fsig/Fsample 0.35 0.4 0.45 0.5 FIGURE 8. HORIZONTAL SCALER PRE-FILTER CURVES Motion Detection The TW6869 supports a motion detector for each of the 8 video decoders. The built-in motion detection algorithm uses the difference of luminance level between current and the reference field. To detect motion properly according to situation needed, the TW6869 provides several sensitivity and velocity control parameters for each motion detector. The TW6869 supports manual strobe function to update motion detection so that it is more appropriate for user-defined motion sensitivity control. When motion is detected in any video inputs, the TW6869 updates its motion status registers. Through which the host processor can read the motion information. Audio Codec The audio codec in the TW6869 is composed of 8 audio Analog-to-Digital converters, audio mixer and audio detector. The TW6869 can accept 8 analog audio signals, and produce 8 channel digital audio data. The level of analog audio input signal AIN1 ~ AIN8 can be adjusted respectively by internal programmable gain amplifiers that are defined via the AIGAIN1, AIGAIN2, AIGAIN3 and AIGAIN4 registers and then sampled by each Analog-to-Digital converters. The TW6869 can mix all of analog audio inputs according to the predefined mixing ratio for each audio via the MIX_RATIO1 ~ MIX_RATIO4 registers. This mixing audio output can also be transferred through PCIe interface. AUDIO DETECTION The TW6869 has an audio detector for individual 8 channels. There are 2 kinds of audio detection method defined by the AAMPMD. One is the detection of absolute amplitude and the other is of differential amplitude. For both detection methods, the accumulating period is defined by the ADET_FILT register and the detecting threshold value is defined by the ADET_TH1 ~ ADET_TH4 registers. 19 TW6869 DMA Controller This module mainly packs the received video and audio data to the defined maximum payload size and manages the target address of each transaction layer package. It uses round-robin arbitration among DMA channels to choose current on-duty one. The Legacy PCI INT_A compatible interrupt emulation is supported to interrupt PC. Internal Video & Audio Generator To assist video debugging, this generator outputs 8 different colorbar patterns for each video DMA channel. Each colorbar pattern includes 7 vertical color bars and 1 horizontal black/grey color whose position and width are adjustable. To assist audio debugging, this generator outputs 8 different single tones with adjustable sampling rate. The 9th audio pattern is a mixing mode whose tone is chosen from one of others with register setting. Control Unit This module handles configuration and control through PCIe to all internal blocks and registers such as DMA controller and PCIe EndPoint Controller. GPIO & Ext. Controller This module controls all GPIO pins, configures external TW2864 through serial control pins (SCLK and SDAT), and resets external TW2864 through RST_TO_2864 pin. PCI Express EndPoint Controller This controller contains three main PCI Express protocol layers: Transaction later, Data Link Layer, and Physical Layer. It complies with PCI Express Base Specification, Revision 1.1, and PCI Express 2.0 Base Specification, Revision 2.0. It works with external x1 PHY through the standard PHY Interface for PCI Express (PIPE). PCI Express PHY This module is PCI express physical layer. Host Interface The TW6869 provides with PCI Express interface for programming and controlling. 20 TW6869 For Video Decoder and Audio Codec CH0~CH3. (*: Read only register/bit) B[31:8] are hardwired to 0 in all registers. Address CH1 CH2 CH3 Mnemonic CH4 R/W BIT7 BIT6 BIT5 BIT4 VDLOSS* HLOCK* SLOCK* FIELD* BIT3 BIT2 BIT1 BIT0 Default VLOCK* RESERVED* MONO* DET50* 0x00 0x100 0x110 0x120 0x130 VIDSTAT* R 0x101 0x111 0x121 0x131 BRIGHT R/W BRIGHTNESS 0x102 0x112 0x122 0x132 CONTRAST R/W CONTRAST 0x103 0x113 0x123 0x133 SHARPNESS R/W 0x104 0x114 0x124 0x134 SAT_U R/W SAT_U 0x80 0x105 0x115 0x125 0x135 SAT_V R/W SAT_V 0x80 0x106 0x116 0x126 0x136 HUE R/W HUE 0x107 0x117 0x127 0x137 CROP_HI R/W 0x108 0x118 0x128 0x138 VDELAY_LO R/W VDELAY[7:0] 0x12 0x109 0x119 0x129 0x139 VACTIVE_LO R/W VACTIVE[7:0] 0xF0 0x10A 0x11A 0x12A 0x13A HDELAY_LO R/W HDELAY[7:0] 0x0F 0x10B 0x11B 0x12B 0x13B HACTIVE_LO R/W HACTIVE[7:0] SCURVE 0x00 0x64 VSF VDELAY[9:8] CTI 0x11 SHARPNESS 0x00 VACTIVE[9:8] HDELAY[9:8] 0x02 HACTIVE[9:8] 0x10C 0x11C 0x12C 0x13C MVSN* R SF* PF* FF* KF* CSBAD* MCVSN* CSTRIPE* CTYPE* 0x D0 0x00 0x10D 0x11D 0x12D 0x13D STATUS2* R VCR* WKAIR* WKAIR1* VSTD* NINTL* 0 0 0 0x00 0x10E 0x11E 0x12E 0x13E SDT R/W 0x10F 0x11F 0x12F 0x13F STD_EN R/W DETSTUS* ATSTART STDNOW* PAL60EN PALCNEN ATREG PALMEN NTSC44EN 0x07 STANDARD SECAMEN PALBEN NTSCEN 0x7F 0x140 0x150 0x160 0x171 RESERVED R 0 0 0 0 0 0 0 0 0x00 0x141 0x151 0x161 0x172 RESERVED R 0 0 0 0 0 0 0 0 0x00 0x142 0x152 0x162 0x173 RESERVED R 0 0 0 0 0 0 0 0 0x00 0x143 0x153 0x163 0x174 RESERVED R 0 0 0 0 0 0 0 0 0x00 0x144 0x154 0x164 0x174 VSCALE_LO R/W 0x145 0x155 0x165 0x175 SCALE_HI R/W 0x146 0x156 0x166 0x176 HSCALE_LO R/W 0x147 0x157 0x167 0x177 F2CROP_HI R/W 0x148 0x158 0x168 0x178 F2VDELAY_LO R/W V2DELAY[7:0] 0x12 0x149 0x159 0x169 0x179 F2VACTIVE_LO R/W V2ACTIVE[7:0] 0xF0 0x14A 0x15A 0x16A 0x17A F2HDELAY_LO R/W H2DELAY[7:0] 0x0F H2ACTIVE[7:0] 0xD0 0x00 VSCALE[7:0] VSCALE[11:8] 0x11 HSACLE[11:8] 0x00 HSCALE[7:0] V2DELAY[9:8] V2ACTIVE[9:8] H2DELAY[9:8] 0x02 H2ACTIVE[9:8] 0x14B 0x15B 0x16B 0x17B F2HACTIVE_LO R/W 0x14C 0x15C 0x16C 0x17C F2VSCALE_LO R/W 0x14D 0x15D 0x16D 0x17D F2SCALE_HI R/W 0x14E 0x15E 0x16E 0x17E F2HSCALE_LO R/W 0x14F 0x15F 0x16F 0x17F F2CNT R/W 0x1A0 0x1A1 0x1A2 0x1A3 RESERVED R 0x1A4 0x1A5 0x1A6 0x1A7 IDCNTL R/W 0x180 SRST R/W 0 0 0 AUDIORST VDEC4RST VDEC3RST VDEC2RST VDEC1RST 0x00 0x181 ACNTL R/W 0 IREF VREF 0 CLKPDN 0 YFLEN YSV 0x02 21 0x00 V2SCALE[7:0] V2SCALE[11:8] 0x11 H2SACLE[11:8] 0x00 H2SCALE[7:0] 0 0 0 CVSTD 0 0 0 NT50 IDX 0 F2CNT 0x00 0x08 RESERVED 0x1A NSEN/SSEN/PSEN/WKTH TW6869 For Video Decoder and Audio Codec CH0~CH3. (*: Read only register/bit) B[31:8] are hardwired to 0 in all registers. Address CH1 CH2 CH3 Mnemonic R/W BIT7 BIT6 0x182 ACNTL2 R/W CTEST 0x183 CNTRL1 R/W PBW 0x184 CKHY R/W GMEN 0x185 SHCOR R/W 0x186 CORING R/W 0x187 CLMPG R/W CLPEND 0x188 IAGC R/W NMGAIN 0x189 VSCL R/W 0x18A PEAKWT R/W 0x18B CLMPL R/W CLMPLD CLMPL 0x18C SYNCT R/W SYNCTD SYNCT 0x18D MISSCNT R/W 0x18E PCLAMP R/W 0x18F VCNTL1 R/W 0x190 VCNTL2 R/W 0x191 CKILL R/W 0x192 COMB R/W COMBMD HTL 0x193 LDLY R/W CKLM YDLY 0x194 MISC1 R/W HPLC 0x195 LOOP R/W 0x196 MISC2 R/W 0x197 CLMD R/W 0x198~0x19F RESERVED R 0x1A8 HFLT21 R/W HFLT2 HFLT1 0x1A9 HFLT43 R/W HFLT4 HFLT3 0x1AA AGCEN R/W 0x1AB AGCGAIN1 R/W AGCGAIN1[7:0] 0xF0 0x1AC AGCGAIN2 R/W AGCGAIN2[7:0] 0xF0 0x1AD AGCGAIN3 R/W AGCGAIN3[7:0] 0xF0 0x1AE AGCGAIN4 R/W AGCGAIN4[7:0] 0x1AF VSHP21 R/W RESERVED CH4 BIT5 BIT4 BIT3 BIT2 YCLEN 0 AFLTEN GTEST VLPF DEM PALSW SET7 COMB HCOMP CKHY SHCOR 0 Default CKLY CKLC 0x10 YCOMB PDLY 0 0 VCOR CIF 0x50 WPGAIN VCCOMB 0 VVBILINE 0xD8 0xBC 0xB8 MISSCNT HSWIN 0x44 PCLAMP VLCKO 0x38 VMODE DETV BSHT CKILMAX SDET SKILL 0 AGCEN3 BP HPF_RES 0x30 TBCEN BYPASS SYOUT 0 0x14 SPM CBAL CBW FCS LCS CCS CLMD 0 0 AGCEN2 0x44 0 YNR 0 0x78 0 ACCT PKILL 0 AGCEN1 VSHP2 0 AGCGAIN4[8] 0xA5 BST PSP 0xE0 0x05 0 AGCGAIN3[8] 0 0x00 0x00 0x00 AGCGAIN2[8] AGCGAIN1[8] 0x00 0xF0 RESERVED VSHP1 0x1B0 VSHP43 R/W RESERVED RESERVED R 0 0x1B3 AADCOFS_H R/W 0x1B4 AADC1OFS_L R/W AADC1OFS[7:0] 0x00 0x1B5 AADC2OFS_L R/W AADC2OFS[7:0] 0x00 0x1B6 AADC3OFS_L R/W AADC3OFS[7:0] 0x00 0 AADC4OFS[9:8] 0 RESERVED 0x00 0x1B1~0x1B2 22 VSHP4 0x00 0x00 VTL PALC FRM AGCEN4 VINT CKILMIN HPM NKILL AFLD VSHT ENCNT 0x22 0x40 PEAKWT VLCKI 0x80 0x44 CLPST VYCOMB 0xCC 0x00 0 CCOR FC27 BIT0 HSDLY CTCOR 0 BIT1 0 0 AADC3OFS[9:8] VSHP3 0 AADC2OFS[9:8] 0 0x00 0 AADC1OFS[9:8] 0x00 0x00 TW6869 For Video Decoder and Audio Codec CH0~CH3. (*: Read only register/bit) B[31:8] are hardwired to 0 in all registers. Address CH1 CH2 CH3 Mnemonic R/W 0x1B7 AADC4OFS_L R/W 0x1B8 AUDADC_H* R 0x1B9 AUD1ADC_L* R AUD1ADC[7:0]* 0x00 0x1BA AUD2ADC_L* R AUD2ADC[7:0]* 0x00 0x1BB AUD3ADC_L* R AUD3ADC[7:0]* 0x00 0x1BC AUD4ADC_L* R AUD4ADC[7:0]* 0x1BD ADJAADC_H* R 0x1BE ADJAADC1_L* R ADJAADC1[7:0]* 0x00 0x1BF ADJAADC2_L* R ADJAADC2[7:0]* 0x00 0x1C0 ADJAADC3_L* R ADJAADC3[7:0]* 0x00 0x1C1 ADJAADC4_L* R ADJAADC4[7:0]* 0x1C2~0x1CD RESERVED R 0 0 0 0 0 0 0 0 0x00 0x1CE ANAPWDN R/W AAUTOMUTE RESERVED RESERVED A_ADC_PWDN V4_ADC_PWDN V3_ADC_PWDN V2_ADC_PWDN V1_ADC_PWDN 0x00 0x1CF RESERVED R 0 0 0 0 0 0 0 0 0x00 0x1D0 AIGAIN1 R/W 0 AIGAIN1 0x20 0x1D1 AIGAIN2 R/W 0 AIGAIN2 0x20 0x1D2 AIGAIN3 R/W 0 AIGAIN3 0x20 0x1D3 AIGAIN4 R/W 0 AIGAIN4 0x1D4~0x1DB RESERVED R/W 0 0x1DC MIX_MUTE R/W 0x1DD MIX_RATIO21 R/W MIX_RATIO2 MIX_RATIO1 0x1DE MIX_RATIO43 R/W MIX_RATIO4 MIX_RATIO3 0x1DF RESERVED R 0 0 0 0x1E0 MIX_OUTSEL R/W VADCCKPOL AADCCKPOL ADACCKPOL 0x1E1 ADET R/W AAMPMD 0x1E2 ADET_TH21 R/W 0x1E3 ADET_TH43 R/W 0x1E4 ADET_TH43 R/W 0 AOFFCORE DOUT_RST DIV_RST ACALEN 0x1E5~0x1FB RESERVED R 0 0 0 0 0 0x1FC AADC_TEST R/W 0 ASYNSERIAL AADC_PFTEST AINSWFIX 0x1FD VADC_TEST R/W 0 0 0 0 0 VADC_PFTEST 0x1FE DEV_ID_H* R 0 0 0 0 0 0 0x00 0x1FF DEV_ID_L* R 0 0 0 1 0x71 CH4 23 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 AADC4OFS[7:0] AUD4ADC[9:8]* 0x00 AUD3ADC[9:8]* ADJAADC4[9:8]* AUD2ADC[9:8]* 0 LAWMD AUD1ADC[9:8]* ADJAADC2[9:8]* 0 ADJAADC1[9:8]* 0 0x20 0 0 0 MIX_MUTE 0 0 ADET_TH4[4] 0 ADET_TH3[4] ADET_TH2[3:0] ADET_TH4[3:0] 0x00 0x00 0x00 0x00 0 0 ADET_TH2[4] ADET_TH1[4] MIX_OUTSEL ADET_FILT DEV_ID[3:0]*: 7h 0x00 0x00 MIX_DERATIO DEV_ID[5:4]*: 0h 0x00 0x00 ADJAADC3[9:8]* 0 Default 0x00 0x14 0xC0 ADET_TH1[3:0] 0xAA ADET_TH3[3:0] 0xAA ASAVE[2:0] 0 0 0xAA 0 AINSWNUM 0x00 0x00 VADC_PFSEL 0x00 TW6869 For PCI-E Endpoint Controller (*: Read only register/bit) Byte Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 Mnemonic R/ W EP_HEADER_ REG0* R EP_HEADER_ REG1 R/ W EP_HEADER_ REG2* R BIT7 BIT6 BIT5 BIT4 BIT3 DEVICE_ID* VENDOR_ID* STATUS_REG COMMAND_REG CLASS_CODE* REVISION_ID* BIST* HEADER_TYPE* LATENCY_TIMER* CACHE_LINE_SIZE EP_HEADER_ REG3 R/ W EP_HEADER_ REG4* R BASE_ADDRESS_REG0* EP_HEADER_ REG5* R BASE_ADDRESS_REG1* EP_HEADER_ REG6* R BASE_ADDRESS_REG2* EP_HEADER_ REG7* R BASE_ADDRESS_REG3* EP_HEADER_ REG8* R BASE_ADDRESS_REG4* EP_HEADER_RE R G9* BASE_ADDRESS_REG5* EP_HEADER_ REGA* R EP_HEADER_ REGB* R CARDBUS_CIS_POINTER* SUBSYSYEM_ID* SUBSYSYEM_VENDOR_ID* 24 BIT2 BIT1 BIT0 Default 0x68 0x64 0x17 0x97 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TW6869 For PCI-E Endpoint Controller (*: Read only register/bit) Byte Offset Address 0x30 0x34 0x38 0x3C 0x40 0x44 0x48~0x6C 0x70 0x74 0x78 0x7C 0x80 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 Mnemonic R/ W EP_HEADER_ REGC R/ W EP_HEADER_ REGD* R* BIT7 BIT6 BIT5 BIT4 BIT3 EXPANSION_ROM_BASE_ADDR RESERVED CAP_PTR* RESERVED R RESERVED EP_HEADER_ REGF* R RESERVED RESERVED INTERRUPT_PIN* INTERRUPT_LINE* EP_PM_CAP_ REG0* R EP_PM_CAP_ REG1 R/ W PMC* RESERVED NEXT_CAP_POINTER* CAP_ID* DATA* PMCSR_BSE_EXT* PMCSR RESERVED PCIE_CAP_REG* EP_PCIE_CAP_ REG0* R EP_PCIE_CAP_ REG1* R EP_PCIE_CAP_ R/ REG2 W EP_PCIE_CAP_ REG3* R EP_PCIE_CAP_ R/ REG4 W 25 NEXT_CAP_POINTER* CAP_ID* DEVICE_CAP* DEVICE_STATUS DEVICE_CONTROL LINK_CAP* LINK_STATUS* LINK_CONTROL BIT2 BIT1 BIT0 Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xFF 0xC9 0xC3 0x50 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x12 0x00 0x10 0x00 0x00 0x87 0x22 0x00 0x10 0x20 0x10 0x00 0x07 0x3C 0x11 0x10 0x11 0x00 0x00 TW6869 For PCI-E Endpoint Controller (*: Read only register/bit) Byte Offset Address 0x84~0x9C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 Mnemonic R/ W RESERVED R RESERVED EP_ERR_CAP_ REG0* R ENHANCE_CAP_HEADER* BIT7 BIT6 BIT5 BIT4 BIT3 EP_ERR_CAP_ R/ REG1 W UNCORRECTABLE_ERROR_STATUS EP_ERR_CAP_ R/ REG2 W UNCORRECTABLE_ERROR_MASK EP_ERR_CAP_ R/ REG3 W UNCORRECTABLE_ERROR_SEVERITY EP_ERR_CAP_ R/ REG4 W CORRECTABLE_ERROR_STATUS EP_ERR_CAP_ R/ REG5 W CORRECTABLE_ERROR_MASK EP_ERR_CAP_ R/ REG6 W ADVANCE_ERROR_CAP_CONTROL EP_ERR_CAP_ REG7 R HEADER_LOG_1ST_DW EP_ERR_CAP_ REG8 R HEADER_LOG_2ND_DW EP_ERR_CAP_ REG9 R HEADER_LOG_3RD_DW EP_ERR_CAP_ REGA R HEADER_LOG_4TH_DW 26 BIT2 BIT1 BIT0 Default 0x00 0x00 0x00 0x00 0x14 0x01 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x20 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0x00 0xA0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TW6869 REGISTER DESCRIPTION DMA Controller Index 0x00 INT_STATUS [4] [3] [7] [6] [5] B3 BAD_ FMT_7 BAD_ FMT_6 BAD_ FMT_5 BAD_ FMT_4 B2 0 0 0 B1 INTSTA_ DMA15 INTSTA_ DMA7 INTSTA_ DMA14 INTSTA_ DMA6 INTSTA_ DMA13 INTSTA_ DMA5 B0 Default [2] [1] [0] BAD_ FMT_3 BAD_ FMT_2 BAD_ FMT_1 BAD_ FMT_0 0x00 0 0 0 DMA_TOUT 0 0x00 INTSTA_ DMA12 INTSTA_ DMA4 INTSTA_ DMA11 INTSTA_ DMA3 INTSTA_ DMA10 INTSTA_ DMA2 INTSTA_ DMA9 INTSTA_ DMA1 INTSTA_ DMA8 INTSTA_ DMA0 BAD_FMT_7 B[31] BAD_FMT_6 BAD_FMT_5 BAD_FMT_4 BAD_FMT_3 BAD_FMT_2 BAD_FMT_1 BAD_FMT_0 B[30] B[29] B[28] B[27] B[26] B[25] B[24] Bad incoming data format flag of video input -7 0 = no error detected 1 = wrong format detected from the incoming data * This bit status is controlled by DMA_CONFIG[31:24] ** BAD_FMT = P_BAD | P_OV See register VIDEO_PARSER_STATUS Bad incoming data format flag of video input -6 Bad incoming data format flag of video input -5 Bad incoming data format flag of video input -4 Bad incoming data format flag of video input -3 Bad incoming data format flag of video input -2 Bad incoming data format flag of video input -1 Bad incoming data format flag of video input -0 DMA_TOUT B[17] Time out flag of DMA channels INTSTA_DMA[15:0] B[15:0] Interrupt request from DMA Channel-15 to Channel 0 0 = no interrupt 1 = interrupt 27 0x00 0x00 TW6869 Index B3 0x01 [7] [6] [5] FFLAG_ DMA7 FFLAG_ DMA6 FFLAG_ DMA5 FFLAG_ DMA4 FFLAG_ DMA3 Default [2] [1] [0] FFLAG_ DMA2 FFLAG_ DMA1 FFLAG_ DMA0 0x00 0x00 B2 0 0 0 0 0 0 0 0 B1 PBFLAG_ DMA15 PBFLAG_ DMA7 PBFLAG_ DMA14 PBFLAG_ DMA6 PBFLAG_ DMA13 PBFLAG_ DMA5 PBFLAG_ DMA12 PBFLAG_ DMA4 PBFLAG_ DMA11 PBFLAG_ DMA3 PBFLAG_ DMA10 PBFLAG_ DMA2 PBFLAG_ DMA9 PBFLAG_ DMA1 PBFLAG_ DMA8 PBFLAG_ DMA0 B0 FFLAG_DMA7 B[31] FFLAG_DMA6 FFLAG_DMA5 FFLAG_DMA4 FFLAG_DMA3 FFLAG_DMA2 FFLAG_DMA1 FFLAG_DMA0 B[30] B[29] B[28] B[27] B[26] B[25] B[24] PBFLAG_DMA15 B[15] PBFLAG_DMA14 PBFLAG_DMA13 PBFLAG_DMA12 PBFLAG_DMA11 PBFLAG_DMA10 PBFLAG_DMA9 PBFLAG_DMA8 PBFLAG_DMA7 PBFLAG_DMA6 PBFLAG_DMA5 PBFLAG_DMA4 PBFLAG_DMA3 PBFLAG_DMA2 PBFLAG_DMA1 PBFLAG_DMA0 B[14] B[13] B[12] B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] 28 PB_STATUS [4] [3] Field flag of DMA Channel-7 0 = Field 1 1 = Field 2 * It is valid only under block DMA mode. See PHASE_REF Field flag of DMA Channel-6 Field flag of DMA Channel-5 Field flag of DMA Channel-4 Field flag of DMA Channel-3 Field flag of DMA Channel-2 Field flag of DMA Channel-1 Field flag of DMA Channel-0 PB flag of DMA Channel-15 0=P 1=B PB flag of DMA Channel-14 PB flag of DMA Channel-13 PB flag of DMA Channel-12 PB flag of DMA Channel-11 PB flag of DMA Channel-10 PB flag of DMA Channel-9 PB flag of DMA Channel-8 PB flag of DMA Channel-7 PB flag of DMA Channel-6 PB flag of DMA Channel-5 PB flag of DMA Channel-4 PB flag of DMA Channel-3 PB flag of DMA Channel-2 PB flag of DMA Channel-1 PB flag of DMA Channel-0 0xFF 0xFF TW6869 Index B3 0x02 [6] [5] DMA_ ENABLE BOND_ OPT_1 BOND_ OPT_0 DMA_CMD [4] [3] 0 0 Default [2] [1] [0] 0 0 0 0x00 0x00 B2 0 0 0 0 0 0 0 0 B1 RESET_ DMA15 RESET_ DMA7 RESET_ DMA14 RESET_ DMA6 RESET_ DMA13 RESET_ DMA5 RESET_ DMA12 RESET_ DMA4 RESET_ DMA11 RESET_ DMA3 RESET_ DMA10 RESET_ DMA2 RESET_ DMA9 RESET_ DMA1 RESET_ DMA8 RESET_ DMA0 B0 DMA_ENABLE BOND_OPT RESET_DMA16 RESET_DMA15 RESET_DMA14 RESET_DMA13 RESET_DMA12 RESET_DMA11 RESET_DMA10 RESET_DMA9 RESET_DMA8 RESET_DMA7 RESET_DMA6 RESET_DMA5 RESET_DMA4 RESET_DMA3 RESET_DMA2 RESET_DMA1 RESET_DMA0 29 [7] B[31] General DMA enable bit 0 = stop 1 = start B[30:29] Bonding status (READ ONLY) B[16] Reset for DMA Channel-16 0 = reset 1 = normal B[15] Reset for DMA Channel-15 B[14] Reset for DMA Channel-14 B[13] Reset for DMA Channel-13 B[12] Reset for DMA Channel-12 B[11] Reset for DMA Channel-11 B[10] Reset for DMA Channel-10 B[9] Reset for DMA Channel-9 B[8] Reset for DMA Channel-8 B[7] Reset for DMA Channel-7 B[6] Reset for DMA Channel-6 B[5] Reset for DMA Channel-5 B[4] Reset for DMA Channel-4 B[3] Reset for DMA Channel-3 B[2] Reset for DMA Channel-2 B[1] Reset for DMA Channel-1 B[0] Reset for DMA Channel-0 0xFF 0xFF TW6869 Index 0x03 [7] [6] [5] FIFO_STATUS [4] [3] [0] OV7 OV6 OV5 OV4 OV3 OV2 OV1 OV0 0x00 B2 BAD_ PTR_7 BAD_ PTR_6 BAD_ PTR_5 BAD_ PTR_4 BAD_ PTR_3 BAD_ PTR_2 BAD_ PTR_1 BAD_ PTR_0 0x00 B1 B0 0 0 0 0 0 0 0 0 0x00 VDLOSS7 VDLOSS6 VDLOSS5 VDLOSS4 VDLOSS3 VDLOSS2 VDLOSS1 VDLOSS0 0x00 B[31] BAD_FMT_6 BAD_FMT_5 BAD_FMT_4 BAD_FMT_3 BAD_FMT_2 BAD_FMT_1 BAD_FMT_0 B[30] B[29] B[28] B[27] B[26] B[25] B[24] BAD_PTR_7 B[23] BAD_PTR_6 BAD_PTR_5 BAD_PTR_4 BAD_PTR_3 BAD_PTR_2 BAD_PTR_1 BAD_PTR_0 B[22] B[21] B[20] B[19] B[18] B[17] B[16] VDLOSS_7 B[7] Video signal lost for Channel-7 0 = no error 1 = has error B[6] Video signal lost for Channel-6 B[5] Video signal lost for Channel-5 B[4] Video signal lost for Channel-4 B[3] Video signal lost for Channel-3 B[2] Video signal lost for Channel-2 B[1] Video signal lost for Channel-1 B[0] Video signal lost for Channel-0 VDLOSS _6 VDLOSS _5 VDLOSS _4 VDLOSS _3 VDLOSS _2 VDLOSS _1 VDLOSS _0 Index 30 [1] B3 BAD_FMT_7 0x04 Default [2] B3 B2 B1 B0 DMA FIFO overflow flag of DMA channel-7 0 = no overflow 1 = overflow DMA FIFO overflow flag of DMA Channel-6 DMA FIFO overflow flag of DMA Channel -5 DMA FIFO overflow flag of DMA Channel -4 DMA FIFO overflow flag of DMA Channel -3 DMA FIFO overflow flag of DMA Channel -2 DMA FIFO overflow flag of DMA Channel -1 DMA FIFO overflow flag of DMA Channel -0 DMA FIFO pointer error in DMA Channel-7 0 = no error 1 = has error DMA FIFO pointer error in DMA Channel-6 DMA FIFO pointer error in DMA Channel-5 DMA FIFO pointer error in DMA Channel-4 DMA FIFO pointer error in DMA Channel-3 DMA FIFO pointer error in DMA Channel-2 DMA FIFO pointer error in DMA Channel-1 DMA FIFO pointer error in DMA Channel-0 [7] [6] [5] 0 0 0 VIDEO_CHANNEL_ID [4] [3] 0 7 [2] [1] 0 0 6 4 2 0 Default 0 5 3 1 [0] 0x00 0x92 0x46 0 0x88 TW6869 Index 0x05 B3 B2 B1 B0 VIDEO_PARSER_STATUS [4] [3] [7] [6] [5] 0 0 0 0 0 0 0 0 P_OV7 P_OV7 P_OV7 P_BAD7 P_BAD6 P_BAD5 Default [2] [1] [0] 0 0 0 0 0x00 0 0 0 0 0x00 P_OV7 P_OV7 P_OV7 P_OV7 P_OV7 0x00 P_BAD4 P_BAD3 P_BAD2 P_BAD1 P_BAD0 0x00 P_OV7 P_OV6 P_OV5 P_OV4 P_OV3 P_OV2 P_OV1 P_OV0 B[15] B[14] B[13] B[12] B[11] B[10] B[9] B[8] Parser FIFO overflow flag for video input-7 Parser FIFO overflow flag for video input-6 Parser FIFO overflow flag for video input-5 Parser FIFO overflow flag for video input-4 Parser FIFO overflow flag for video input-3 Parser FIFO overflow flag for video input-2 Parser FIFO overflow flag for video input-1 Parser FIFO overflow flag for video input-0 * These status bits are kept asserted until been read P_BAD7 P_BAD 6 P_BAD 5 P_BAD 4 P_BAD 3 P_BAD 2 P_BAD 1 P_BAD 0 B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] Parser found bad format at incoming video input-7 Parser found bad format at incoming video input-6 Parser found bad format at incoming video input-5 Parser found bad format at incoming video input-4 Parser found bad format at incoming video input-3 Parser found bad format at incoming video input-2 Parser found bad format at incoming video input-1 Parser found bad format at incoming video input-0 * The status bits are kept asserted until been read 31 TW6869 Index 0x06 [6] [5] 0 0 0 0 0 0 0 0 0 0 0 0 B3 B2 B1 B0 RESET_AV_REG RESET_DMA_CTRL RESET_DEC_INTF RESET_EXT_PHY 32 SYS_SOFT_RST [4] [3] [7] 0 0 B[3] B[2] B[1] B[0] 0 0 Default [2] [1] [0] 0 0 0 0 0x00 0 0 0 0 0x00 0 0 0 0 0x00 RESET_AV_REG RESET_ DMA_CTRL RESET_ DEC_INTF RESET_ EXT_PHY 0x07 Reset for registers of internal AV decoder. Reset for DMA controller. Reset for decode interface. Reset for external PHY. It is a software reset, active low and self clear. TW6869 Index 0x08 B3 B2 B1 B0 0x09 B3 B2 B1 B0 0xD0 B3 B2 B1 B0 0xD1 B3 B2 B1 B0 0xD2 B3 B2 B1 B0 0xD3 B3 B2 B1 B0 0xD4 B3 B2 B1 B0 0xD5 B3 B2 B1 B0 0xD6 B3 B2 B1 B0 [6] [5] DMA_PAGE_TABLE_ADDR [4] [3] Default [2] [1] [0] 0x00 PAGE_TABLE0_ADDR (Channel 0) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 0) 0x00 0x00 0x00 0x00 PAGE_TABLE0_ADDR (Channel 1) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 1) 0x00 0x00 0x00 0x00 PAGE_TABLE0_ADDR (Channel 2) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 2) 0x00 0x00 0x00 0x00 PAGE_TABLE0_ADDR (Channel 3) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 3) 0x00 0x00 0x00 0x00 PAGE_TABLE0_ADDR (Channel 4) 0x00 0x00 0x00 0xD7 B3 B2 B1 B0 0xD8 B3 B2 B1 B0 PAGE_TABLE0_ADDR (Channel 5) B3 PAGE_TABLE1_ADDR (Channel 5) 0xD9 33 [7] 0x00 PAGE_TABLE1_ADDR (Channel 4) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TW6869 Index 0xDA [7] [5] DMA_PAGE_TABLE_ADDR [4] [3] Default [2] [1] [0] B2 B1 B0 0x00 B3 B2 B1 B0 0x00 0xDB B3 B2 B1 B0 0xDC B3 B2 B1 B0 0xDD [6] B3 B2 B1 B0 PAGE_TABLE0_ADDR B[31:0] PAGE_TABLE1_ADDR B[31:0] 0x00 0x00 PAGE_TABLE0_ADDR (Channel 6) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 6) 0x00 0x00 0x00 0x00 PAGE_TABLE0_ADDR (Channel 7) 0x00 0x00 0x00 0x00 PAGE_TABLE1_ADDR (Channel 7) 0x00 0x00 0x00 The address of page0 table The address of page1 table Driver needs to allocate 2 pages of Non-Pageable memory, and saves allocated addresses to these 2 registers for each video DMA channel Each page is 4096-bytes continuously buffer. Every 8-bytes (2 DWord) is called one Descriptor. Each page has 4096/8=512 video descriptors. The following is the video descriptor‟s data structure (little endian format) B[63:32] = target address of DMA B[31:30] = descriptor status 0 = Host buffer unavailable 1 = Host buffer available 2 = This buffer has been filled by DMA successfully 3 = This buffer has been filled by DMA with error B[29] = new frame flag B[28:21] = do not care B[20:14] = do not care B[13] = do not care B[12:0] = total byte length requirement 34 TW6869 Index B3 0x0A [6] [5] 0 0 0 DMA_CHANNEL_ENABLE [4] [3] 0 0 Default [2] [1] 0 0 B2 0 0 0 0 0 0 0 B1 ENA_ DMA15 ENA_ DMA7 ENA_ DMA14 ENA_ DMA6 ENA_ DMA13 ENA_ DMA5 ENA_ DMA12 ENA_ DMA4 ENA_ DMA11 ENA_ DMA3 ENA_ DMA10 ENA_ DMA2 ENA_ DMA9 ENA_ DMA1 B0 ENA_DMA16 ENA_DMA15 ENA_DMA14 ENA_DMA13 ENA_DMA12 ENA_DMA11 ENA_DMA10 ENA_DMA9 ENA_DMA8 ENA_DMA7 ENA_DMA6 ENA_DMA5 ENA_DMA4 ENA_DMA3 ENA_DMA2 ENA_DMA1 ENA_DMA0 35 [7] B[16] B[15] B[14] B[13] B[12] B[11] B[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] Enable DMA Channel-16 Enable DMA Channel-15 Enable DMA Channel-14 Enable DMA Channel-13 Enable DMA Channel-12 Enable DMA Channel-11 Enable DMA Channel-10 Enable DMA Channel-9 Enable DMA Channel-8 Enable DMA Channel-7 Enable DMA Channel-6 Enable DMA Channel-5 Enable DMA Channel-4 Enable DMA Channel-3 Enable DMA Channel-2 Enable DMA Channel-1 Enable DMA Channel-0 [0] 0 ENA_ DMA16 ENA_ DMA8 ENA_ DMA0 0x00 0x00 0x00 0x00 TW6869 Index [6] [5] B1 MASK_ BAD_FMT7 MASK_ BAD_PTR7 MASK_ OV_7 MASK_ BAD_FMT6 MASK_ BAD_PTR6 MASK_ OV_6 MASK_ BAD_FMT5 MASK_ BAD_PTR5 MASK_ OV_5 MASK_ BAD_FMT4 MASK_ BAD_PTR4 MASK_ OV_4 B0 0 0 0 0 B3 0B DMA_CONFIG [4] [3] [7] B2 MASK_ BAD_FMT3 MASK_ BAD_PTR3 MASK_ OV_3 ENA_CPL_ WAIT Default [2] [1] [0] MASK_ BAD_FMT2 MASK_ BAD_PTR2 MASK_ OV_2 MASK_ BAD_FMT1 MASK_ BAD_PTR1 MASK_ OV_1 MASK_ BAD_FMT0 MASK_ BAD_PTR0 MASK_ OV_0 ENA_INTX 0 BIG_ENDIAN MASK_BAD_FMT B[31:24] Mask bad format error of incoming data of DMA Channel 0 = mask off, no report 1 = ON MASK_BAD_PTR B[23:16] Enable DMA FIFO pointer check of DMA Channel 0 = mask off, no report 1 = ON MASK_OVF B[15:8] Enable DMA FIFO overflow check of DMA Channel 0 = mask off, no report 1 = ON ENA_CPL_WAIT B[3] ENA_INTX BIG_ENDIAN B[2] B[0] Wait for CPL done during initialization stage 0 = disable 1 = enable INTx enable, should be set to 1 by driver Big endian enable 0 = little endian 1 = big endian 36 0x00 0x00 0x00 0x04 TW6869 Index 0x0C B3 B2 B1 B0 DMA_INT_TIMER 37 [7] [6] [5] 0 0 0 0 0 DMA_TIMER_INTERVAL [4] [3] 0 0 Default [2] [1] [0] 0 0 0 DMA_INT_TIMER[21:16] DMA_INT_TIMER[15:0] B[21:0] Minimum time span for DMA interrupting host. 0x00 0x09 0x89 0x68 TW6869 Index 0x0D B3 B2 B1 B0 [7] [6] 0 0 DMA_CHANNEL_TIMEOUT [4] [3] Default [2] [1] PRE_TIMEOUT_OFST DMA_DAT_CH_TIMEOUT[11:4] DMA_DAT_CH_TIMEOUT[3:0] B[29:24] B[23:12] DMA_VDO_CH_TIMEOUT B[11:0] [0] 0x14 0x0C DMA_VDO_CH_TIMEOUT[11:8] DMA_VDO_CH_TIMEOUT[7:0] PRE_TIMEOUT_OFST DMA_DAT_CH_TIMEOUT 38 [5] Offset from pre timeout to final timeout Service timeout of each DMA data channel Note: It should be set a big value to avoid time out. Service timeout of each DMA video channel 0x85 0x84 TW6869 Index [7] B3 0x10 B2 B2 B2 B2 0x14 B2 0x15 B2 B2 0x17 39 B2 B1 B0 ENA_ MASTER0 VIDEO_OUT_FORMAT0 Default [2] [1] MASTER_CHID0 [0] ENA_ VDECI0 END_IDX_DMA0[9:6] FIELD_OUT1 ENA_FIELD_DR OP1 ENA_ MASTER1 VIDEO_OUT_FORMAT1 MASTER_CHID1 VIN_MUX_SEL2 ENA_ HDECI2 FIELD_OUT2 VIDEO_OUT_FORMAT2 MASTER_CHID2 VIN_MUX_SEL3 ENA_ HDECI3 FIELD_OUT3 ENA_ MASTER3 VIDEO_OUT_FORMAT3 MASTER_CHID3 VIN_MUX_SEL4 ENA_ HDECI4 FIELD_OUT4 ENA_ MASTER4 VIDEO_OUT_FORMAT4 MASTER_CHID4 VIN_MUX_SEL5 ENA_ HDECI5 FIELD_OUT5 ENA_ MASTER5 VIDEO_OUT_FORMAT5 MASTER_CHID5 VIN_MUX_SEL6 ENA_ HDECI6 FIELD_OUT6 ENA_ MASTER6 VIDEO_OUT_FORMAT6 MASTER_CHID6 VIN_MUX_SEL7 ENA_ HDECI7 FIELD_OUT7 ENA_ MASTER7 VIDEO_OUT_FORMAT7 START_IDX_DMA7[7:0] 0x00 0x00 MASTER_CHID7 ENA_ VDECI7 END_IDX_DMA7[9:6] END_IDX_DMA7[5:0] 0x00 0x00 START_IDX_DMA6[9:8] START_IDX_DMA6[7:0] ENA_FIELD_DR OP7 0x00 0x00 ENA_ VDECI6 END_IDX_DMA6[9:6] END_IDX_DMA6[5:0] 0x00 0x00 START_IDX_DMA5[9:8] START_IDX_DMA5[7:0] ENA_FIELD_DR OP6 0x00 0x00 ENA_ VDECI5 END_IDX_DMA5[9:6] END_IDX_DMA5[5:0] 0x00 0x00 START_IDX_DMA4[9:8] START_IDX_DMA4[7:0] ENA_FIELD_DR OP5 0x00 0x00 ENA_ VDECI4 END_IDX_DMA4[9:6] END_IDX_DMA4[5:0] 0x00 0x00 START_IDX_DMA3[9:8] START_IDX_DMA3[7:0] ENA_FIELD_DR OP4 0x00 0x00 ENA_ VDECI3 END_IDX_DMA3[9:6] END_IDX_DMA3[5:0] 0x00 0x00 START_IDX_DMA2[9:8] START_IDX_DMA2[7:0] ENA_FIELD_DR OP3 0x00 0x00 ENA_ VDECI2 END_IDX_DMA2[9:6] END_IDX_DMA2[5:0] 0x00 0x00 START_IDX_DMA1[9:8] ENA_ MASTER2 0x00 0x00 ENA_ VDECI1 END_IDX_DMA1[9:6] ENA_FIELD_DR OP2 0x00 0x00 START_IDX_DMA0[9:8] START_IDX_DMA1[7:0] B1 B0 B3 ENA_FIELD_DR OP0 END_IDX_DMA1[5:0] B1 B0 B3 0x16 VIN_MUX_SEL1 ENA_ HDECI1 B1 B0 B3 FIELD_OUT0 DMA_CHANNEL_CONFIG [4] [3] START_IDX_DMA0[7:0] B1 B0 B3 [5] END_IDX_DMA0[5:0] B1 B0 B3 0x13 ENA_ HDECI0 B1 B0 B3 0x12 VIN_MUX_SEL0 B1 B0 B3 0x11 [6] START_IDX_DMA7[9:8] 0x00 0x00 0x00 0x00 TW6869 VIN_MUX_SEL B[31:30] Analog Mux input selection for build-in video decoder 1~4 respectively 0 = Select input 0 1 = Select input 1 2 = Select input 2 3 = Select input 3 B[29] Which field dropped (applicable for master only) 0 = Field1 dropped 1 = Field2 dropped B[28] Drop off field 0 = no drop 1 = drop B[27] Master or slave 0 = slave 1 = master B[26:25] Master channel # of the current one. For master channel, it is itself B[24] Vertical (line) decimation 0 = No decimation 1 = 2:1 Decimation B[23] Horizontal (pixel) decimation 0 = No decimation 1 = 2:1 Decimation B[22:20] Set output video format 000b = UYVY / Y422 001b = Y420 010b = IYU1 / Y411 011b = Y41P 100b = RGB 555 101b = RGB 565 110b = YUYV / YUY2 111b = Reserved FIELD_OUT ENA_FIELD_DROP ENA_MASTER MASTER_CHID ENA_VDECI ENA_HDECI VIDEO_OUT _FORMAT UYVY / Y422 Byte Ordering (lowest byte) Cb 0 Byte Ordering (lowest byte) Cb 0 Y0 Y0' Y1' Y0 Y1 Cb 2 Cr0 Y1 Cb 2 Y2 Cr2 Y3 Y2' Y3' Y4' Y5' Y6' Y7' Cr0 Y2 Cr2 Y3 Cb 4 Y4 Cr4 Y5 Cb 6 Y6 Cr6 Y7 Cb 4 Y4 Cr4 Y5 Cb 6 Y6 Cr6 Y7 Y420 Active Line (2n+1) IYU1 / Y411 Byte Ordering (lowest byte) Cb 0 Y0 Y1 Cr0 Y2 Y3 Cb 4 Y4 Y5 Cr4 Y6 Y7 Y5 Y6 Y7 Cb 4 Y5 Cr4 Y41P Byte Ordering (lowest byte) Cb 0 Y0 Cr0 Y1 Cb 4 Y2 Cr4 Y2 Cb 2 Y3 Y3 Y4 RGB 555 Bit: 0 Byte Ordering (lowest byte) 45 B 9 10 G 14 15 R 0 RGB 565 Bit: 0 45 Byte Ordering (lowest byte) B Byte Ordering (lowest byte) Y0 10 11 G 15 R YUYV / YUY2 40 Cb 0 Y1 Cr0 Cr2 Active Line 2n Y4 Y6 Cb 6 Y7 Cr6 TW6869 END_IDX_DMA START_IDX_DMA B[19:10] end_idx of DMA B[ 9: 0] start_idx of DMA NOTE: B[29:25] are used for field dropping purpose. (1) DMA0-3 and DMA4-7 are 2 big groups. (2) Master means this DMA channel has higher priority to drop preferred field (odd/even), and slave means this channel is affected by master. Whenever master channel is sending data, it must drop the received. Index [6] [5] Default [2] [1] [0] 0x18 DMA8_P_ADDR 0x0000_ 0000 0x19 DMA8_B_ADDR 0x0000_ 0000 0x1A DMA9_P_ADDR 0x0000_ 0000 0x1B DMA9_B_ADDR 0x0000_ 0000 0x1C DMAA_P_ADDR 0x0000_ 0000 0x1D DMAA_B_ADDR 0x0000_ 0000 0x1E DMAB_P_ADDR 0x0000_ 0000 0x1F DMAB_B_ADDR 0x0000_ 0000 0x20 DMAC_P_ADDR 0x0000_ 0000 0x21 DMAC_B_ADDR 0x0000_ 0000 0x22 DMAD_P_ADDR 0x0000_ 0000 0x23 DMAD_B_ADDR 0x0000_ 0000 0x24 DMAE_P_ADDR 0x0000_ 0000 0x25 DMAE_B_ADDR 0x0000_ 0000 0x26 DMAF_P_ADDR 0x0000_ 0000 0x27 DMAF_B_ADDR 0x0000_ 0000 0x28 DMA10_P_ADDR 0x0000_ 0000 0x29 DMA10_B_ADDR 0x0000_ 0000 DMA_P/B_ADDR 41 [7] DMA_PB_CONFIG [4] [3] [31:0] Starting addresses for DMA Channel-8 ~ Channel-16. Each Channel has 2 starting addresses for P-buffer and B-buffer respectively. These buffer addresses are allocated by Driver during initialization. They are called as Common Buffer. Driver needs to copy data from these buffers to their destination TW6869 Index [7] [6] [5] 0 0 0 B3 0x2A B2 B1 B0 VIDEO_CONTROL1 [4] [3] 0 0 Default [2] [1] [0] 0 0 0 SYS_MODE_DM SYS_MODE_DM SYS_MODE_DM SYS_MODE_DM SYS_MODE_DM 0 0 0 A7 A6 A5 A4 A3 SYS_MODE_DM SYS_MODE_DM SYS_MODE_DM VSCL_ 0 0 0 0 A2 A1 A0 ENA_1 HSCL_ VSCL_ 0 0 0 0 0 0 ENA_0 ENA_0 SYS_MODE_DMA7 B[20] SYS_MODE_DMA6 SYS_MODE_DMA5 SYS_MODE_DMA4 SYS_MODE_DMA3 SYS_MODE_DMA2 SYS_MODE_DMA1 SYS_MODE_DMA0 B[19] B[18] B[17] B[16] B[15] B[14] B[13] System mode for DMA Channel-7 0 = 525 Lines 1 = 625 Lines System mode for DMA Channel-6 System mode for DMA Channel-5 System mode for DMA Channel-4 System mode for DMA Channel-3 System mode for DMA Channel-2 System mode for DMA Channel-1 System mode for DMA Channel-0 B[10] set the input format of DMA Channel-4~Channel-7. VSCL_ENA_1 B[10] Vertical scaler 0 = Disabled 1 = Enabled (360x240) B[7:6] set the input format of DMA Channel-0~Channel-3. HSCL_ENA_0 B[7] Horizontal scaler 0 = Disabled (full D1) 1 = Enabled – 360x480(B[6]=0) or 360x240(B[6]=1) VSCL_ENA_0 B[6] Vertical scaler 0 = Disabled 1 = Enabled (360x240) -- B[7] must be “1” 42 0x00 0x00 0x00 0x01 TW6869 Index 0x2B B3 B2 [6] [5] 0 0 0 0 RST_GEN7 RST_GEN6 RST_GEN5 PAT_SEL_ GEN7 EXT_VDAT _ENA7 PAT_SEL_ GEN6 EXT_VDAT _ENA6 PAT_SEL_ GEN5 EXT_VDAT _ENA5 B1 B0 RST_GEN7 B[23] RST_GEN6 RST_GEN5 RST_GEN4 RST_GEN3 RST_GEN2 RST_GEN1 RST_GEN0 B[22] B[21] B[20] B[19] B[18] B[17] B[16] PAT_SEL_GEN7 B[15] PAT_SEL_GEN6 PAT_SEL_GEN5 PAT_SEL_GEN4 PAT_SEL_GEN3 PAT_SEL_GEN2 PAT_SEL_GEN1 PAT_SEL_GEN0 B[14] B[13] B[12] B[11] B[10] B[9] B[8] EXT_VDAT_ENA7 B[7] EXT_VDAT_ENA6 EXT_VDAT_ENA5 EXT_VDAT_ENA4 EXT_VDAT_ENA3 EXT_VDAT_ENA2 EXT_VDAT_ENA1 EXT_VDAT_ENA0 B[6] B[5] B[4] B[3] B[2] B[1] B[0] 43 VIDEO_CONTROL2 [4] [3] [7] Default [2] [1] [0] 0 0 0 0 RST_GEN4 RST_GEN3 RST_GEN2 RST_GEN1 RST_GEN0 PAT_SEL_ GEN4 EXT_VDAT _ENA4 PAT_SEL_ GEN3 EXT_VDAT _ENA3 PAT_SEL_ GEN2 EXT_VDAT _ENA2 PAT_SEL_ GEN1 EXT_VDAT _ENA1 PAT_SEL_ GEN0 EXT_VDAT _ENA0 Reset control for YUV Generator-7 0 = reset 1 = not reset Reset control for YUV Generator-6 Reset control for YUV Generator-5 Reset control for YUV Generator-4 Reset control for YUV Generator-3 Reset control for YUV Generator-2 Reset control for YUV Generator-1 Reset control for YUV Generator-0 Pattern selector for YUV Generator-7 0 = Color Bar 1 = Sequenced Data Pattern selector for YUV Generator-6 Pattern selector for YUV Generator-5 Pattern selector for YUV Generator-4 Pattern selector for YUV Generator-3 Pattern selector for YUV Generator-2 Pattern selector for YUV Generator-1 Pattern selector for YUV Generator-0 selection for each video DMA Channel-7 0 = Use build in YUV Generator 1 = Use external inputs selection for each video DMA Channel-6 selection for each video DMA Channel-5 selection for each video DMA Channel-4 selection for each video DMA Channel-3 selection for each video DMA Channel-2 selection for each video DMA Channel-1 selection for each video DMA Channel-0 0x00 0xFF 0x00 0xFF TW6869 Index 0x2C [7] [6] B3 B2 B1 B0 [5] AUDIO_CONTROL1 [4] [3] Default [2] [1] BYTE_LENGTH_DMA8TO16[12:5] BYTE_LENGTH_DMA8TO16[4:0] 0x80 INT_GEN_ADAT_RATE[13:11] INT_GEN_ADAT_RATE[10:3] INT_GEN_ADAT_RATE[2:0] PAT_SEL_ ADO 0x07 0xA1 MIX_MODE BYTE_LENGTH _DMA8TO16 B[31:19] Total byte length requirement of Audio DMA Channel-8 ~ Channel-16 (default: 4096 bytes) INT_GEN_ADAT _RATE B[18:5] Internal audio generator sampling rate For example, if sampling rate is 8k, the value should be 125M/8K = 15625 = 0x3d09 (default) PAT_SEL_ADO B[4] MIX_MODE B[3:1] EXT_ADAT_ENA B[0] Pattern selector for internal audio signal generator 0 = Sine wave 1 = Sequenced Data Mix mode of internal mixed audio generator 111b = output audio channel-7 data …. 000b = output audio channel-0 data 0 = Use build-in sine waveform generator for Ch8-ChB 1 = Use external inputs 44 [0] EXT_ADAT_ ENA 0x21 TW6869 Index 0x2D B3 B2 B1 B0 AUDIO_CLK_REF [7] [6] 0 0 [5] AUDIO_CONTROL2 [4] [3] AUDIO_CLK_REF[29:24] [1] [0] 0x3D 0x09 AUDIO_CLK_REF[23:0] 0x00 0x00 B[29:0] Audio sampling frequency reference A_ref = (2^24) * 125MHz / (256*Fs) --------------------------------------------------------Sampling Rate Value (kHz) (HEX) --------------------------------------------------------8 0x3D09_0000 16 0x1E84_8000 32 0x0F42_4000 44.1 0x0B12_7795 48 0x0A2C_2AAA --------------------------------------------------------- 45 Default [2] TW6869 Index 0x2E [7] B3 B2 B1 B0 DMA_MODE7 [6] DMA_MODE7 PHASE_REF [4] [3] DMA_MODE6 DMA_MODE3 0 [5] DMA_MODE2 0 Default [2] [0] DMA_MODE5 DMA_MODE4 0x00 DMA_MODE1 DMA_MODE0 0x00 PHASE_REF[13:8] PHASE_REF[7:0] DMA_MODE6 DMA_MODE5 DMA_MODE4 DMA_MODE3 DMA_MODE2 DMA_MODE1 DMA_MODE0 B[31:30] DMA mode configuration of DMA Channel-7 00b = S & G mode 01b = Reserved 10b = Frame mode 11b = Field mode B[29:28] DMA mode configuration of DMA Channel-6 B[27:26] DMA mode configuration of DMA Channel-5 B[25:24] DMA mode configuration of DMA Channel-4 B[23:22] DMA mode configuration of DMA Channel-3 B[21:20] DMA mode configuration of DMA Channel-2 B[19:18] DMA mode configuration of DMA Channel-1 B[17:16] DMA mode configuration of DMA Channel-0 PHASE_REF B[13:0] 46 [1] Phase reference for rate conversion at each Video DMA channel. Valid range is [4800:5400]. 0x14 0x4D TW6869 Index 0x2F 0xE0 0xE1 GPP_Cn …… GPP_Dn 47 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 [7] [6] [5] GPP_C15 GPP_C14 GPP_C13 GPIO_REG [4] [3] GPP_C12 GPP_C11 Default [2] [1] [0] GPP_C10 GPP_C9 GPP_C8 0xFF GPP_C7 GPP_C6 GPP_C5 GPP_C4 GPP_C3 GPP_C2 SDA_C1 GPP_C0 0xFF GPP_D15 GPP_D14 GPP_D13 GPP_D12 GPP_D11 GPP_D10 GPP_D9 GPP_D8 0x00 GPP_D7 GPP_D6 GPP_D5 GPP_D4 GPP_D3 GPP_D2 DPP_D1 GPP_D0 0x00 GPP_C31 GPP_C30 GPP_C29 GPP_DC8 GPP_C27 GPP_C26 GPP_C25 GPP_C24 0xFF GPP_C23 GPP_C22 GPP_C21 GPP_DC0 GPP_C19 GPP_C18 DPP_C17 GPP_C16 0xFF GPP_D31 GPP_D30 GPP_D29 GPP_D28 GPP_D27 GPP_D26 GPP_D25 GPP_D24 0x00 GPP_D23 GPP_D22 GPP_D21 GPP_D20 GPP_D19 GPP_D18 DPP_D17 GPP_D16 0x00 GPP_C47 GPP_C46 GPP_C45 GPP_C44 GPP_C43 GPP_C42 GPP_C41 GPP_C40 0xFF GPP_C39 GPP_C38 GPP_C37 GPP_C36 GPP_C35 GPP_C34 DPP_C33 GPP_C32 0xFF GPP_D47 GPP_D46 GPP_D45 GPP_D44 GPP_D43 GPP_D42 GPP_D41 GPP_D40 0x00 GPP_D39 GPP_D38 GPP_D37 GPP_D36 GPP_D35 GPP_D34 DPP_D33 GPP_D32 0x00 I/O control of GPIO pin 0 = Pin is output 1 = Pin is input GPIO pin TW6869 Index INTL_HBAR_CTRL [4] [3] Default [7] [6] [5] B3 B2 B1 B0 0 0 0 0 0 0 0 0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0x00 0 0 0 0 0 0 0 0 0x00 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x34 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 0x35 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0x00 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 0x31 0x32 0x33 0x36 0x37 HEIGHT_HBAR ST_LINE_HBAR 48 [2] [1] [0] 0 0 0 0 0 0 0 0 0x00 HEIGHT_HBAR0 0x0A ST_LINE_HBAR0 0x0A 0x00 0x00 HEIGHT_HBAR1 0x0A ST_LINE_HBAR1 0x14 HEIGHT_HBAR2 0x0A ST_LINE_HBAR2 0x1E 0x00 0x00 HEIGHT_HBAR3 0x0A ST_LINE_HBAR3 0x28 HEIGHT_HBAR4 0x00 0x00 0x0A ST_LINE_HBAR4 0x32 HEIGHT_HBAR5 0x0A ST_LINE_HBAR5 B[15:8] B[ 7:0] 0x00 0x3C 0x00 0x00 HEIGHT_HBAR6 0x0A ST_LINE_HBAR6 0x46 0x00 0x00 HEIGHT_HBAR7 0x0A ST_LINE_HBAR7 0x50 Height (lines) of horizontal bar. Start line (position) of horizontal bar, ranges at [10 = 255] TW6869 Index 0x38 [6] [5] B3 B2 0 0 0 0 0 0 0 B1 0 0 0 B0 0 0 0 OUT_BITWIDTH 49 AUDIO_CONTROL3 [4] [3] [7] B[8] Default [2] [1] [0] 0 0 0 0 0x00 0 0 0 0 0 0x00 0 0 0 0 OUT_ BITWIDTH 0x00 0 0 0 0 0 0x40 Audio DMA output bit width 0 = 16 bits 1 = 8 bits TW6869 Index B3 0x39 0x3E 0x3F 0x40 START_ FLD1 FLD_OUT_OPT0[29:24] [0] 0x00 0x00 FLD_OUT_OPT1[29:24] 0x00 0x00 0x00 0x00 FLD_CTRL_ENA 2 START_ FLD2 FLD_OUT_OPT2[29:24] 0x00 0x00 FLD_OUT_OPT2[23:0] 0x00 0x00 FLD_CTRL_ENA 3 START_ FLD3 FLD_OUT_OPT3[29:24] 0x00 0x00 FLD_OUT_OPT3[23:0] 0x00 0x00 FLD_CTRL_ENA 4 START_ FLD4 FLD_OUT_OPT4[29:24] 0x00 0x00 FLD_OUT_OPT4[23:0] 0x00 0x00 FLD_CTRL_ENA 5 START_ FLD5 FLD_OUT_OPT5[29:24] 0x00 0x00 FLD_OUT_OPT5[23:0] 0x00 0x00 FLD_CTRL_ENA 6 START_ FLD6 FLD_OUT_OPT6[29:24] 0x00 0x00 FLD_OUT_OPT6[23:0] 0x00 0x00 FLD_CTRL_ENA 7 START_ FLD7 B2 B1 B0 FLD_OUT_OPT7[29:24] 0x00 0x00 FLD_OUT_OPT7[23:0] 0x00 0x00 FLD_CTRL_ENA B[31] START_FLD B[30] FLD_OUT_OPT B[29:0] 50 [1] FLD_OUT_OPT1[23:0] B2 B1 B0 B3 Default [2] 0x00 FLD_CTRL_ENA 1 B2 B1 B0 B3 VIDEO_FIELD_CTRL [4] [3] FLD_OUT_OPT0[23:0] B2 B1 B0 B3 [5] 0x00 B2 B1 B0 B3 0x3D START_ FLD0 B2 B1 B0 B3 0x3C FLD_CTRL_ENA 0 B2 B1 B0 B3 0x3B [6] B2 B1 B0 B3 0x3A [7] Enable bit for each field control register 0 = output both odd and even field 1 = output according to B20~B0 Starting field control bit 0 = starting from field 2 1 = starting from field 1 Output flag of consecutive 30(NTSC)/25(PAL) fields. 0 = not output 1 = output TW6869 Index [7] B3 0x42 HSCALER_ ENA0 B3 PHASE_ REF0[0] END_POS0[2:0] HSCALER_ ENA1 0x44 PHASE_ REF1[0] 0x45 END_POS2[2:0] B0 B3 0x46 END_POS3[2:0] B0 B3 0x47 END_POS4[2:0] B0 B3 0x48 0x49 0x71 0xD8 START_POS5 PHASE_REF6[15:9] PHASE_ REF6[0] END_POS6[2:0] 0x71 0xD8 START_POS6 PHASE_REF7[15:9] B0 HSCALER_ENA 0x71 END_POS7[9:3] END_POS7[2:0] B[31] 0xD8 START_POS7 Customize horizontal scaler enable bit 0 = disable 1 = enable PHASE_REF B[30:15] Scaler phase reference. Its calculation is Phase_ref=(END_POS–START_POS) *(2^16) / Total_Active_Pixel_Per_Line For example, START_POS = 10, END_POS = 710, Total_Active_Pixel_Per_Line = 720, Phase_ref = (710-10)*2^16/720 = 0xF8E3 51 0xCA 0x7C PHASE_REF7[8:1] PHASE_ REF7[0] 0xCA 0x7C END_POS6[9:3] HSCALER_ ENA7 0xCA 0x7C PHASE_REF6[8:1] B2 B1 START_POS4 END_POS5[2:0] HSCALER_ ENA6 B0 B3 0xD8 END_POS5[9:3] B2 B1 0x71 PHASE_REF5[8:1] PHASE_ REF5[0] 0xCA 0x7C PHASE_REF5[15:9] B2 B1 START_POS3 END_POS4[9:3] HSCALER_ ENA5 0x7C 0xD8 PHASE_REF4[8:1] PHASE_ REF4[0] 0xCA 0x71 PHASE_REF4[15:9] B2 B1 START_POS2 END_POS3[9:3] HSCALER_ ENA4 0x7C 0xD8 PHASE_REF3[8:1] PHASE_ REF3[0] 0xCA 0x71 PHASE_REF3[15:9] B2 B1 START_POS1 END_POS2[9:3] HSCALER_ ENA3 0x7C 0xD8 PHASE_REF2[15:9] PHASE_ REF2[0] 0xCA 0x71 PHASE_REF2[8:1] B0 B3 START_POS0 END_POS1[2:0] 0x7C 0xD8 END_POS1[9:3] HSCALER_ ENA2 [0] 0x71 PHASE_REF1[15:9] B2 B1 [1] PHASE_REF1[8:1] B0 B3 Default [2] END_POS0[9:3] B2 B1 HSCALER_CTRL [4] [3] PHASE_REF0[15:9] B2 B1 [5] PHASE_REF0[8:1] B0 0x43 [6] 0xCA TW6869 END_POS B[14:5] START_POS B[4:0] 52 End pixel position of each line. This pixel will NOT be shown and the setting must be an even number. Start pixel position of each line. This pixel will be shown and the setting must be an even number. TW6869 Index VIDEO_SIZE [4] [3] [7] [6] [5] B3 B2 B1 B0 VS_EN0 VS_F2_EN0 0 0 0 0 0 0 B3 B2 B1 B0 VS_EN1 B3 B2 B1 B0 VS_EN2 B3 B2 B1 B0 VS_EN3 VS_F2_EN3 0 0 0 0 0 0 VS_EN4 0x4E B3 B2 B1 B0 0 0 0 0 VS_EN5 VS_F2_EN5 0 0 0x4F B3 B2 B1 B0 B3 B2 B1 B0 VS_EN6 VS_F2_EN6 0 0 0 0 0 0 B3 B2 B1 B0 VS_EN7 0x4A 0x4B 0x4C 0x4D 0x50 0x51 [1] [0] 0 0 V_SIZE0[8] V_SIZE0[7:0] VS_F2_EN1 0 0 H_SIZE0[10:8] 0x02 0xD0 0 0 0 V_SIZE1[8] V_SIZE1[7:0] 0 0 0 0 0 0 H_SIZE1[10:8] 0x02 0xD0 0 0 0 V_SIZE2[8] V_SIZE2[7:0] 0 0 0 0 0 H_SIZE2[10:8] 0x02 0xD0 0 0 0 V_SIZE3[8] V_SIZE3[7:0] 0 H_SIZE3[10:8] 0x02 0xD0 0 0 0 V_SIZE4[8] V_SIZE4[7:0] H_SIZE4[10:8] 0x02 0xD0 0 0 0 V_SIZE5[8] V_SIZE5[7:0] 0 0 0 0 H_SIZE5[10:8] 0x02 0xD0 0 0 0 V_SIZE6[8] V_SIZE6[7:0] 0 H_SIZE6[10:8] 0x02 0xD0 0 0 0 V_SIZE7[7:0] 0 0 0 0 VS_F2_EN B[30] V_SIZE H_SIZE B[24:16] B[10:0] V_SIZE7[8] 0x00 0xF0 0 H_SIZE7[10:8] H_SIZE7[7:0] B[31] 0x00 0xF0 0 H_SIZE6[7:0] 0 0x00 0xF0 H_SIZE5[7:0] VS_F2_EN7 0x00 0xF0 0 H_SIZE4[7:0] 0 0x00 0xF0 0 H_SIZE3[7:0] 0 0x00 0xF0 H_SIZE2[7:0] VS_F2_EN4 0x00 0xF0 0 H_SIZE1[7:0] VS_F2_EN2 0x00 0xF0 0 H_SIZE0[7:0] VS_EN 53 0 Default [2] Customize video size enable bit 0 = disable 1 = enable Enable to field 2 video size control registers 0 = Field 2 video size controlled by VIDEO_SIZEx 1 = Field 2 video size controlled by VIDEO_SIZEx_F2 Note: “x” means DMA channel number (0~7) Height of field. Width of field 0x02 0xD0 TW6869 Index B3 0x52 0x53 0x54 0x55 0x56 0x58 0x59 [5] 0 0 0 VIDEO_SIZE_F2 [4] [3] 0 0 B3 0 0 0 0 B2 B1 B0 0 0 0 0 0 0 0 [0] 0 0 V_SIZE0_ F2[8] 0 0 H_SIZE0_F2[10:8] 0x02 0xD0 0 V_SIZE1_ F2[8] 0 0 B2 B1 B0 0 0 0 0 0 H_SIZE1_F2[10:8] 0x02 0xD0 0 V_SIZE2_F2 [8] 0 V_SIZE2_F2[7:0] 0 0 0 0 B2 B1 B0 0 0 0 0 0 H_SIZE2_F2[10:8] 0x02 0xD0 0 V_SIZE3_F2 [8] 0 V_SIZE3_F2[7:0] 0 0 0 0 B2 B1 B0 0 0 0 0 0 H_SIZE3_F2[10:8] 0x02 0xD0 0 V_SIZE4_F2 [8] 0 V_SIZE4_F2[7:0] 0 0 B3 0 0 0 0 0 H_SIZE4_F2[10:8] 0x02 0xD0 0 V_SIZE5_F2 [8] 0 V_SIZE5_F2[7:0] 0 0 0 0 0 0 0 H_SIZE5_F2[10:8] 0x02 0xD0 0 V_SIZE6_F2 [8] 0 V_SIZE6_F2[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 H_SIZE6_F2[10:8] H_SIZE7_F2[7:0] B[24:16] B[10:0] Height of field 2. Width of field 2. 0x02 0xD0 0 0 V_SIZE7_F2[8] V_SIZE7_F2[7:0] 0 0x00 0xF0 H_SIZE6_F2[7:0] 0 0x00 0xF0 H_SIZE5_F2[7:0] 0 0x00 0xF0 0 H_SIZE4_F2[7:0] B2 B1 B0 0x00 0xF0 0 H_SIZE3_F2[7:0] B3 0x00 0xF0 0 H_SIZE2_F2[7:0] B3 0x00 0xF0 0 H_SIZE1_F2[7:0] 0 0x00 0xF0 V_SIZE1_F2[7:0] 0 B3 B2 B1 B0 [1] H_SIZE0_F2[7:0] 0 B2 B1 B0 0 Default [2] V_SIZE0_F2[7:0] B3 V_SIZE_F2 H_SIZE_F2 54 [6] B2 B1 B0 B3 0x57 [7] 0x00 0xF0 H_SIZE7_F2[10:8] 0x02 0xD0 TW6869 [7] [6] [5] [4] MD_CONF [3] [2] [1] [0] B3 B2 B1 B0 0 0 0 0 0 0 0 0 MD0_ACT_FLD MD0_MODE B3 B2 B1 B0 0 B3 B2 B1 B0 0 B3 B2 B1 B0 0 0 0x64 B3 B2 B1 B0 0 0x65 B3 B2 B1 B0 B3 B2 B1 B0 0 B3 B2 B1 B0 0 Index 0x60 0x61 0x62 0x63 0x66 0x67 MD0_TSCALE 0 0 MD1_TSCALE 0 0 MD2_TSCALE MD0_THRESHOLD[17:16] 0 0x04 0x10 0 0 0 MD1_ENABLE MD1_ACT_FLD MD1_MODE 0 0 MD1_THRESHOLD[17:16] MD3_TSCALE 0 0 MD4_TSCALE 0x04 0x10 0 0 MD2_ACT_FLD MD2_MODE 0 0 MD2_THRESHOLD[17:16] MD5_TSCALE 0 MD3_ACT_FLD MD3_MODE 0 0 MD3_THRESHOLD[17:16] 0x04 0x10 0 0 0 MD4_ENABLE MD4_ACT_FLD MD4_MODE 0 0 MD4_THRESHOLD[17:16] MD6_TSCALE 0 MD7_TSCALE B[23:21] B[20] MD_ACT_FLD B [19] MD_MODE B [18] MD_TRESHOLD B[17:0] 0 0x05 0x10 0 0 MD5_ENABLE MD5_ACT_FLD MD5_MODE MD6_ENABLE 0x00 0x04 0 0 0x05 MD3_THRESHOLD[7:0] 0 0 MD5_THRESHOLD[17:16] 0x00 0x05 0x04 MD5_THRESHOLD[7:0] 0 0x00 MD3_THRESHOLD[15:8] MD5_THRESHOLD[15:8] 0 0x05 0x10 0 MD4_THRESHOLD[7:0] 0 0x00 0x04 MD4_THRESHOLD[15:8] 0 0x05 MD1_THRESHOLD[7:0] 0 MD3_ENABLE 0x00 MD1_THRESHOLD[15:8] MD2_ENABLE 0 0x05 MD0_THRESHOLD[7:0] MD2_THRESHOLD[7:0] 0 0x00 MD0_THRESHOLD[15:8] MD2_THRESHOLD[15:8] MD_TSCALE MD_ENABLE 55 MD0_ENABLE Default 0x10 0 0 MD6_ACT_FLD MD6_MODE 0 0 MD6_THRESHOLD[17:16] 0x00 0x05 MD6_THRESHOLD[15:8] 0x04 MD6_THRESHOLD[7:0] 0x10 0 0 0 MD7_ENABLE MD7_ACT_FLD MD7_MODE 0 0 MD7_THRESHOLD[17:16] 0x00 0x05 MD7_THRESHOLD[15:8] 0x04 MD7_THRESHOLD[7:0] 0x10 Scale amount of threshold (T