TW6872-NA1-CR-EVALZ

DATASHEET TW6872 FN8616 Rev 0.00 May 23, 2014 Triple-Rate (SD/HD/3G) SDI Transmitter with VC-2 Encoder and Audio Decoder Features The TW6872 is a triple-rate (SD/HD/3G) SDI transmitter. It receives parallel BT.656/BT.1120/ASI video data from a CMOS sensor/ISP chip. It also receives analog audio, or serial digital audio. The TW6872 serializes the video and audio into an SDI stream and transmits it to an SDI receiver via its integrated cable driver. • Triple-rate (SD/HD/3G) SDI transmitter for Standard Definition (SD) and High Definition (HD), and 3G 10-bit component video • Encoding SDI standard of ITU-R BT.656/SMPTE 259M Level C, ITU-R BT.1120/SMPTE ST 292, SMPTE 424M 10-bit parallel component video inputs into 10-bit serial video output • BT.656/BT.1120 interface for CMOS sensor/ISP chip In addition to the standard SDI format with uncompressed raw video data, TW6872 can optionally compress video with a visually lossless VC-2 compression algorithm to send the video formats normally running at HD rate (1.5Gbps) on the cable at SD rate (270Mbps), and therefore achieve longer cable reach. • Asynchronous Serial Interface (ASI) for IEC 13818-1 compliant transport streams Together, the TW6872 and Intersil’s TW6874 SDI receiver provide a complete end-to-end SDI link solution and can operate with or without VC-2 compression. Integrated audio/video test patterns and PRBS checker ease system design and implementation. • Integrated 75Ω cable driver with pre/de-emphasis • Integrated VC-2 encoder allows transmission of HD video over SD transmission lengths • Analog audio and I2S serial audio input interfaces over ancillary field The TW6872 is available in a 76 Ld QFN. It is specified for operation over the -40°C to +85°C ambient temperature range and operates on two power supplies: 1V and 3.3V. A single 27MHz crystal is used for all supported audio/video operating modes. • Digital audio with PCM encoding for embedding audio samples into the audio ancillary field of SDI stream • Single 27MHz clock/crystal input Applications • Optional clock output for use as the ISP chip’s clock input to enhance overall jitter • SD/HD/3G-SDI Camera • PRBS7/23 and video/audio pattern generator • I2C for external micro-controller interface • Low power consumption • Small footprint LTZ-QFN76L (9mm x9mm) package • Pb-free (RoHS compliant) 1.0V 3.3V CLK CMOS SENSOR 3.3V ISP 21 3 DATA CLKO SDO VD SDO d u m m y AIN0 4.7k 75 COAX 1µF 75 22pF 27MHz XTO AIN1 22pF RSET 1.6k  HOST PROCESSOR TW6874S DI RX XTI 2.2µF 4.7k  0  75  open* TW6872 1µF open* 3.3V I2S 2.2µF 0 75  IRQ I2C AINN *Final RLN values pending optimization. Place holder for inductor recommended. 2.2µF FIGURE 1. TW6872 TYPICAL APPLICATION FN8616 Rev 0.00 May 23, 2014 Page 1 of 44 d u m m y TW6872 Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Video Input Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master/Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Serial Interface Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 13 13 SDI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDI Video Standard Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cable Reach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre/De-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC-2 Compressed Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 13 14 Audio Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S Digital Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDI Ancillary Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 15 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDO Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Video Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 17 18 18 Other Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ancillary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 19 19 19 19 I2C Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 21 21 21 21 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ancillary Audio Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Audio Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 30 37 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FN8616 Rev 0.00 May 23, 2014 Page 2 of 44 TW6872 Block Diagram BT.1120 / BT.656 / ASI BT1120 VC-2 ENCODING STEREO ANALOG AUDIO INPUT SDI Tx PREEMPHASIS CABLE DRIVER SDI OUTPUT AUDIO DECODER STEREO I2S INPUT I2C FN8616 Rev 0.00 May 23, 2014 PLL Page 3 of 44 TW6872 Pin Configuration TW6872 (76 PIN QFN) TOP VIEW AVSS_ADCA AVDD_ADCA AVDD_ADCD AVSS_ADCD ADAT WCLK DVSSI ACLK DVDDI SDA IRQ SCL DVDDO DVSSO VD0 VD1 DVDDI NC VD2 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 VD3 DVSSI VD4 VD5 VD6 VD7 VD_CLK VD8 VD9 DVDDI VD10 VD11 DVSSI VD12 VD13 VD14 VD15 VD16 VD17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 EPAD AINN AIN0 AIN1 AVDD_SDO SDO SDOb AVSS_SDO AVDD_PLL2 AVSS_PLL2 AVDD_PLL1 AVSS_PLL1 ATEST RSET AVSS_MISC AVDD_MISC XTI XTO AVDD_PLL3 AVSS_PLL3 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 AVSS_PLLX4 AVDD_PLLX4 CLK108 TESTEN RSTB DVSSI TDO DVDDO DVSSO TDI DVDDI TMS TCLK MPP0 FN8616 Rev 0.00 May 23, 2014 CLKO DVDDO DVSSO DVSSI VD19 VD18 DVDDI DVDDI DVSSI AVDD_* AVSS_* Page 4 of 44 TW6872 Pin Descriptions PIN NUMBER PIN NAME TYPE 22 VD19 Digital Input 21 VD18 Digital Input 19 VD17 Digital Input 18 VD16 Digital Input 17 VD15 Digital Input 16 VD14 Digital Input 15 VD13 Digital Input 14 VD12 Digital Input 12 VD11 Digital Input 11 VD10 Digital Input 9 VD9 Digital Input 8 VD8 Digital Input 6 VD7 Digital Input 5 VD6 Digital Input 4 VD5 Digital Input 3 VD4 Digital Input 1 VD3 Digital Input 75 VD2 Digital Input 73 VD1 Digital Input 72 VD0 Digital Input DESCRIPTION PARALLEL DIGITAL VIDEO Parallel video data input. HD/3G mode: Chroma (C) data SD mode: not used ASI mode: not used Parallel video data input. HD/3G mode: Luma (Y) data SD mode: multiplexed BT.656 chroma/luma data ASI mode: transport stream data input Parallel video clock input. 7 VD_CLK Digital Input 3G mode: 148.5MHz HD mode: 74.25MHz SD mode: 27MHz ASI mode: 27MHz Clock source for the ISP in master mode. Generated frequencies are: 27MHz 3G mode: 148.5MHz HD mode: 74.25MHz or 148.5MHz SD mode: 13.5MHz or 27MHz 26 CLKO Digital Output 36 CLK108 Digital I/O 62 ADAT Digital Input Audio serial data input. 63 WCLK Digital Input Audio word clock input. 65 ACLK Digital Input Audio serial bit clock. Alternate 108MHz clock source for the ISP in master mode I2S AUDIO FN8616 Rev 0.00 May 23, 2014 Page 5 of 44 TW6872 Pin Descriptions (Continued) PIN NUMBER PIN NAME TYPE DESCRIPTION 67 SDA Digital I/O 68 SCL Digital Input 32 TDO Digital Output JTAG test data output. 31 TDI Digital Input JTAG test data input. 29 TMS Digital Input JTAG test mode start. 28 TCLK Digital Input JTAG test clock input. 69 IRQ Digital I/O 34 RSTB Digital Input Resets chip when pulled LO. Reset must be asserted for 1µs every time the power supplies have powered up and settled to their final value. 35 TESTEN Digital Input For internal use only. Tie LO. 27 MPP0 Digital I/O 46 ATEST Analog Output 76 NC No Connect 53 SDO Analog Output SDI serial data output. See “SDO Routing” on page 15 for termination guidelines. 52 SDOb Analog Output Inverted SDI serial data output. See “SDO Routing” on page 15 for termination guidelines. 45 RSET Analog Output Tie a 1.6kΩ (1%) resistor from this pin to analog ground. The resistor should be placed as close as possible to the RSET pin. SDI output amplitude can be adjusted by changing the value of the resistor. 42 XTI Analog Input 41 XTO Analog Output 55 AIN1 Analog Input Audio input for channel 1. Terminate with 4.7kΩ to ground and AC-couple with 2.2μF. 56 AIN0 Analog Input Audio input for channel 0. Terminate with 4.7kΩ to ground and AC-couple with 2.2μF. 57 AINN Analog Input Audio ADC reference. Terminate with 2.2μF to ground. Do not connect external audio signal to this pin. 10, 20, 30, 66, 74 DVDDI Digital Power 1.0V digital power supply for core. Place a local 0.1μF ceramic bypass capacitor to the digital ground as close to the pin as possible. 2, 13, 23, 33, 64 DVSSI Digital Ground Digital ground. 25, 70 DVDDO Digital Power 3.3V digital power supply for I/O. Place a local 0.1μF ceramic bypass capacitor to the digital ground as close to the pin as possible. 24, 71 DVSSO Digital Ground Digital ground. I2C I2C serial data IO. Requires pull-up resistor to VDDO. I2C serial clock input. Requires pull-up resistor to VDDO. JTAG SYSTEM Interrupt request. Multi-purpose pin. Analog test output. For internal use only. Do not connect anything to this pin. Do not connect anything to this pin. SERIAL DATA OUTPUT CLOCK INPUT 27MHz crystal connection or 27MHz oscillator input. 27MHz crystal connection. ANALOG AUDIO DIGITAL POWER FN8616 Rev 0.00 May 23, 2014 Page 6 of 44 TW6872 Pin Descriptions (Continued) PIN NUMBER PIN NAME TYPE DESCRIPTION 54 AVDD_SDO Analog Power 3.3V analog power supply for SDO driver. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 51 AVSS_SDO Analog Ground Analog ground. 43 AVDD_MISC Analog Power 3.3V analog power supply for SDO driver. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 44 AVSS_MISC Analog Ground Analog ground. 60 AVDD_ADCD Analog Power 3.3V analog power supply for ADC. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 61 AVSS_ADCD Analog Ground Analog ground. 59 AVDD_ADCA Analog Power 3.3V analog power supply for ADC. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 58 AVSS_ADCA Analog Ground Analog ground. 48 AVDD_PLL1 Analog Power 3.3V analog power supply for PLL. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 47 AVSS_PLL1 Analog Ground Analog ground. 50 AVDD_PLL2 Analog Power 3.3V analog power supply for PLL. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 49 AVSS_PLL2 Analog Ground Analog ground. 40 AVDD_PLL3 Analog Power 3.3V analog power supply for PLL. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 39 AVSS_PLL3 Analog Ground Analog ground. 37 AVDD_PLLX4 Analog Power 3.3V analog power supply for PLL. Place a local 0.1μF ceramic bypass capacitor to the analog ground as close to the pin as possible. 38 AVSS_PLLX4 Analog Ground Analog ground. EPAD EPAD Ground ANALOG POWER Ground. Ordering Information PART NUMBER (Notes 1, 2) TW6872-NA1-CR PART MARKING TW6872 NA1-CR TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-Free) 76 Lead QFN PKG. DWG. # L76.9x9 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for TW6872. For more information on MSL please see tech brief TB363. FN8616 Rev 0.00 May 23, 2014 Page 7 of 44 TW6872 Absolute Maximum Ratings Thermal Information Supply Pins AVDD_SDO to AVSS_SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_MISC to AVSS_MISC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_ADCA to AVSS_ADCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_ADCD to AVSS_ADCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_PLL1 to AVSS_PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_PLL2 to AVSS_PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_PLL3 to AVSS_PLL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V AVDD_PLLX4 to AVSS_PLLX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V DVDDI to DVSSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.2V DVDDO to DVSSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.0V Other Pins Voltage on any Input Pin . . . . . . . . . . . . . . . . . . DVSSO-0.3 V to DVDDO V SDO/SDOb Voltage. . . . . . . . . . . . . . . . . . . .AVSS_SDO V to AVDD_SDO V XTI/XTO Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 1 V AIN0/1/N Voltage . . . . . . . . . . . . . . . . . AVSS_ADCA V to AVDD_ADCA V ESD Ratings IEC 61000-4-2 (contact discharge) Analog Audio Pins . . . . . . . . . . . 6kV Human Body Model (JEDEC JS-001-2011) all Pins . . . . . . . . . . . . . . 2kV Charged Device Model (JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . . 750V Latch Up (Tested per JESD78; Class II, Level A) . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) QFN Package (Notes 3, 4) . . . . . . . . . . . . . . 22 1.5 Power Dissipation. . . . . . . . . . . . . . . . . . . . . .See “Electrical Specifications” Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications DVDDI = 1.0V, AVDD_SDO = AVDD_MISC = AVDD_ADCD = AVDD_ADCA = AVDD_PLL1 = AVDD_PLL2 = AVDD_PLL3 = AVDD_PLLX4 = DVDDO = 3.3V, TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNIT POWER SUPPLY VOLTAGE AVDD_SDO Analog SDO Driver Supply Voltage 3.0 3.3 3.6 V AVDD_MISC Analog Misc Supply Voltage 3.0 3.3 3.6 V AVDD_ADCA Analog ADC Supply Voltage 3.0 3.3 3.6 V AVDD_ADCD Analog ADC Supply Voltage 3.0 3.3 3.6 V AVDD_PLL1 Analog PLL Supply Voltage 3.0 3.3 3.6 V AVDD_PLL2 Analog PLL Supply Voltage 3.0 3.3 3.6 V AVDD_PLL3 Analog PLL Supply Voltage 3.0 3.3 3.6 V AVDD_PLLX4 Analog PLL Supply Voltage 3.0 3.3 3.6 V DVDDI Digital Core Supply Voltage 0.9 1.0 1.1 V DVDDO Digital IO Supply Voltage 3.0 3.3 3.6 V POWER DISSIPATION 60 mA I_AVDD_SDO Analog SDO Supply Current 60 mA I_DVDDI Digital Core Supply Current 90 mA I_DVDDO Digital IO Supply Current 6 mA PTOT Total Power 505.8 mW I_AVDD Analog Supply Current (Note 10) (all AVDD_* tied together except SDO) FN8616 Rev 0.00 May 23, 2014 Page 8 of 44 TW6872 Electrical Specifications DVDDI = 1.0V, AVDD_SDO = AVDD_MISC = AVDD_ADCD = AVDD_ADCA = AVDD_PLL1 = AVDD_PLL2 = AVDD_PLL3 = AVDD_PLLX4 = DVDDO = 3.3V, TA = +25°C, unless otherwise specified. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNIT 148.5 MHz PARALLEL VIDEO INPUT fVDCLK Pixel Clock Frequency DCYCVDCLK Pixel Clock Duty Cycle 27 tSU Data Set-up Time 3.8 ns tHD Data Hold Time 0.6 ns 50 % SERIAL DIGITAL OUTPUT DRSDO Serial Data Rate 0.27 OSSDO Serial Data Output Swing 720 OVSDO Serial Data Output Overshoot -10 TTSDO Transition (Rise/Fall) Time (20% to 80%) 270Mbps 1.485Gbps Difference between Rise/Fall Time 270Mbps 40 ps 1.485Gbps 10 ps TTDSDO RLSDO JITSDO Return Loss (Note 9) Output Jitter 400 2.97 Gbps 880 mV +10 % 850 1500 ps 135 270 ps 800