X28HC64KMB-70

® X28HC64 64K, 8K x 8 Bit Data Sheet June 1, 2005 FN8109.0 5 Volt, Byte Alterable EEPROM FEATURES • 70ns access time • Simple byte and page write —Single 5V supply —No external high voltages or VPP control circuits —Self-timed —No erase before write —No complex programming algorithms —No overerase problem • Low power CMOS —40mA active current max. —200µA standby current max. • Fast write cycle times —64-byte page write operation —Byte or page write cycle: 2ms typical —Complete memory rewrite: 0.25 sec. typical —Effective byte write cycle time: 32µs typical • Software data protection • End of write detection —DATA polling —Toggle bit • High reliability —Endurance: 1 million cycles —Data retention: 100 years • JEDEC approved byte-wide pin out DESCRIPTION The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinto for byte-wide memories, compatible with industry standard RAMs. The X28HC64 supports a 64-byte page write operation, effectively providing a 32µs/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features DATA Polling and Toggle Bit Polling, two methods providing early end of write detection. In addition, the X28HC64 includes a user-optional software data protection mode that further enhances Intersil’s hardware write protect capability. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN CONFIGURATIONS Plastic DIP Flat Pack CERDIP 1 2 3 4 5 6 8 9 10 11 12 13 14 28 27 26 25 24 23 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 29 28 27 26 A8 A9 A11 NC OE A10 CE I/O7 I/O6 I/O1 12 I/O0 11 A1 9 A3 7 A5 I/O 2 13 A0 10 A2 8 LCC PLCC VCC WE A12 NC NC NC A7 TSOP A2 A1 A0 I/O 0 I/O 1 I/O 2 NC VSS NC I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE A10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A3 A4 A5 A6 A7 A 12 NC NC VCC NC WE NC A8 A9 A 11 OE SOIC NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 4 3 2 1 32 31 30 X28HC64 7 X28HC64 22 X28HC64 (Top View) 25 24 23 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 I/O3 I/O4 VSS I/O5 NC PGA I/O3 15 VSS 14 I/O5 17 I/O4 16 CE 20 I/O 6 18 I/O 7 19 A 10 21 A11 23 A8 25 NC 26 X28HC64 A4 OE 6 (BOTTOM 22 VIEW) A12 2 A7 3 VCC 28 NC 1 A9 24 WE 27 5 A6 4 Bottom View 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC64 PIN DESCRIPTIONS Addresses (A0-A12) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC64. BLOCK DIAGRAM X Buffers Latches and Decoder A0–A12 Address Inputs Y Buffers Latches and Decoder I/O Buffers and Latches 65,536-Bit EEPROM Array PIN NAMES Symbol A0-A12 I/O0-I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect CE OE WE VCC VSS Control Logic and Timing I/O0–I/O7 Data Inputs/Outputs 2 FN8109.0 June 1, 2005 X28HC64 DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 2ms. Page Write Operation The page write feature of the X28HC64 allows the entire memory to be written in 0.25 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28HC64 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The X28HC64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment I/O DP TB 5 4 3 2 1 0 Reserved Toggle Bit DATA Polling DATA Polling (I/O7) The X28HC64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. 3 FN8109.0 June 1, 2005 X28HC64 DATA POLLING I/O7 Figure 2. DATA Polling Bus Sequence WE Last Write CE OE VIH I/O7 HIGH Z VOL A0–A12 An An An An An An An VOH X28HC64 Ready Figure 3. DATA Polling Software Flow Write Data DATA Polling can effectively reduce the time for writing to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. Writes Complete? Yes Save Last Data and Address No Read Last Address IO7 Compare? Yes No Ready 4 FN8109.0 June 1, 2005 X28HC64 THE TOGGLE BIT I/O6 Figure 4. Toggle Bit Bus Sequence WE Last Write CE OE I/O6 VOH * VOL HIGH Z * X28HC64 Ready * Beginning and ending state of I/O6 will vary. Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. Last Write Yes Load Accum From Addr N Compare Accum with Addr N Compare Ok? Yes No Ready 5 FN8109.0 June 1, 2005 X28HC64 HARDWARE DATA PROTECTION The X28HC64 provides two hardware features that protect nonvolatile data from inadvertent writes. – Default VCC Sense—All write functions are inhibited when VCC is 3V typically. – Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. SOFTWARE DATA PROTECTION The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during powerup/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC64 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device, unless the reset command is issued. Once the software protection is enabled, the X28HC64 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to sixty-four bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. 6 FN8109.0 June 1, 2005 X28HC64 SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write VCC 0V Data ADDR CE ≤tBLC MAX WE Byte or Page AAA 1555 55 0AAA A0 1555 Writes OK (VCC) tWC Write Protected Figure 7. Write Sequence for Software Data Protection Write Data AA to Address 1555 Write Data 55 to Address 0AAA Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued to deactivate it. If no further commands are issued the X28HC64 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. Write Data A0 to Address 1555 Byte/Page Load Enabled Write Data XX to Any Address Optional Byte/Page Load Operation Write Last Byte to Last Address After tWC Re-Enters Data Protected State 7 FN8109.0 June 1, 2005 X28HC64 RESETTING SOFTWARE DATA PROTECTION Figure 8. Reset Software Data Protection Timing Sequence VCC AAA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 Data ADDR CE ≥tWC Standard Operating Mode WE Figure 9. Software Sequence to Deactivate Software Data Protection Write Data AA to Address 1555 In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC64 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. Write Data 55 to Address 0AAA Write Data 80 to Address 1555 Write Data AA Address 1555 Write Data 55 to Address 0AAA Write Data 20 to Address 1555 8 FN8109.0 June 1, 2005 X28HC64 SYSTEM CONSIDERATIONS Because the X28HC64 is frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus, and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. Normalized ICC(RD) @ 25% Over the VCC Range and Frequency 1.4 Normalized ICC(RD) by Temperature Over Frequency 1.4 5.5 VCC 1.2 ICCRD Normalized (mA) 1.0 0.8 0.6 0.4 0.2 0 10 Frequency (MHz) 20 - 55°C + 25°C 1.2 ICCRD Normalized (mA) 1.0 5.5 VCC 5.0 VCC 4.5 VCC + 125°C 0.8 0.6 0.4 0.2 0 10 Frequency (MHz) 20 9 FN8109.0 June 1, 2005 X28HC64 ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC64 ......................................... -10°C to +85°C X28HC64I, X28HC64M .................. -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to VSS ......................................... -1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).................................. 300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min. 0°C -40°C -55°C Max. +70°C +85°C +125°C Supply Voltage X28HC64 Limits 5V ±10% D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ICC ISB1 ISB2 ILI ILO VlL (2) (2) Parameter VCC current (active) (TTL inputs) VCC current (standby) (TTL inputs) VCC current (standby) (CMOS inputs) Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Min. Typ.(1) 15 1 100 Max. 40 2 200 ±10 ±10 Unit mA mA µA µA µA V V V V IOL = 5mA IOH = -5mA Test Conditions CE = OE = VIL, WE = VIH, All I/O’s = open, address inputs = TTL levels @ f = 10 MHz CE = VIH, OE = VIL All I/O’s = open, other inputs = VIH CE = VCC - 0.3V, OE = GND, All I/O’s = open, other inputs = VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH -1 2 2.4 0.8 VCC + 1 0.4 VIH VOL VOH Notes: (1) Typical values are for TA = 25°C and nominal supply voltage (2) VIL min. and VIH max. are for reference only and are not tested. 10 FN8109.0 June 1, 2005 X28HC64 ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Max. Unit Cycles Years POWER-UP TIMING Symbol tPUR(3) tPUW (3) Parameter Power-up to read operation Power-up to write operation Typ.(1) 100 5 Unit µs ms CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol CI/O(3) CIN(3) Parameter Input/output capacitance Input capacitance Max. 10 6 Unit pF pF Test Conditions VI/O = 0V VIN = 0V A.C. CONDITIONS OF TEST Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 5ns 1.5V MODE SELECTION CE L L H X X OE WE L H X L X H L X X H Mode Read Write Standby and write inhibit Write inhibit Write inhibit I/O DOUT DIN High Z — — Power Active Active Standby — — Note: (3) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUITS 5V 1.92kΩ Output 1.37kΩ 30pF SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 11 FN8109.0 June 1, 2005 X28HC64 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read Cycle Limits X28HC64-70 -55°C to +125°C Symbol tRC tCE tAA tOE tLZ (4) (4) X28HC64-90 -55°C to +125°C Min. 90 X28HC64-12 -55°C to +125°C Min. 120 Parameter Read cycle time Chip enable access time Address access time Output enable access time CE LOW to active output OE LOW to active output CE HIGH to high Z output OE HIGH to high Z output Output hold from address change Min. 70 Max. 70 70 35 Max. 90 90 40 Max. 120 120 50 Unit ns ns ns ns ns ns 0 0 30 30 0 0 0 30 30 0 0 0 30 30 0 tOLZ tHZ (4) (4) ns ns ns tOHZ tOH Read Cycle tRC Address tCE CE tOE OE VIH WE tLZ Data I/O HIGH Z Data Valid tAA Note: (4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. tOLZ tOH Data Valid tHZ tOHZ 12 FN8109.0 June 1, 2005 X28HC64 WRITE CYCLE LIMITS Symbol tWC (5) Parameter Write cycle time Address setup time Address hold time Write setup time Write hold time CE pulse width OE High setup time OE High hold time WE pulse width WE HIGH recovery Data valid Data setup Data hold Delay to next write Byte load cycle Min. 0 50 0 0 50 0 0 50 50 Typ.(1) 2 Max. 5 Unit ms ns ns ns ns ns ns ns ns ns tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV (6) (6) 1 50 0 10 0.15 100 µs ns ns µs µs tDS tDH tDW(6) tBLC WE Controlled Write Cycle tWC Address tAS tCS CE tAH tCH OE tOES tWP WE tDV Data In tDS HIGH Z Data Out Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. (6) tWPH and tDW are periodically sampled and not 100% tested. Data Valid tDH tOEH 13 FN8109.0 June 1, 2005 X28HC64 CE CONTROLLED WRITE CYCLE tWC Address tAS CE tOES OE tOEH tCS WE tDV Data In tDS Data Out HIGH Z Data Valid tDH tCH tAH tCW Page Write Cycle OE(7) CE tWP WE tWPH tBLC Address*(8) I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Last Byte Byte n+2 tWC *For each successive write within the page write operation, A6–A12 should be the same or writes to an unknown address could occur. Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 14 FN8109.0 June 1, 2005 X28HC64 DATA Polling Timing Diagram(9) Address An An An CE WE tOEH tOES OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X Toggle Bit Timing Diagram(9) CE WE tOEH OE tDW I/O*6 HIGH Z * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings. * tOES 15 FN8109.0 June 1, 2005 X28HC64 Ordering Information X28HC64 Device X X -X Access Time -70 = 70ns -90 = 90ns -12 = 120ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C M = Military = -55°C to +125°C MB = MIL-STD-883 Package P = 28-Lead Plastic DIP D = 28-Lead Cerdip J = 32-Lead PLCC S = 28-Lead Plastic SOIC E = 32-Pad LCC K = 28-Lead Pin Grid Array F = 28-Lead Flat Pack T = 32-Lead TSOP All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN8109.0 June 1, 2005