X28HC64
®
64K, 8K x 8 Bit
Data Sheet
June 7, 2006
5 Volt, Byte Alterable EEPROM
FN8109.1
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free plus anneal available (RoHS compliant)
FEATURES
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or VPP control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
—DATA polling
—Toggle bit
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
A5
5
24
A9
A4
6
23
A11
A3
7 X28HC64 22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
VSS
14
15
I/O3
WE
NC
1 32 31 30
A6
5
29
A8
A5
6
28
A9
A4
7
27
A11
A3
8
26
NC
A2
9
A1
X28HC64
(Top View)
25
OE
10
24
A10
A0
11
23
CE
NC
12
22
I/O7
13
21
14 15 16 17 18 19 20
I/O6
I/O0
I/O5
A6
A8
2
I/O4
NC
25
NC
26
4
3
I/O3
3
NC
A7
4
NC
WE
A12
VCC
27
VSS
28
2
I/O2
1
I/O1
NC
A12
TSOP
A7
SOIC
VCC
LCC
PLCC
Plastic DIP
Flat Pack
CERDIP
A2
A1
A0
I/O 0
I/O 1
I/O 2
NC
VSS
NC
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
X28HC64
A3
A4
A5
A6
A7
A 12
NC
NC
VCC
NC
WE
NC
A8
A9
A 11
OE
PGA
I/O1
12
I/O 2
13
I/O3
15
I/O5
17
I/O 6
18
I/O0
11
A0
10
VSS
14
I/O4
16
I/O 7
19
A1
A2
8
CE
20
A 10
21
A3
A4
OE
6 (BOTTOM 22
VIEW)
A11
23
A5
A12
2
A9
24
A8
25
A6
A7
3
WE
27
NC
26
9
7
5
4
X28HC64
VCC
28
NC
1
Bottom View
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC64
Ordering Information
PART NUMBER
PART MARKING
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns)
-55 to 125
70
PACKAGE
PKG. DWG. #
X28HC64EM-70
X28HC64EM-70
X28HC64J-70*
X28HC64J-70
0 to 70
32 Ld PLCC
N32.45x55
X28HC64JI-70*
X28HC64JI-70
-40 to 85
32 Ld PLCC
N32.45x55
X28HC64JIZ-70* (Note)
X28HC64JI-70 Z
-40 to 85
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64JZ-70* (Note)
X28HC64J-70 Z
0 to 70
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64KM-70
X28HC64KM-70
-55 to 125
28 Ld PGA
G28.550x650A
X28HC64P-70
X28HC64P-70
0 to 70
28 Ld PDIP
E28.6
X28HC64PZ-70 (Note)
X28HC64P-70 Z
0 to 70
28 Ld PDIP** (Pb-free)
E28.6
X28HC64S-70*
X28HC64S-70
0 to 70
28 Ld SOIC (300 mil)
M28.3
X28HC64SI-70*
X28HC64SI-70
-40 to 85
28 Ld SOIC (300 mil)
M28.3
X28HC64SM-70*
X28HC64SM-70
-55 to 125
28 Ld SOIC (300 mil)
M28.3
X28HC64SZ-70 (Note)
X28HC64S-70 Z
0 to 70
28 Ld SOIC (300 mil) (Pb-free)
M28.3
X28HC64J-90*
X28HC64J-90
0 to 70
32 Ld PLCC
N32.45x55
X28HC64JI-90*
X28HC64JI-90
-40 to 85
32 Ld PLCC
N32.45x55
X28HC64JIZ-90* (Note)
X28HC64JI-90 Z
-40 to 85
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64KM-90
X28HC64KM-90
-55 to 125
28 Ld PGA
G28.550x650A
X28HC64KMB-90
C X28HC64KMB-90
MIL-STD-883
28 Ld PGA
G28.550x650A
X28HC64P-90
X28HC64P-90
0 to 70
28 Ld PDIP
E28.6
X28HC64PI-90
X28HC64PI-90
-40 to 85
28 Ld PDIP
E28.6
X28HC64PIZ-90 (Note)
X28HC64PI-90 Z
-40 to 85
28 Ld PDIP** (Pb-free)
E28.6
X28HC64PZ-90 (Note)
X28HC64P-90 Z
0 to 70
28 Ld PDIP** (Pb-free)
E28.6
X28HC64S-90*
X28HC64S-90
0 to 70
28 Ld SOIC (300 mil)
M28.3
2
90
32 Ld LCC (458 mil)
FN8109.1
June 7, 2006
X28HC64
Ordering Information (Continued)
PART NUMBER
PART MARKING
TEMPERATURE
RANGE (°C)
ACCESS TIME
(ns)
120
PACKAGE
PKG. DWG. #
X28HC64D-12
X28HC64D-12
0 to 70
X28HC64DI-12
X28HC64DI-12
-40 to 85
28 Ld CERDIP
X28HC64DM-12
X28HC64DM-12
-55 to 125
28 Ld CERDIP
X28HC64DMB-12
C X28HC64DMB-12
MIL-STD-883
28 Ld CERDIP
X28HC64FM-12
X28HC64FM-12
X28HC64J-12*
X28HC64J-12
0 to 70
32 Ld PLCC
N32.45x55
X28HC64JI-12*
X28HC64JI-12
-40 to 85
32 Ld PLCC
N32.45x55
X28HC64JIZ-12* (Note)
X28HC64JI-12 Z
-40 to 85
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64JZ-12* (Note)
X28HC64J-12 Z
0 to 70
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64KMB-12
C X28HC64KMB-12
MIL-STD-883
28 Ld PGA
G28.550x650A
X28HC64P-12
X28HC64P-12
0 to 70
28 Ld PDIP
E28.6
X28HC64PI-12
X28HC64PI-12
-40 to 85
28 Ld PDIP
E28.6
X28HC64PIZ-12 (Note)
X28HC64PI-12 Z
-40 to 85
28 Ld PDIP** (Pb-free)
E28.6
X28HC64PZ-12 (Note)
X28HC64P-12 Z
0 to 70
28 Ld PDIP** (Pb-free)
E28.6
X28HC64S-12*
X28HC64S-12
0 to 70
28 Ld SOIC (300 mil)
M28.3
X28HC64SI-12*
X28HC64SI-12
-40 to 85
28 Ld SOIC (300 mil)
M28.3
X28HC64SIZ-12* (Note)
X28HC64SI-12 Z
-40 to 85
28 Ld SOIC (300 mil) (Pb-free)
M28.3
X28HC64SZ-12 (Note)
X28HC64S-12 Z
0 to 70
28 Ld SOIC (300 mil) (Pb-free)
M28.3
X28HC64DM-15
X28HC64DM-15
-55 to 125
X28HC64J-15T1
X28HC64J-15
0 to 70
X28HC64JI-15
X28HC64JI-15
X28HC64JM-15
-55 to 125
28 Ld CERDIP
28 Ld FLATPACK (440 mil)
150
28 Ld CERDIP
32 Ld PLCC Tape and Reel
N32.45x55
-40 to 85
32 Ld PLCC
N32.45x55
X28HC64JM-15
-55 to 125
32 Ld PLCC
N32.45x55
X28HC64JZ-15* (Note)
X28HC64J-15 Z
0 to 70
32 Ld PLCC (Pb-free)
N32.45x55
X28HC64KMB-15
C X28HC64KMB-15
MIL-STD-883
28 Ld PGA
G28.550x650A
X28HC64P-15
X28HC64P-15
0 to 70
28 Ld PDIP
E28.6
X28HC64PIZ-15 (Note)
X28HC64PI-15 Z
-40 to 85
28 Ld PDIP** (Pb-free)
E28.6
X28HC64PZ-15 (Note)
X28HC64P-15 Z
0 to 70
28 Ld PDIP** (Pb-free)
E28.6
X28HC64S-15
X28HC64S-15
0 to 70
28 Ld SOIC (300 mil)
M28.3
X28HC64SI-15
X28HC64SI-15
-40 to 85
28 Ld SOIC (300 mil)
M28.3
*Add "T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN8109.1
June 7, 2006
X28HC64
PIN NAMES
PIN DESCRIPTIONS
Addresses (A0-A12)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Symbol
Description
A0-A12
Address Inputs
I/O0-I/O7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
VCC
+5V
VSS
Ground
NC
No Connect
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28HC64 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC64.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
65,536-Bit
EEPROM
Array
A0–A12
Address
Inputs
CE
OE
WE
Y Buffers
Latches
and
Decoder
I/O Buffers
and Latches
Control
Logic and
Timing
I/O0–I/O7
Data Inputs/Outputs
VCC
VSS
4
FN8109.1
June 7, 2006
X28HC64
Write Operation Status Bits
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28HC64 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
5
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
FN8109.1
June 7, 2006
X28HC64
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
WE
Last
Write
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
A0–A12
An
An
An
Figure 3. DATA Polling Software Flow
Write Data
X28HC64
Ready
An
An
An
An
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method
of implementing the routine.
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO7
Compare?
No
Yes
Ready
6
FN8109.1
June 7, 2006
X28HC64
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
WE
Last
Write
CE
OE
VOH
I/O6
*
HIGH Z
VOL
*
X28HC64
Ready
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
Last Write
Yes
Load Accum
From Addr N
Compare
Accum with
Addr N
No
Compare
Ok?
Yes
Ready
7
FN8109.1
June 7, 2006
X28HC64
HARDWARE DATA PROTECTION
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default VCC Sense—All write functions are inhibited
when VCC is 3V typically.
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with
the software data protection NOT ENABLED; that is,
the device will be in the standard operating mode. In
this mode data should be protected during power-up/down operations through the use of external circuits.
The host would then have open read and write access
of the device once VCC was stable.
8
The X28HC64 can be automatically protected during
power-up and power-down without the need for external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will
remain set for the life of the device, unless the reset
command is issued.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
The three-byte sequence opens the page write window,
enabling the host to write from one to sixty-four bytes
of data. Once the page load cycle has been completed, the device will automatically be returned to the
data protected state.
FN8109.1
June 7, 2006
X28HC64
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
VCC
(VCC)
0V
Data
ADDR
AAA
1555
55
0AAA
A0
1555
Writes
OK
tWC
Write
Protected
CE
≤tBLC MAX
WE
Byte
or
Page
Figure 7. Write Sequence for Software
Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued
to deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Write Data AA
to Address
1555
Write Data 55
to Address
0AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
1555
Byte/Page
Load Enabled
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After tWC
Re-Enters Data
Protected State
9
FN8109.1
June 7, 2006
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
VCC
Data
ADDR
AAA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
≥tWC
Standard
Operating
Mode
CE
WE
Figure 9. Software Sequence to Deactivate Software
Data Protection
Write Data AA
to Address
1555
Write Data 55
to Address
0AAA
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28HC64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data 80
to Address
1555
Write Data AA
Address
1555
Write Data 55
to Address
0AAA
Write Data 20
to Address
1555
10
FN8109.1
June 7, 2006
X28HC64
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large
memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus, and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Normalized ICC(RD) by Temperature
Over Frequency
Because the X28HC64 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.4
5.5 VCC
1.2
- 55°C
5.5 VCC
1.2
1.0
5.0 VCC
+ 125°C
ICCRD
Normalized (mA)
ICCRD
Normalized (mA)
+ 25°C
0.8
0.6
0.4
1.0
4.5 VCC
0.8
0.6
0.4
0.2
0.2
0
10
Frequency (MHz)
11
20
0
10
20
Frequency (MHz)
FN8109.1
June 7, 2006
X28HC64
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
X28HC64 ......................................... -10°C to +85°C
X28HC64I, X28HC64M .................. -65°C to +135°C
Storage temperature.......................... -65°C to +150°C
Voltage on any pin with
respect to VSS ......................................... -1V to +7V
D.C. output current ............................................... 5mA
Lead temperature
(soldering, 10 seconds).................................. 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X28HC64
5V ±10%
Industrial
-40°C
+85°C
Military
-55°C
+125°C
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Min.
Typ.(1)
Max.
Unit
ICC
VCC current (active)
(TTL inputs)
15
40
mA
CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = TTL levels @ f = 10 MHz
ISB1
VCC current (standby)
(TTL inputs)
1
2
mA
CE = VIH, OE = VIL All I/O’s = open,
other inputs = VIH
ISB2
VCC current (standby)
(CMOS inputs)
100
200
µA
CE = VCC - 0.3V, OE = GND, All I/O’s = open,
other inputs = VCC - 0.3V
ILI
Input leakage current
±10
µA
VIN = VSS to VCC
ILO
Output leakage current
±10
µA
VOUT = VSS to VCC, CE = VIH
VlL
Parameter
Test Conditions
(2)
Input LOW voltage
-1
0.8
V
(2)
Input HIGH voltage
2
VCC + 1
V
0.4
V
IOL = 5mA
V
IOH = -5mA
VIH
VOL
Output LOW voltage
VOH
Output HIGH voltage
2.4
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage
(2) VIL min. and VIH max. are for reference only and are not tested.
12
FN8109.1
June 7, 2006
X28HC64
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Unit
Minimum endurance
100,000
Cycles
Data retention
100
Years
POWER-UP TIMING
Symbol
Parameter
Typ.(1)
Unit
tPUR(3)
Power-up to read operation
100
µs
(3)
Power-up to write operation
5
ms
tPUW
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Unit
Test Conditions
CI/O(3)
CIN(3)
Input/output capacitance
10
pF
VI/O = 0V
Input capacitance
6
pF
VIN = 0V
A.C. CONDITIONS OF TEST
MODE SELECTION
CE
OE WE
Mode
I/O
Power
H
Read
DOUT
Active
H
L
Write
DIN
Active
H
X
X
Standby and
write inhibit
High Z
Standby
X
L
X
Write inhibit
—
—
X
X
H
Write inhibit
—
—
Input pulse levels
0V to 3V
Input rise and fall times
5ns
L
L
Input and output timing levels
1.5V
L
Note:
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
5V
SYMBOL TABLE
WAVEFORM
1.92kΩ
Output
1.37kΩ
30pF
13
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8109.1
June 7, 2006
X28HC64
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle Limits
Symbol
Parameter
X28HC64-70
X28HC64-90
X28HC64-12
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
Min.
Max.
Max.
Max.
Unit
Read cycle time
tCE
Chip enable access time
70
90
120
ns
tAA
Address access time
70
90
120
ns
tOE
Output enable access time
35
40
50
ns
tLZ
tOLZ
tHZ
(4)
(4)
tOHZ
(4)
tOH
90
Min.
tRC
(4)
70
Min.
120
ns
CE LOW to active output
0
0
0
ns
OE LOW to active output
0
0
0
ns
CE HIGH to high Z output
30
30
30
ns
OE HIGH to high Z output
30
30
30
ns
Output hold from address change
0
0
0
ns
Read Cycle
tRC
Address
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
Data I/O
HIGH Z
tOH
tHZ
Data Valid
Data Valid
tAA
Note:
(4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
14
FN8109.1
June 7, 2006
X28HC64
WRITE CYCLE LIMITS
Symbol
tWC
(5)
Parameter
Min.
Write cycle time
Typ.(1)
Max.
Unit
2
5
ms
tAS
Address setup time
0
ns
tAH
Address hold time
50
ns
tCS
Write setup time
0
ns
tCH
Write hold time
0
ns
tCW
CE pulse width
50
ns
tOES
OE High setup time
0
ns
tOEH
OE High hold time
0
ns
tWP
WE pulse width
50
ns
WE HIGH recovery
50
ns
tWPH
tDV
(6)
(6)
Data valid
1
µs
tDS
Data setup
tDH
Data hold
0
ns
Delay to next write
10
µs
tDW(6)
tBLC
50
Byte load cycle
ns
0.15
100
µs
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tDV
Data In
Data Valid
tDS
tDH
HIGH Z
Data Out
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(6) tWPH and tDW are periodically sampled and not 100% tested.
15
FN8109.1
June 7, 2006
X28HC64
CE CONTROLLED WRITE CYCLE
tWC
Address
tAS
tAH
tCW
CE
tOES
OE
tOEH
tCS
tCH
WE
tDV
Data Valid
Data In
tDS
tDH
HIGH Z
Data Out
Page Write Cycle
OE(7)
CE
tWP
tBLC
WE
tWPH
Address*(8)
Last Byte
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
Byte n+2
tWC
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH
to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a
polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
16
FN8109.1
June 7, 2006
X28HC64
DATA Polling Timing Diagram(9)
Address
An
An
An
CE
WE
tOEH
tOES
OE
tDW
I/O7
DIN = X
DOUT = X
DOUT = X
tWC
Toggle Bit Timing Diagram(9)
CE
WE
tOES
tOEH
OE
tDW
I/O*6
HIGH Z
*
*
tWC
* I/O6 beginning and ending state will vary, depending upon actual tWC.
Note:
(9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN8109.1
June 7, 2006
X28HC64
Printer Friendly Version
64K, 8K x 8 Bit; 5 Volt, Byte Alterable EEPROM
Datasheets,
Related Docs
& Simulations
Description
Key
Features
Parametric
Data
Ordering Information
Design-In
Status
Temp.
Package
Price
MSL US $
X28HC64D-12
Active
Comm
28 Ld CerDIP
N/A 13.06
X28HC64DI-12
Active
Ind
28 Ld CerDIP
N/A 13.61
X28HC64DM
Active
Mil
28 Ld CerDIP
N/A
X28HC64DM-12
Active
Mil
28 Ld CerDIP
N/A 9.24
X28HC64DM-15
Active
Mil
28 Ld CerDIP
N/A 8.84
X28HC64DMB-12
Active
Mil
28 Ld CerDIP
N/A
X28HC64EM-70
Active
Mil
32 Ld LCC
N/A
X28HC64FM-12
Active
Mil
28 Ld FlatPack
N/A
X28HC64J-12
Active
Comm
32 Ld PLCC
3
3.87
X28HC64J-12T1
Active
Comm 32 Ld PLCC T+R
3
3.87
X28HC64J-15T1
Active
Comm 32 Ld PLCC T+R
3
X28HC64J-70
Active
Comm
3
5.53
X28HC64J-70T1
Active
Comm 32 Ld PLCC T+R
3
5.53
X28HC64J-90
Active
Comm
3
5.22
X28HC64J-90T1
Active
Comm 32 Ld PLCC T+R
3
5.22
X28HC64JI-12
Active
Ind
32 Ld PLCC
3
4.17
X28HC64JI-12T1
Active
Ind
32 Ld PLCC T+R
3
4.17
X28HC64JI-12T2
Active
Ind
32 Ld PLCC T+R
3
4.17
X28HC64JI-15
Active
Ind
32 Ld PLCC
3
5.33
X28HC64JI-70
Active
Ind
32 Ld PLCC
3
4.72
X28HC64JI-70T1
Active
Ind
32 Ld PLCC T+R
3
4.72
X28HC64JI-90
Active
Ind
32 Ld PLCC
3
4.44
X28HC64JI-90T1
Active
Ind
32 Ld PLCC
3
4.44
X28HC64JI-90T2
Active
Ind
32 Ld PLCC T+R
3
4.44
X28HC64JIZ-12
Active
Ind
32 Ld PLCC
3
4.17
X28HC64JIZ-12T1
Active
Ind
32 Ld PLCC T+R
3
4.17
X28HC64JIZ-70
Active
Ind
32 Ld PLCC
3
4.72
X28HC64JIZ-70T1
Active
Ind
32 Ld PLCC T+R
3
4.72
X28HC64JIZ-90
Active
Ind
32 Ld PLCC
3
4.44
X28HC64JIZ-90T1
Active
Ind
32 Ld PLCC T+R
3
4.44
X28HC64JM-15
Active
Mil
32 Ld PLCC
3
X28HC64JZ-12
Active
Comm
32 Ld PLCC
3
3.87
X28HC64JZ-12T1
Active
Comm 32 Ld PLCC T+R
3
3.87
Part No.
32 Ld PLCC
32 Ld PLCC
Related
Devices
X28HC64JZ-15
Active
Comm
32 Ld PLCC
X28HC64JZ-15T1
Active
Comm 32 Ld PLCC T+R
3
X28HC64JZ-70
Active
Comm
3
5.53
X28HC64JZ-70T1
Active
Comm 32 Ld PLCC T+R
3
5.53
X28HC64KM-70
Active
Mil
28 Ld PGA
N/A
X28HC64KM-90
Active
Mil
28 Ld PGA
N/A
X28HC64KMB-12
Active
Mil
28 Ld PGA
N/A
X28HC64KMB-15
Active
Mil
28 Ld PGA
N/A 68.79
X28HC64KMB-90
Active
Mil
28 Ld PGA
N/A
X28HC64P-12
Active
Comm
28 Ld PDIP
N/A 2.28
X28HC64P-15
Active
Comm
28 Ld PDIP
N/A 4.73
X28HC64P-70
Active
Comm
28 Ld PDIP
N/A 5.76
X28HC64P-90
Active
Comm
28 Ld PDIP
N/A 5.00
X28HC64PI-12
Active
Ind
28 Ld PDIP
N/A 3.52
X28HC64PI-90
Active
Ind
28 Ld PDIP
N/A 5.60
X28HC64PIZ-12
Active
Ind
28 Ld PDIP
N/A 3.52
X28HC64PIZ-15
Active
Ind
28 Ld PDIP
N/A 3.50
X28HC64PIZ-90
Active
Ind
28 Ld PDIP
N/A 5.60
X28HC64PZ-12
Active
Comm
28 Ld PDIP
N/A 2.28
X28HC64PZ-15
Active
Comm
28 Ld PDIP
N/A 4.73
X28HC64PZ-90
Active
Comm
28 Ld PDIP
N/A 5.00
X28HC64S-12
Active
Comm
28 Ld SOIC
X28HC64S-12T1
Active
X28HC64S-12T2
32 Ld PLCC
3
5
4.56
Comm 28 Ld SOIC T+R
5
4.56
Active
Comm 28 Ld SOIC T+R
5
X28HC64S-12T4
Active
Comm 28 Ld SOIC T+R
5
X28HC64S-12T5
Active
Comm 28 Ld SOIC T+R
5
X28HC64S-15
Active
Comm
28 Ld SOIC
5
X28HC64S-70
Active
Comm
28 Ld SOIC
3
6.06
X28HC64S-70T1
Active
Comm 28 Ld SOIC T+R
3
6.06
X28HC64S-90
Active
Comm
3
5.39
X28HC64S-90T1
Active
Comm 28 Ld SOIC T+R
3
5.39
X28HC64SI-12
Active
Ind
28 Ld SOIC
5
4.89
X28HC64SI-12T1
Active
Ind
28 Ld SOIC T+R
5
4.89
X28HC64SI-12T2
Active
Ind
28 Ld SOIC T+R
5
4.89
X28HC64SI-15
Active
Ind
28 Ld SOIC
5
X28HC64SI-70
Active
Ind
28 Ld SOIC
3
6.57
X28HC64SI-70T1
Active
Ind
28 Ld SOIC T+R
5
6.57
X28HC64SIZ-12
Active
Ind
28 Ld SOIC
3
4.89
X28HC64SIZ-12T1
Active
Ind
28 Ld SOIC T+R
3
4.89
X28HC64SIZ-70
Active
Ind
28 Ld SOIC
3
6.57
X28HC64SM-70
Active
Mil
28 Ld SOIC
5
X28HC64SM-70T1
Active
Mil
28 Ld SOIC T+R
5
X28HC64SM-70T2
Active
Mil
28 Ld SOIC T+R
5
28 Ld SOIC
4.56
X28HC64SZ-12
Active
Comm
28 Ld SOIC
3
X28HC64SZ-70
Active
Comm
28 Ld SOIC
3
X28HC64W
Active
Comm
X28HC64PZ-70
X28HC64J-90C7871
Coming Soon Comm
InActive
Comm
4.56
N/A
28 Ld PDIP
N/A
32 Ld PLCC
3
The price listed is the manufacturer's suggested retail price for quantities between 100 and
999 units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
Description
The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s proprietary, high performance,
floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64
is a 5V only device. It features the JEDEC approved pinout for byte-wide memories, compatible with
industry standard RAMs.
The X28HC64 supports a 64-byte page write operation, effectively providing a 32ìs/byte write cycle,
and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features
DATA Polling and Toggle Bit Polling, two methods providing early end of write detection. In addition,
the X28HC64 includes a user-optional software data protection mode that further enhances
Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent
data retention is greater than 100 years.
Key Features
70ns access time
Simple byte and page write
Single 5V supply
No external high voltages or VPP control circuits
Self-timed
No erase before write
No complex programming algorithms
No overerase problem
Low power CMOS
40mA active current max.
200μA standby current max.
Fast write cycle times
64-byte page write operation
Byte or page write cycle: 2ms typical
Complete memory rewrite: 0.25 sec. typical
Effective byte write cycle time: 32μs typical
Software data protection
End of write detection
DATA polling
Toggle bit
High reliability
Endurance: 1 million cycles
Data retention: 100 years
JEDEC approved byte-wide pin out
Pb-free plus anneal available (RoHS compliant)
Related Documentation
Datasheet(s):
64K, 8K x 8 Bit; 5 Volt, Byte Alterable EEPROM
Technical Homepage:
Digital ICs
Parametric Data
Organization
Access Time (ns)
Active Current Max. (mA)
Standby Current Max. (μA)
8kx8-Bit
70
40
200
Related Devices
X28C010
5V, Byte Alterable E2PROM
X28C512
5V, Byte Alterable EEPROM
X28C513
5V, Byte Alterable EEPROM
X28HC256
256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM
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