X3100

NS E SI G W D CT NE ® FO R ODU D E D U TE PR EN TI T MM U BS EC O OT R SIBLE S ISL9208 Data Sheet N PO S X3100, X3101 4 Cell/3 Cell January 3, 2008 FN8110.1 3 or 4 Cell Li-ion Battery Protection and Monitor IC The X3100 is a protection and monitor IC for use in battery packs consisting of 4 series Lithium-Ion battery cells. The X3101 is designed to work in 3-cell applications. Both devices provide internal over-charge, over-discharge, and overcurrent protection circuitry, internal EEPROM memory, an internal voltage regulator, and internal drive circuitry for external FET devices that control cell charge, discharge, and cell voltage balancing. Over-charge, over-discharge, and over-current thresholds reside in an internal EEPROM memory register and are selected independently via software using a 3MHz SPI serial interface. Detection and time-out delays can also be individually varied using external capacitors. Using an internal analog multiplexer, the X3100 or X3101 allow battery parameters such as cell voltage and current (using a sense resistor) to be monitored externally by a separate microcontroller with A/D converter. Software on this microcontroller implements gas gauge and cell balancing functionality in software. The X3100 and X3101 contain a current sense amplifier. Selectable gains of 10, 25, 80 and 160 allow an external 10-bit A/D converter to achieve better resolution than a more expensive 14-bit converter. An internal 4k-bit EEPROM memory featuring IDLock™ allows the designer to partition and “lock in” written battery cell/pack data. The X3100 and X3101 are each housed in a 28 Ld TSSOP package. Features • Software Selectable Protection Levels and Variable Protect Detection/Release Times • Integrated FET Drive Circuitry • Cell Voltage and Current Monitoring • 0.5% Accurate Voltage Regulator • Integrated 4k-bit EEPROM • Flexible Power Management with 1µA Sleep Mode • Cell Balancing Control • Pb-Free Available (RoHS Compliant) Benefit • Optimize protection for chosen cells to allow maximum use of pack capacity • Reduce component count and cost • Simplify implementation of gas gauge • Accurate voltage and current measurements • Record battery history to optimize gas gauge, track pack failures and monitor system use • Reduce power to extend battery life • Increase battery capacity and improve cycle life battery life Functional Diagram VCC RGP RGC RGO UVP/OCP OVP/LMON AS0 AS1 AS2 AO VCELL1 CB1 VCELL2 CB2 VCELL3 CB3 VCELL4/VSS CB4 OVERCHARGE OVERDISCHARGE PROTECTION SENSE CIRCUITS PROTECTION SAMPLE RATE TIMER 5VDC REGULATOR INTERNAL VOLTAGE REGULATOR POWER-ON RESET AND STATUS REGISTER FET CONTROL CIRCUITRY ANALOGMUX 4k-BIT EEPROM CONTROL REGISTER S0 SPI I/F CS SI SCK OVERCURRENT PROTECTION AND CURRENT SENSE VSS VCS1 VCS2 PROTECTION CIRCUIT TIMING CONTROL AND CONFIGURATION OVT UVT OCT CONFIGURATION REGISTER 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X3100, X3101 Pinout X3100, X3101 (28 LD TSSOP) TOP VIEW VCELL1 1 CB1 2 VCELL2 3 CB2 4 VCELL3 5 CB3 6 VCELL4/VSS* 7 CB4 8 VSS 9 VCS1 10 VCS2 11 OVT 12 UVT 13 OCT 14 28 VCC 27 RGP 26 RGC 25 RGO 24 UVP/OCP 23 OVP/LMON 22 CS 21 SCK 20 SO 19 SI 18 AS2 17 AS1 16 AS0 15 AO *For X3101, Connect to GND Ordering Information PART NUMBER* X3100V28* X3100V28I X3100V28Z (Note) X3101V28* X3101V28Z (Note) PART MARKING X3100V X3100V I X3100VZ X3101V X3101VZ VCC LIMITS (V) 6 to 24 6 to 24 6 to 24 6 to 24 6 to 24 TEMP. RANGE (°C) -20 to +70 -20 to +70 -20 to +70 -20 to +70 -20 to +70 PACKAGE 28 Ld TSSOP 28 Ld TSSOP 28 Ld TSSOP (Pb-free) 28 Ld TSSOP 28 Ld TSSOP (Pb-free) PKG. DWG. # M28.173 M28.173 M28.173 M28.173 M28.173 **Add “-T1” or “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Descriptions PIN NUMBER PIN NAME 1 VCELL1 BRIEF DESCRIPTION Battery cell 1 voltage input. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. Cell balancing FET control output 1. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust an individual cell voltage (e.g. during cell charging). CB1 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Battery cell 2 voltage. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. 2 CB1 3 VCELL2 2 FN8110.1 January 3, 2008 X3100, X3101 Pin Descriptions (Continued) PIN NUMBER PIN NAME 4 CB2 BRIEF DESCRIPTION Cell balancing FET control output 2. These outputs are used to switch an external FETs in order to perform cell voltage balancing control. This function can be used to adjust individual cell voltages (e.g. during cell charging). CB2 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Battery cell 3 voltage. This pin is used to monitor the voltage of each battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. Cell balancing FET control output 3. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust an individual cell voltage (e.g. during cell charging). CB3 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. Battery cell 4 voltage (X3100) Ground (X3101). This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can also be monitored externally at pin AO. The X3100 monitors 4 battery cells. The X3101 monitors 3 battery cells. For the X3101 device connect the VCELL4/VSS pin to ground. Cell balancing FET control output 4. This output is used to switch an external FET in order to perform cell voltage balancing control. This function can be used to adjust individual cell voltages (e.g. during cell charging). CB4 can be driven high (Vcc) or low (Vss) to switch the external FET ON/OFF. When using the X3101, the CB4 pin can be left unconnected, or the FET control can be used for other purposes. Ground. Current sense voltage pin 1. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect against over-current conditions. The voltage at each end of RSENSE can also be monitored at pin AO. Current sense voltage pin 2. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect against over-current conditions. The voltage at each end of RSENSE can also be monitored at pin AO. Over-charge detect/release time input. This pin is used to control the delay time (TOV) associated with the detection of an over-charge condition (see section “Over-charge Protection” on page 14). Over-discharge detect/release time input. This pin is used to control the delay times associated with the detection (TUV) and release (TUVR) of an over-discharge (under-voltage) condition (see section “Over-discharge Protection” on page 16). Over-current detect/release time input. This pin is used to control the delay times associated with the detection (TOC) and release (TOCR) of an over-current condition (see section “Over-Current Protection” on page 19). Analog multiplexer output. The analog output pin is used to externally monitor various battery parameter voltages. The voltages which can be monitored at AO (see section “Analog Multiplexer Selection” on page 21) are: – Individual cell voltages – Voltage across the current sense resistor (RSENSE). This voltage is amplified with a gain set by the user in the control register (see section “Current Monitor Function” on page 21.) The analog select pins pins AS0 - AS2 select the desired voltage to be monitored on the AO pin. Analog output select pin 0. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control (SLP)” on page 11 and section “Current Monitor Function” on page 21) Analog output select pin 1. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control (SLP)” on page 11 and section “Current Monitor Function” on page 21) Analog output select pin 2. These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control (SLP)” on page 11 and section “Current Monitor Function” on page 21) Serial data input. SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input on this pin. Serial data output. SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state. Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3100 or X3101 is undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur. Serial data clock input. The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip select input pin. When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW enables the SPI serial bus. 5 VCELL3 6 CB3 7 VCELL4/ VSS 8 CB4 9 10 VSS VCS1 11 VCS2 12 13 14 15 OVT UVT OCT AO 16 17 18 19 20 AS0 AS1 AS2 SI SO 21 SCK 22 CS 3 FN8110.1 January 3, 2008 X3100, X3101 Pin Descriptions (Continued) PIN NUMBER PIN NAME 23 OVP/ LMON BRIEF DESCRIPTION Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the present mode of operation of the X3100 or X3101. Over-charge Voltage Protection (OVP) This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is possible when OVP/LMON=VSS, and cell charge is prohibited when OVP/LMO = VCC. In this configuration the X3100 and X3101 turn off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the application of charging voltage for an extended period of time (see section “Over-charge Protection” on page 14). Load Monitor (LMON) In Over-current Protection mode, a small test current (7.5µA typ.) is passed out of this pin to sense the load resistance. The measured load resistance determines whether or not the X3100 or X3101 returns from an over-current protection mode (see section “Over-Current Protection” on page 19). Over-discharge protection output/Over-current protection output. Pin UVP/OCP controls the battery cell discharge via an external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when UVP/OCP=Vcc. The X3100 and X3101 turn the external power FET off when the X3100 or X3101 detects either: Over-discharge Protection (UVP) In this case, pin 24 is referred to as “Over-discharge (Under-Voltage) protection (UVP)” (see section “Over-discharge Protection” on page 16). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to excessively low voltages. Over-current protection (OCP) In this case, pin 24 is referred to as “Over-current protection (OCP)” (see section “Over-Current Protection” on page 19). UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of a surge current resulting from a stalled disk drive). Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage at this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage for the device. Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on. Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an external current limit resistor and provides a current limit voltage. Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up circuits. 24 UVP/ OCP 25 RGO 26 27 28 RGC RGP VCC principles of operation The X3100 and X3101 provide two distinct levels of functionality and battery cell protection: First, in Normal mode, the device periodically checks each cell for an overcharge and overdischarge state, while continuously watching for a pack over-current condition. A protection mode violation results from an over-charge, overdischarge, or overcurrent state. The thresholds for these states are selected by the user through software. When one of these conditions occur, a Discharge FET or a Charge FET or both FETs are turned off to protect the battery pack. In an over-discharge condition, the X3100 and X3101 devices go into a low power sleep mode to conserve battery power. During sleep, the voltage regulator turns off, removing power from the microcontroller to further reduce pack current. Second, in Monitor mode, a microcontroller with A/D converter measures battery cell voltage and pack current via pin AO and the X3100 or X3101 on-board MUX. The user can thus implement protection, charge/discharge, cell balancing or gas gauge software algorithms to suit the specific application and characteristics of the cells used. While monitoring these voltages, all protection circuits are on continuously. In a typical application, the microcontroller is also programmed to provide an SMBus interface along with the Smart Battery System interface protocols. These additions allow an X3100 or X3101 based module to adhere to the latest industry battery pack standards. Typical Application Circuit The X3100 and X3101 have been designed to operate correctly when used as connected in the Typical Application Circuit (see Figure 1 on page 5). The power MOSFET’s Q1 and Q2 are referred to as the “Discharge FET” and “Charge FET,” respectively. Since these FETs are p-channel devices, they will be ON when the gates are at VSS, and OFF when the gates are at VCC. As their names imply, the discharge FET is used to control cell discharge, while the charge FET is used to control cell charge. Diode D1 allows the battery cells to receive charge even if the Discharge FET is OFF, while diode D2 allows the cells to discharge even if the charge FET is OFF. D1 and D2 are integral to the Power FETs. It should be noted that the cells can neither charge nor discharge if both the charge FET and discharge FET are OFF. 4 FN8110.1 January 3, 2008 X3100, X3101 Power to the X3100 or X3101 is applied to pin VCC via diodes D6 and D7. These diodes allow the device to be powered by the Li-Ion battery cells in normal operating conditions, and allow the device to be powered by an external source (such as a charger) via pin P+ when the battery cells are being charged. These diodes should have sufficient current and voltage ratings to handle both cases of battery cell charge and discharge. The operation of the voltage regulator is described in section “Voltage Regulator” on page 22. This regulator provides a 5VDC±0.5% output. The capacitor (C1) connected from RGO to ground provides some noise filtering on the RGO output. The recommended value is 0.1µF or less. The value chosen must allow VRGO to decay to 0.1V in 170ms or less when the X3100 or X3101 enter the sleep mode. If the decay is slower than this, a resistor (R1) can be placed in parallel with the capacitor. During an initial turn-on period (TPUR + TOC), VRGO has a stable, regulated output in the range of 5VDC ± 10% (see Figure ). The selection of the microcontroller should take this into consideration. At the end of this turn on period, the X3100 and X3101 “self-tunes” the output of the voltage regulator to 5V+/-0.5%. As such, VRGO can be used as a reference voltage for the A/D converter in the microcontroller. Repeated power-up operations, consistently re-apply the same “tuned” value for VRGO. Figure 1 shows a battery pack temperature sensor implemented as a simple resistive voltage divider, utilizing a thermistor (RT) and resistor (RT’). The voltage VT can be fed to the A/D input of a microcontroller and used to measure and monitor the temperature of the battery cells. RT’ should be chosen with consideration of the dynamic resistance range of RT as well as the input voltage range of the microcontroller A/D input. An output of the microcontroller can be used to turn on the thermistor divider to allow periodic turn-on of the sensor. This reduces power consumption since the resistor string is not always drawing current. Diode D3 is included to facilitate load monitoring in an Overcurrent protection mode (see section “Over-Current Protection” on page 19), while preventing the flow of current into pin OVP/LMON during normal operation. The NChannel transistor turns off this function during the sleep mode. Resistor RPU is connected across the gate and drain of the charge FET (Q2). The discharge FET Q1 is turned off by the X3100 or X3101, and hence the voltage at pin OVP/LMON will be (at maximum) equal to the voltage of the battery terminal, minus one forward biased diode voltage drop (VP+ VD7). Since the drain of Q2 is connected to a higher potential (VP+) a pull-up resistor (RPU) in the order of 1MΩ should be used to ensure that the charge FET is completely turned OFF when OVP/LMON = VCC. The capacitors on the VCELL1 to VCELL4 inputs are used in a first order low pass filter configuration, at the battery cell voltage monitoring inputs (VCELL1 - VCELL4) of the X3100 or X3101. This filter is used to block any unwanted interference signals from being inadvertently injected into the monitor inputs. These interference signals may result from: • Transients created at battery contacts when the battery pack is being connected/disconnected from the charger or the host. • Electrostatic discharge (ESD) from something/someone touching the battery contacts. • Unfiltered noise that exists in the host device. • RF signals which are induced into the battery pack from the surrounding environment. Such interference can cause the X3100 or X3101 to operate in an unpredictable manner, or in extreme cases, damage the device. As a guide, the capacitor should be in the order of 0.01µF and the resistor, should be in the order of 10kΩ. The capacitors should be of the ceramic type. In order to minimize interference, PCB tracks should be made as short and as wide as possible to reduce their impedance. The battery cells should also be placed as close to the X3100 or X3101 monitor inputs as possible. Resistors RCB and the associated n-channel MOSFET’s (Q6 Q9) are used for battery cell voltage balancing. The X3100 and X3101 provide internal drive circuitry which allows the user to switch FETs Q6 - Q9 ON or OFF via the microcontroller and SPI port (see section “Cell Voltage Balance Control (CBC1-CBC4)” on page 12). When any of the these FETs are switched ON, a current, limited by resistor RCB, flows across the particular battery cell. In doing so, the user can control the voltage across each individual battery cell. This is important when using Li-Ion battery cells since imbalances in cell voltages can, in time, greatly reduce the usable capacity of the battery pack. Cell voltage balancing may be implemented in various ways, but is usually performed towards the end of cell charging (“Top-ofcharge method”). Values for RCB will vary according to the specific application. The internal 4kbit EEPROM memory can be used to store the cell characteristics for implementing such functions as gas gauging, battery pack history, charge/discharge cycles, and minimum/maximum conditions. Battery pack manufacturing data as well as serial number information can also be stored in the EEPROM array. An SPI serial bus provides the communication link to the EEPROM. A current sense resistor (RSENSE) is used to measure and monitor the current flowing into/out of the battery terminals, and is used to protect the pack from over-current conditions (see section “Over-Current Protection” on page 19). RSENSE is also used to externally monitor current via a 5 FN8110.1 January 3, 2008 X3100, X3101 microcontroller (see section “Current Monitor Function” on page 21). FETs Q4 and Q5 may be required on general purpose I/Os of the microcontroller that connect outside of the package. In some cases, without FETs, pull-up resistors external to the pack force a voltage on the VCC pin of the microcontroller during a pack sleep condition. This voltage can affect the proper tuned voltage of the X3100/X3101 regulator. These FETs should be turned-on by the microcontroller. (See Figure 1.) Power-on Sequence Initial connection of the Li-Ion cells in the battery pack will not normally power-up the battery pack. Instead, the X3100 or X3101 enters and remains in the SLEEP mode. To exit the SLEEP mode, after the initial power-up sequence, or following any other SLEEP MODE, a minimum of 16V (X3100 VSLR) or 12V (X3101 VSLR) is applied to the VCC pin, as would be the case during a battery charge condition. (See Figure .) When VSLR is applied to VCC, the analog select pins (AS2 AS0) and the SPI communication pins (CS, CLK, SI, SO) must be low, so the X3100 and X3101 power-up correctly into the normal operating mode. This can be done by using a power-on reset circuit. When entering the normal operating mode, either from initial power-up or following the SLEEP MODE, all bits in the control register are zero. With UVPC and OVPC bits at zero, the charge and discharge FETs are off. The microcontroller must turn these on to activate the pack. The microcontroller would typically check the voltage and current levels prior to turning on the FETs via the SPI port. The software should prevent turning on the FETs throughout an initial measurement/calibration period. The duration of this period is TOV + 200ms or TUV + 200ms, whichever is longer. 6 FN8110.1 January 3, 2008 D6 BAT54 D1 CHARGE FET P+ ILMON RPU 1M D7 BAT54 D2 Q1 DISCHARGE FET D3 Transistor Recommendations Q1, Q2 = Si4435 Q3 = 2N3906 Q4 - Q10 = 2N7002 Q2 Typical Application Circuit 7 Q10 ILMT . 1µF 28 VCC 1 VCELL1 0.01µF 2 CB1 VCELL2 22 X3100/X3101 CB2 SO SI VCELL3 0.01µF 6 CB3 7 VCELL4/VSS 0.01µF 8 CB4 AO VT VSS 9 10 11 COV RSENSE VCS1 VCS2 OVT 12 CUV UVT 13 COC OCT RT 14 15 A/D INPUT A/D INPUT 20 19 GP I/O 18 AS2 AS1 AS0 17 16 CS SCK 21 0.01µF 4 5 3 RGP UVP/ OCP RGC OVP/ LMON RGO 27 26 25 24 23 RLMT C1 0.1µF R1 1M (Optional) VCC A/D REF GP I/O RT’ GP I/O RESET Q3 VRGO µC, ASIC Choose R1 and C1 such that VRGO goes to 0.1V (or less) in 170ms (or less) when entering the Sleep Mode (at +25oC). 3 OR 4 Li-ion cells† B+ RPOR RCB 100 CPOR Q6 Set High after poweruppowerdown to enable X3100, X3101 100 RCB Q7 100 Q4 Q5 SMBCLK RCB Q8 100 100 SMBDATA RCB 100 Q9 B- For the X3101, or X3100 when 3 cells are used, VCELL4/VSS MUST be tied to Ground (Vss). CB4 is left unconnected. FETs Q4 and Q5 are needed only if external pull-ups on the SMBus lines cause voltage to appear at the uC Vcc pin during sleep mode. P- FN8110.1 January 3, 2008 X3100, X3101 Power-up Timing (Initial Power-up or after Sleep Mode) TPUR VCC VSLR 0V 5V ±10% (STABLE AND REPEATABLE) VRGO TUNED TO 5V ±0.5% 5V VRGO 0V 2ms (Typ.) VOLTAGE REGULATOR OUTPUT STATUS (INTERNAL SIGNAL) VRGS TOC 1 OVERCURRENT DETECTION STATUS (INTERNAL SIGNAL) OCDS 1 0 1 = X3100/1 in Overcurrent Protection Mode 0 = X3100/1 NOT in Overcurrent Protection Mode 0 1 1 = X3100/1 in Overcurrent Protection Mode OR VRGO Not Yet Tuned 0 = X3100/1 NOT in Overcurrent Protection Mode AND VRGO Tuned 0 TOV+200ms 1 STATUS REGISTER BIT 0 VRGS+OCDS STATUS REGISTER BIT 2 (SWCEN = 0) CCES+OVDS 1 = VCELL < VCE OR X3100/1 in Overcharge Protection Mode 0 = VCELL > VCE OR X3100/1 NOT in Overcharge Protection Mode 1 STATUS REGISTER BIT 2 (SWCEN = 1) OVDS 1 = X3100/1 in Overcharge Protection Mode 0 = X3100/1 NOT in Overcharge Protection Mode 0 0 MICROCONTROLLER AS2_AS0 TOV + 200ms OR TUV + 200ms (WHICHEVER IS LONGER) FROM SPI PORT Any Read or Write Operation, except turn-on of FETs can start here. Charge, Discharge FETs can be turned on here. 8 FN8110.1 January 3, 2008 X3100, X3101 Configuration Register The X3100 and X3101 can be configured for specific user requirements using the Configuration Register. TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY BIT(s) 0 to 5 6 7 8 to 9 10 to11 12 to 13 14 to 15 NAME – SWCEN CELLN VCE1-VCE0 VOC1-VOC0 VUV1-VUV0 VOV1-VOV0 (don’t care) Switch Cell Charge Enable threshold function ON/OFF Set the number of Li-ion battery cells used (3 or 4) Select Cell Charge Enable threshold Select overcurrent threshold Select overdischarge (under voltage) threshold Select overcharge voltage threshold FUNCTION Overdischarge Settings VUV1 and VUV0 control the cell over-discharge (under voltage threshold) level. See section “Over-discharge Protection” on page 16. TABLE 5. OVERDISCHARGE THRESHOLD SELECTION. CONFIGURATION REGISTER BITS VUV1 0 0 1 1 VUV0 0 1 0 1 X3100 VUV = 1.95V VUV = 2.05V VUV = 2.15V VUV = 2.25V (X3100 default) OPERATION X3101 VUV = 2.25V (X3101 default) VUV = 2.35V VUV = 2.45V VUV = 2.55V Overcurrent Settings VOC1 and VOC0 control the pack over-current level. See section “Over-Current Protection” on page 19. TABLE 6. OVERCURRENT THRESHOLD VOLTAGE SELECTION CONFIGURATION REGISTER BITS VOC1 0 VOC0 0 1 0 1 OPERATION VOC = 0.075V (Default) VOC = 0.100V VOC = 0.125V VOC = 0.150V TABLE 2. CONFIGURATION REGISTER—UPPER BYTE 15 VOV1 14 VOV0 13 VUV1 12 VUV0 11 VOC1 10 VOC0 9 VCE1 8 VCE0 X3100 Default = 33H; X3101 Default = 03H. TABLE 3. CONFIGURATION REGISTER—LOWER BYTE 7 CELLN 6 SWCEN 5 x 4 x 3 x 2 x 1 x 0 x 0 1 1 X3100 Default = C0H; X3101 Default = 40H. Overcharge Voltage Settings VOV1 and VOV0 control the cell over-charge level. See section “Over-charge Protection” on page 14. TABLE 4. OVERCHARGE VOLTAGE THRESHOLD SELECTION CONFIGURATION REGISTER BITS Cell Charge Enable Settings VCE1, VCE0 and SWCEN control the pack charge enable function. SWCEN enables or disables a circuit that prevents charging if the cells are at too low a voltage. VCE1 and VCE0 select the voltage that is recognized as too low. See section “Sleep Mode” on page 16. TABLE 7. CELL CHARGE ENABLE FUNCTION CONFIGURATION REGISTER BITS SWCEN 0 1 OPERATION Charge enable function: ON Charge enable function: OFF VOV1 0 0 1 1 VOV0 0 1 0 1 OPERATION (V) VOV = 4.20 (Default) VOV = 4.25 VOV = 4.30 VOV = 4.35 TABLE 8. CELL CHARGING THRESHOLD VOLTAGE SELECTION CONFIGURATION REGISTER BITS VCE1 0 0 1 1 VCE0 0 1 0 1 OPERATION VCE = 0.5V VCE = 0.80V VCE = 1.10V VCE = 1.40V (Default) 9 FN8110.1 January 3, 2008 X3100, X3101 Cell Number Selection The X3100 is designed to operate with four (4) Li-Ion battery cells. The X3101 is designed to operate with three (3) Li-ion battery cells. The CELLN bit of the configuration register (Table 9) sets the number of cells recognized. For the X3101, the value for CELLN should always be zero. Figure 1. Power-up of Configuration Register Configuration Register (SRAM) Upper Byte Recall Lower Byte Recall Shadow EEPROM Table 9. Selection of Number of Battery Cells1 Configuration Register Bit CELLN 1 0 Operation 4 Li-Ion battery cells (X3100 default) 3 Li-Ion battery cells (X3100 or X3101) The configuration register is designed for unlimited write operations to SRAM, and a minimum of 1,000,000 store operations to the EEPROM. Data retention is specified to be greater than 100 years. It should be noted that the bits of the shadow EEPROM are for the dedicated use of the configuration register, and are NOT part of the general purpose 4kbit EEPROM array. The WCFIG command writes to the configuration reg- The configuration register consists of 16 bits of NOVRAM memory (Table 2, Table 3). This memory features a high-speed static RAM (SRAM) overlaid bitfor-bit with non-volatile “Shadow” EEPROM. An automatic array recall operation reloads the contents of the shadow EEPROM into the SRAM configuration register upon power-up (Figure 1). ister, see Table 30 and section “X3100/X3101 SPI Serial Communication” on page 23. After writing to this register using a WCFIG instruction, data will be stored only in the SRAM of the configuration register. In order to store data in shadow EEPROM, a WREN instruction, followed by a EEWRITE to any address of the 4kbit EEPROM memory array must occur, see Figure 2. This sequence initiates an internal nonvolatile write cycle which permits data to be stored in the shadow EEPROM cells. It must be noted that even though a EEWRITE is made to the general purpose 4kbit EEPROM array, the value and address to which it is written, is unimportant. If this procedure is not followed, the configuration register will power-up to the last previously stored values following a power-down sequence. 1. In the case that the X3100 or X3101 is configured for use with only three Li-Ion battery cells (i.e. CELLN = 0), then VCELL4 (pin 7) MUST be tied to Vss (pin 9) to ensure correct operation. 10 FN8110.1 January 3, 2008 X3100, X3101 Figure 2. Writing to Configuration Register Power-up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM = Old Value) WCFIG (New Value) Configuration Register (Sram = New Value) Since the control register is volatile, data will be lost following a power-down and power-up sequence. The default value of the control register on initial power-up or when exiting the SLEEP MODE is 00h (for both upper and lower bytes respectively). The functions that can be manipulated by the Control Register are shown in Table 12. Table 12. Control Register Functionality Bit(s) Name 0-4 5,6 7 – 0, 0 SLP (don’t care) Reserved—write 0 to these locations. Select sleep mode. Function NO Store (New Value) in Shadow EEPROM YES 8,9 10 CSG1, Select current sense voltage gain CSG0 OVPC OVP control: switch pin OVP = VCC/VSS UVPC CBC1 CBC2 CBC3 CBC4 UVP control: switch pin UVP = VCC/VSS CB1 control: switch pin CB1 = VCC/VSS CB2 control: switch pin CB2 = VCC/VSS CB3 control: switch pin CB3 = VCC/VSS CB4 control: switch pin CB4 = VCC/VSS WREN Power-downpower-on Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM = old value) Power-down Power-up Data Recalled from Shadow EEPROM to SRAM Configuration Register (SRAM = New Value) Write Enable EEWRITE Write to 4kbit EEPROM 11 12 13 14 15 Sleep Control (SLP) Setting the SLP bit to ‘1’ forces the X3100 or X3101 into the sleep mode, if VCC < VSLP. See section “Sleep Mode” on page 16. Table 13. Sleep Mode Selection Control Register Bits SLP Operation Normal operation mode Device enters Sleep mode 0 1 CONTROL REGISTER The Control Register is realized as two bytes of volatile RAM (Table 10, Table 11). This register is written using the WCNTR instruction, see Table 30 and section “X3100/X3101 SPI Serial Communication” on page 23. Table 10. Control Register—Upper Byte 15 CBC4 14 CBC3 13 CBC2 12 CBC1 11 UVPC 10 OVPC 9 CSG1 8 CSG0 Table 11. Control Register—Lower Byte 7 6 5 4 3 2 1 0 SLP 0 0 x x x x x 11 FN8110.1 January 3, 2008 X3100, X3101 Current Sense Gain (CSG1, CSG0) These bits set the gain of the current sense amplifier. These are x10, x25, x80 and x160. For more detail, see section “Current Monitor Function” on page 21. Table 14. Current Sense Gain Control Control Register Bits CSG1 0 0 1 1 Table 16. CB1—CB4 Control Control Register Bits CBC4 CBC3 CBC2 CBC1 x x x x x x 1 0 x x x x 1 0 x x x x 1 0 x x x x 1 0 x x x x x x Operation Set CB1 = VCC (ON) Set CB1=VSS (OFF) Set CB2 = VCC (ON) Set CB2 = VSS (OFF) Set CB3 = VCC (ON) Set CB3 = VSS (OFF) Set CB4 = VCC (ON) Set CB4 = VSS (OFF) CSG0 0 1 0 1 Operation Set current sense gain = x10 Set current sense gain = x25 Set current sense gain = x80 Set current sense gain = x160 Charge/Discharge Control (OVPC, UVPC) The OVPC and UVPC bits allow control of cell charge and discharge externally, via the SPI port. These bits control the OVP/LMON and UVP/OCP pins, which in turn control the external power FETs. Using P-channel power FETs ensures that the FET is on when the pin voltage is low (Vss), and off when the pin voltage is high (Vcc). OVP/LMON and UVP/OCP can be controlled by using the WCNTR Instruction to set bits OVPC and UVPC in the Control register (See page 11). Table 15. UVP/OVP Control Control Register Bits OVPC 1 0 x x CB1 - CB4 can be controlled by using the WCNTR Instruction to set bits CBC1 - CBC4 in the control register (Table 16). STATUS REGISTER The status of the X3100 or X3101 can be verified by using the RDSTAT command to read the contents of the Status Register (Table 17). Table 17. Status Register. 7 0 6 0 5 0 4 0 3 0 2 CCES+ OVDS 1 UVDS 0 VRGS+ OCDS UVPC x x 1 0 Operation Pin OVP = VSS (FET ON) Pin OVP = VCC (FET OFF) Pin UVP = VSS (FET ON) Pin UVP = VCC (FET OFF) The function of each bit in the status register is shown in Table 18. Bit 0 of the status register (VRGS+OCDS) actually indicates the status of two conditions of the X3100 or X3101. Voltage Regulator Status (VRGS) is an internally generated signal which indicates that the output of the Voltage Regulator (VRGO) has reached an output of 5VDC ± 0.5%. In this case, the voltage regulator is said to be “tuned”. Before the signal VRGS goes low (i.e. before the voltage regulator is tuned), the voltage at the output of the regulator is nominally 5VDC ± 10% (See section “Voltage Regulator” on page 22.) Overcurrent Detection Status (OCDS) is another internally generated signal which indicates whether or not the X3100 or X3101 is in over-current protection mode. Signals VRGS and OCDS are logically OR’ed together (VRGS + OCDS) and written to bit 0 of the status register (See Table 18, Table 17 and Figure ). It is possible to set/change the values of OVPC and UVPC during a protection mode. A change in the state of the pins OVP/LMON and UVP/OCP, however, will not take place until the device has returned from the protection mode. Cell Voltage Balance Control (CBC1-CBC4) This function can be used to adjust individual battery cell voltage during charging. Pins CB1 - CB4 are used to control external power switching devices. Cell voltage balancing is achieved via the SPI port. 12 FN8110.1 January 3, 2008 X3100, X3101 Bit 1 of the status register simply indicates whether or not the X3100 or X3101 is in over-discharge protection mode. Bit 2 of the status register (CCES+OVDS) indicates the status of two conditions of the X3100 or X3101. Cell Charge Enable Status (CCES) is an internally generated signal which indicates the status of any cell voltage (VCELL) with respect to the Cell Charge Enable Voltage (VCE). Over-charge Voltage Detection Status (OVDS) is an internally generated signal which indicates whether or not the X3100 or X3101 is in overcharge protection mode. Table 18. Status Register Functionality. Bit(s) 0 When the cell charge enable function is switched ON (configuration bit SWCEN=0), the signals CCES and OVDS are logically OR’ed (CCES+OVDS) and written to bit 2 of the status register. If the cell charge enable function is switched OFF (configuration bit SWCEN=1), then bit 2 of the status register effectively only represents information about the over-charge status (OVDS) of the X3100 or X3101 (See Table 18, Table 17 and Figure ). Name Description Case - Status 1 0 Interpretation VRGO not yet tuned (VRGO = 5V ± 10%) OR X3100/X3101 in over-current protection mode. VRGO tuned (VRGO = 5V ± 0.5%) AND X3100/X3101 NOT in over-current protection mode. X3100/X3101 in over-discharge protection mode X3100/X3101 NOT in over-discharge protection mode VCELL < VCE OR X3100/X3101 in over-charge protection mode VCELL > VCE AND X3100/X3101 NOT in over-charge protection mode X3100/X3101 in over-charge protection mode X3100/X3101 NOT in over-charge protection mode Not used (always return zero) VRGS+OCDS Voltage regulator status + Over-current detection status UVDS CCES+OVDS Over-discharge detection status Cell charge enable status + Over-charge detection status 1 2 SWCEN =0† 1 0 1 0 SWCEN =1† - 1 0 0 3-7 - Notes: † This bit is set in the configuration register. X3100/X3101 INTERNAL PROTECTION FUNCTIONS The X3100 and the X3101 provide periodic monitoring (see section “Periodic Protection Monitoring” on page 13) for over-charge and over-discharge states and continuous monitoring for an over-current state. It has automatic shutdown when a protection mode is encountered, as well as automatic return after the device is released from a protection mode. When sampling voltages through the analog port (Monitor Mode), over-charge and over-discharge protection monitoring is also performed on a continuous basis. Voltage thresholds for each of these protection modes (VOV, VUV, and VOC respectively) can be individually selected via software and stored in an internal non-volatile register. This feature allows the user to avoid the restrictions of mask programmed voltage thresholds, and is especially useful during prototype/evaluation design stages or when cells with slightly different characteristics are used in an existing design. 13 Delay times for the detection of, and release from protection modes (TOV, TUV/TUVR, and TOC/TOCR respectively) can be individually varied by setting the values of external capacitors connected to pins OVT, UVT, OCT. Periodic Protection Monitoring In normal operation, the analog select pins are set such that AS2 = L, AS1 = L, AS0 = L. In this mode the X3100 and X3101 conserve power by sampling the cells for over or over-discharge conditions. In this state over-charge and over-discharge protection circuitry are usually off, but are periodically switched on by the internal Protection Sample Rate Timer (PSRT). The over-charge and over-discharge protection circuitry is on for approximately 2ms in each 125ms period. Over-current monitoring is continuous. In monitor mode (see page 21) over-charge and overdischarge monitoring is also continuous. FN8110.1 January 3, 2008 X3100, X3101 Over-charge Protection The X3100 and X3101 monitor the voltage on each battery cell (VCELL). If for any cell, VCELL > VOV for a time exceeding TOV, then the Charge FET will be switched OFF (OVP/LMON = VCC). The device has now entered Over-charge protection mode (Figure 3). The status of the discharge FET (via pin UVP) will remain unaffected. While in over-charge protection mode, it is possible to change the state of the OVPC bit in the control register such that OVP/LMON = Vss (Charge FET = ON). Although the OVPC bit in the control register can be changed, the change will not be seen at pin OVP until the X3100 or X3101 returns from over-charge protection mode. The over-charge detection delay TOV, is varied using a capacitor (COV) connected between pin OVT and GND. A typical delay time is shown in Table 10. The delay TOV that results from a particular capacitance COV, can be approximated by the following linear equation: TOV (s) ≈ 10 x COV (µF). Table 19. Typical over-charge detection time Symbol TOV COV 0.1µF Delay 1.0s (Typ) The device further continues to monitor the battery cell voltages, and is released from over-charge protection mode when VCELL< VOVR, for all cells. When the X3100 or X3101 is released from over-charge protection mode, the charge FET is automatically switched ON (OVP/LMON = VSS). When the device returns from over-charge protection mode, the status of the discharge FET (pin UVP/OCP) remains unaffected. The value of VOV can be selected from the values shown in Table 4 by setting bits VOV1, VOV0. These bits are set by using the WCFIG instruction to write to the configuration register. Figure 3. Over-charge Protection Mode—Event Diagram Normal Operation Mode Over-charge Protection Mode Normal Operation Mode VOV VOVR VCELL TOV VCC OVP/LMON VSS Event 0 1 2 3 14 FN8110.1 January 3, 2008 X3100, X3101 Table 20. Over-charge Protection Mode—Event Diagram Description Event [0,1) Event Description — Discharge FET is ON (UVP/OCP = VSS). — Charge FET is ON (OVP/LMON = VSS), and hence battery cells are permitted to receive charge. — All cell voltages (VCELL - VCELL4) are below the over-charge voltage threshold (VOV). — The device is in normal operation mode (i.e. not in a protection mode). — The voltage of one or more of the battery cells (VCELL), exceeds VOV. — The internal over-charge detection delay timer begins counting down. — The device is still in normal operation mode The internal over-charge detection delay timer continues counting for TOV seconds. The internal over-charge detection delay timer times out AND VCELL still exceeds VOV. — Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc). — The device has now entered over-charge protection mode. [1] (1,2) [2] (2,3) While in over-charge protection mode: — The battery cells are permitted to discharge via the discharge FET, and diode D2 across the charge FET — The X3100 or X3101 monitors the voltages VCELL1 - VCELL4 to determine whether or not they have all fallen below the “Return from over-charge threshold” (VOVR). — (It is possible to change the status of UVP/OCP or OVP/LMON using the control register) — All cell voltages fall below VOVR—The device is now in normal operation mode. — The X3100/X3101 automatically switches charge FET = ON (OVP/LMON = Vss) — The status of the discharge FET remains unaffected. — Charging of the battery cells can now resume. [3] 15 FN8110.1 January 3, 2008 X3100, X3101 Over-discharge Protection If VCELL < VUV, for a time exceeding TUV, the cells are said to be in a over-discharge state (Figure 4). In this instance, the X3100 and X3101 automatically switch the discharge FET OFF (UVP/OCP = Vcc), and then enter sleep mode. The over-discharge (under-voltage) value, VUV, can be selected from the values shown in Table 5 by setting bits VUV1, VUV0 in the configuration register. These bits are set using the WCFIG command. Once in the sleep mode, the following steps must occur before the X3100 or X3101 allows the battery cells to discharge: – The X3100 and X3101 must wake from sleep mode (see section “Voltage Regulator” on page 22). – The charge FET must be switched ON by the microcontroller (OVP/LMON=VSS), via the control register (see section “Control Register Functionality” on page 11). – All battery cells must satisfy the condition: VCELL > VUVR for a time exceeding TUVR. – The discharge FET must be switched ON by the microcontroller (UVP/OCP=VSS), via the control register (see section “Control Register Functionality” on page 11) The times TUV/TUVR are varied using a capacitor (CUV) connected between pin UVT and GND (Table 13). The delay TUV that results from a particular capacitance CUV, can be approximated by the following linear equation: TUV (s) ≈ 10 x CUV (µF) TUVR (ms) ≈ 70 x CUV (µF) Table 21. Typical Over-discharge Delay Times Symbol TUV TUVR A sleep mode can be induced by the user, by setting the SLP bit in the control register (Table 13) using the WCNTR Instruction. In sleep mode, power to all internal circuitry is switched off, minimizing the current drawn by the device to 1µA (max). In this state, the discharge FET and the charge FET are switched OFF (OVP/LMON=VCC and UVP/OCP=VCC), and the 5VDC regulated output (VRGO) is 0V. Control of UVP/OCP and OVP/LMON via bits UVPC and OVPC in the control register is also prohibited. The device returns from sleep mode when VCC ≥ VSLR. (e.g. when the battery terminals are connected to a battery charger). In this case, the X3100 or the X3101 restores the 5VDC regulated output (section “Voltage Regulator” on page 22), and communication via the SPI port resumes. If the Cell Charge Enable function is enabled when VCC rises above VSLR, the X3100 and X3101 internally verifies that the individual battery cell voltages (VCELL) are larger than the cell charge enable voltage (VCE) before allowing the FETs to be turned on. The value of VCE is selected by using the WCFIG command to set bits VCE1–VCE0 in the configuration register. Only if the condition “VCELL > VCE” is satisfied can the state of charge and discharge FETs be changed via the control register. Otherwise, if VCELL < VCE for any battery cell then both the Charge FET and the discharge FET are OFF (OVP/LMON=Vcc and UVP/OCP=VCC). Thus both charge and discharge of the battery cells via terminals P+ / P- is prohibited1. Description Over-discharge detection delay Over-discharge release time CUV 0.1µF 0.1µF Delay 1.0s (Typ) 7ms (Typ) The cell charging threshold function can be switched ON or OFF by the user, by setting bit SWCEN in the configuration register (Table 7) using the WCFIG command. In the case that this cell charge enable function is switched OFF, then VCE is effectively set to 0V. Neither the X3100 nor the X3101 enter sleep mode (automatically or manually, by setting the SLP bit) if VCC ≥ VSLR. This is to ensure that the device does not go into a sleep mode while the battery cells are at a high voltage (e.g. during cell charging). Sleep Mode The X3100 or X3101 can enter sleep mode in two ways: i) The device enters the over-discharge protection mode. ii) The user sends the device into sleep mode using the control register. 1. In this case, charging of the battery may resume ONLY if the cell charge enable function is switched OFF by setting bit SWCEN = 1 in the configuration register (See Above, “CONFIGURATION REGISTER FUNCTIONALITY” on page 9). 16 FN8110.1 January 3, 2008 X3100, X3101 Figure 4. Over-discharge Protection Mode—Event Diagram VSLR Cell Charge Prohibited if SWCEN=0 AND VCELL < VCE VCELL 0.7V VUV TUVR VCE TUV Over-discharge Protection Mode The Longer of TOV+200ms OR TUV+200ms VCC VUVR VCC Note 3 VSS VCC UVP/OCP OVP/LMON RGO Note 1, 2 Sleep Mode VSS 5V 0V Event 0 1 2 3 4 5 Note 1: If SWEN = 0 and VCELL < VCE, then OVP/LMON stays high and charging is prohibited. Note 2: OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned on prior to this time. Note 3: UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the discharge FET. The FET cannot be turned on prior to this time. Table 22. Over-discharge Protection Mode—Event Diagram Description Event [0,1) Event Description — Charge FET is ON (OVP/LMON = VSS) — Discharge FET is ON (UVP/OCP = VSS), and hence battery cells are permitted to discharge. — All cell voltages (VCELL1 - VCELL4) are above the Over-discharge threshold voltage (VUV). — The device is in normal operation mode (i.e. not in a protection mode). — The voltage of one or more of the battery cells (VCELL), falls below VUV. — The internal over-discharge detection delay timer begins counting down. — The device is still in normal operation mode The internal over-discharge detection delay timer continues counting for TUV seconds. — The internal over-discharge detection delay timer times out, AND VCELL is still below VUV. — The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc). — The charge FET is switched OFF (OVP/LMON = VCC). — The device has now entered over-discharge protection mode. — At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 22). While device is in sleep (in over-discharge protection) mode: — The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA. — The output of the 5VDC voltage regulator (RGO) is 0V. — Access to the X3100/X3101 via the SPI port is NOT possible. [1] (1,2) [2] (2,3) 17 FN8110.1 January 3, 2008 X3100, X3101 Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued) Event [3] Event Description Return from sleep mode (but still in over-discharge protection mode): — Vcc rises above the “Return from Sleep mode threshold Voltage” (VSLR)—This would normally occur in the case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and not the battery pack cells. — Power is returned to ALL internal circuitry — 5VDC output is returned to the regulator output (RGO). — Access is enabled to the X3100/X3101 via the SPI port. — The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will have no effect at this time). If the cell charge enable function is switched ON AND VCELL > VCE OR Charge enable function is switched OFF — The X3100/X3101 initiates a reset operation that takes the longer of TOV + 200ms or TUV + 200ms to complete. Do not write to the FET control bits during this time. — The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by writing a “1” to the OVPC bit in the control register. — The battery cells now receive charge via the charge FET and diode D1 across the discharge FET (which is OFF). — The X3100/X3101 monitors the VCELL voltage to determine whether or not it has risen above VUVR. — Charge/discharge of the battery cells via P+ is no longer permitted (Charge FET and discharge FET are held OFF). — (Charging may re-commence only when the Cell Charge Enable function is switched OFF - See Sections: “Configuration Register” page 4, and “Sleep mode” page 17.) (3,4) If the cell charge enable function is switched ON AND VCELL < VCE [4] — The voltage of all of the battery cells (VCELL), have risen above VUVR. — The internal Over-discharge release timer begins counting down. — The X3100/X3101 is still in over-discharge protection mode. — The internal over-discharge release timer continues counting for tUVR seconds. — The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on tUVR. Otherwise recovery is based on two successive samples about 120ms apart. — The internal over-discharge release timer times out, AND VCELL is still above VUVR. — The device returns from over-discharge protection mode, and is now in normal operation mode. — The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep. — The discharge FET is can now be switched ON (UVP/OCP = VSS) by the microcontroller by writing a “1” to the UVPC bit of the control register. — The status of the charge FET remains unaffected (ON) — The battery cells continue to receive charge via the charge FET and discharge FET (both ON). (4,5) [5] 18 FN8110.1 January 3, 2008 X3100, X3101 Over-Current Protection In addition to monitoring the battery cell voltages, the X3100 and X3101 continually monitor the voltage VCS21 (VCS2 - VCS1) across the current sense resistor (RSENSE). If VCS21 > VOC for a time exceeding TOC, then the device enters over-current protection mode (Figure 7). In this mode, the X3100 and X3101 automatically switch the discharge FET OFF (UVP/OCP = Vcc) and hence prevent current from flowing through the terminals P+ and P-. Figure 5. Over-Current Protection ILMON D1 VRGO ROCR (Load) P+ If the load resistance > ROCR (ILMON = 0µA) for a time exceeding TOCR, then the X3100 or X3101 is released from over-current protection mode. The discharge FET is then automatically switched ON (UVP/OCP = Vss) by the X3100 or X3101, unless the status of UVP/OCP has been changed in control register (by manipulating bit UVPC) during the over-current protection mode. TOC/TOCR are varied using a capacitor (COC) connected between pin OCT and VSS. A list of typical delay times is shown in Table 23. Note that the value COC should be larger than 1nF. The delay TOC and TOCR that results from a particular capacitance COC can be approximated by the following equations: TOC (ms) ≈ 10,000 x COC (µF) TOCR (ms) ≈ 10,000 x COC (µF) Table 23. Typical Over-Current Delay Times Symbol Description Over-current detection delay Over-current release time Q2 Q10 OVP/LMON X3100/X3101 FET Control Circuitry COC 0.001µF 0.001µF Delay 10ms (Typ) 10ms (Typ) TOC TOCR VSS VCS1 RSENSE VCS2 P- The value of VOC can be selected from the values shown in Table 6, by setting bits VOC1, VOC0 in the configuration register using the WCFIG command. Note: If the Charge FET is turned off, due to an overcharge condition or by direct command from the microcontroller, the cells are not in an undervoltage condition and the pack has a load, then excessive current may flow through Q10 and diode D1. To eliminate this effect, the gate of Q10 can be turned off by the microcontroller through an unused X3101 cell balance output, or directly from a microcontroller port instead of connecting to VRGO. The 5VDC voltage regulator output (VRGO) is always active during an over-current protection mode. Once the device enters over-current protection mode, the X3100 and X3101 begin a load monitor state. In the load monitor state, a small current (ILMON = 7.5µA typ.) is passed out of pin OVP/LMON in order to determine the load resistance. The load resistance is the impedance seen looking out of pin OVP/LMON, between terminal P+ and pin VSS (See Figure 5.) 19 FN8110.1 January 3, 2008 X3100, X3101 Figure 6. Over-Current Protection Mode—Event Diagram Normal Operation Mode B+ P+ Over-Current Protection Mode Normal Operation Mode P+ = (RLOAD+RSENSE) x ILMON VOC VCS2 TOC TOCR Voc VSS VCC UVP/OCP VSS Event 0 1 2 3 4 Table 24. Over-Current Protection Mode—Event Diagram Description Event [0,1) Event Description — Discharge FET is ON (OCP = Vss). Battery cells are permitted to discharge. — VCS21 (VCS2 - VCS1) is less than the over-current threshold voltage (VOC). — The device is in normal operation mode (i.e. not in a protection mode). — Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 6.). — The positive battery terminal voltage (P+) falls, and VCS21 exceeds VOC. — The internal over-current detection delay timer begins counting down. — The device is still in Normal Operation Mode The internal Over-current detection delay timer continues counting for TOC seconds. — The internal over-current detection delay timer times out, AND VCS21 is still above VOC. — The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc). — The device now begins a load monitor state by passing a small test current (ILMON = 7.5µA) out of pin OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < ROCR) still exists across P+/P-. — The device has now entered over-current protection mode. — It is possible to change the status of UVPC and OVPC in the control register, although the status of pins UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection mode. — The X3100/X3101 now continuously monitors the load resistance to detect whether or not an overcurrent condition is still present across the battery terminals P+/P-. [1] (1,2) [2] (2,3) 20 FN8110.1 January 3, 2008 X3100, X3101 Table 24. Over-Current Protection Mode—Event Diagram Description (Continued) Event [3] Event Description — The device detects the load resistance has risen above ROCR. — Voltages P+ and VCS21 return to their normal levels. — The test current from pin OVP/LMON is stopped (ILMON = 0µA) — The device has now returned from the load monitor state — The internal over-current release time timer begins counting down. — Device is still in over-current protection mode. The internal over-current release timer continues counting for TOCR seconds. — The internal over-current release timer times out, and VCS21 is still below VOC. — The device returns from over-current protection mode, and is now in normal operation mode. — The discharge FET is automatically switched ON (UVP/OCP = Vss)—unless the status of UVPC has been changed in the control register during the over-current protection mode. — The status of the charge FET remains unaffected. — Discharge of the battery cells is once again possible. (3,4) [4] MONITOR MODE Analog Multiplexer Selection The X3100 and X3101 can be used to externally monitor individual battery cell voltages, and battery current. Each quantity can be monitored at the analog output pin (AO), and is selected using the analog select (AS0 - AS2) pins (Table 25). Also, see Figure 7. Table 25. AO Selection Map AS2 AS1 AS0 L L L L H H H H L L H H L L H H L H L H L H L H VSS(1) VCELL1 - VCELL2 (VCELL12) VCELL2 - VCELL3 (VCELL23) VCELL3 - VCELL4 (VCELL34) VCELL4 - Vss (VCELL4) VCS1 - VCS2 (VCS12)(2) VCS2 - VCS1 (VCS21)(2) VSS Since the value of the sense resistor (RSENSE) is small (typically in the order of tens of mΩ), and since the resolution of various A/D converters may vary, the voltage across RSENSE (VCS1 and VCS2) is amplified internally with a gain of between 10 and 160, and output to pin AO (Figure 7). Figure 7. X3100/X3101 Monitor Circuit AO output Analog MUX Voltage Level Shifters Cell 1 Voltage Cell 2 Voltage Cell 3 Voltage Cell 4 Voltage AS0 AS1 AS2 AO 2.5V R2 + R1 R1 Config Register Gain Setting OP1 R2 S0 Notes: (1) This is the normal state of the X3100 or X3101. While in this state Over-charge and Over-discharge Protection conditions are periodically monitored (See “Periodic Protection Monitoring” on page 13.) (2) VCS1, VCS2 are read at AO with respect to a DC bias voltage of 2.5V (See section “Current Monitor Function” on page 21). SPI I/F SCL CS SI CSG1 CSG0 Cross-Bar Switch Over-Current Protection Current Monitor Function The voltages monitored at pins VCS1 and VCS2 can be used to calculate current flowing through the battery terminals, using an off-board microcontroller with an A/D. VCS1 VCS2 RSENSE X3100/X3101 P- 21 FN8110.1 January 3, 2008 X3100, X3101 The internal gain of the X3100 or X3101 current sense voltage amplifier can be selected by using the WCNTR Instruction to set bits CSG1 and CSG0 in the control register (Table 14). The CSG1 and CSG0 bits select one of four input resistors to Op Amp OP1. The feedback resistors remain constant. This ratio of input to feedback resistors determines the gain. Putting external resistors in series with the inputs reduces the gain of the amplifier. VCS1 and VCS2 are read at AO with respect to a DC bias voltage of 2.5V. Therefore, the voltage range of VCS12 and VCS21 changes depending upon the direction of current flow (i.e. battery cells are in Charge or Discharge—Table 21). Table 26. AO Voltage Range for VCS12 and VCS21 AO VCS12 VCS12 VCS21 VCS21 The maximum current that can flow from the voltage regulator (ILMT) is controlled by the current limiting resistor (RLMT) connected between RGP and VCC. When the voltage across VCC and RGP reaches a nominal 2.5V (i.e. the threshold voltage for the FET), Q2 switches ON, shorting VCC to the base of Q1. Since the base voltage of Q1 is now higher than the emitter voltage, Q1 switches OFF, and hence the supply current goes to zero. Typical values for RLMT and ILMT are shown in Table 27. In order to protect the voltage regulator circuitry from damage in case of a short-circuit, RLMT ≥ 10Ω should always be used. Table 27. Typical Values for RLMT and ILMT RLMT 10Ω 25Ω 50Ω Cell State Charge Discharge Charge Discharge AO Voltage Range 2.5V ≤ AO ≤ 5.0V 0V ≤ AO ≤ 2.5V 0V ≤ AO ≤ 2.5V 2.5V ≤ AO ≤ 5.0V Voltage Regulator Current Limit (ILMT) 250mA ± 50% (Typical) 100mA ± 50% (Typical) 50mA ± 50% (Typical) By calculating the difference of VCS12 and VCS21 the offset voltage of the internal op-amp circuitry is cancelled. This allows for the accurate calculation of current flow into and out of the battery cells. Pack current is calculated using the following formula: ( VCS 12 – VCS 21 ) Pack Current = --------------------------------------------------------------------------------------------------------( 2 ) ( gain setting ) (current sense resistor) When choosing the value of RLMT, the drive limitations of the PNP transistor used should also be taken into consideration. The transistor should have a gain of at least 100 to support an output current of 250mA. Figure 8. Voltage Regulator Operation VCC To Internal Voltage Regulating Circuitry Un-Regulated Voltage Input RLMT X3100/X3101 VOLTAGE REGULATOR The X3100 and X3101 are able to supply peripheral devices with a regulated 5VDC±0.5% output at pin RGO. The voltage regulator should be configured externally as shown in Figure 8. The non-inverting input of OP1 is fed with a high precision 5VDC supply. The voltage at the output of the voltage regulator (VRGO) is compared to this 5V reference via the inverting input of OP1. The output of OP1 in turn drives the regulator pnp transistor (Q1). The negative feedback at the regulator output maintains the voltage at 5VDC±0.5% (including ripple) despite changes in load, and differences in regulator transistors. When power is applied to pin VCC of the X3100 or X3101, VRGO is regulated to 5VDC±10% for a nominal time of TOC+2ms. During this time period, VRGO is “tuned” to attain a final value of 5VDC±0.5% (Figure ). Tuning Q2 RGP ILMT 5VDC Precision Voltage Reference + _ OP1 RGC Q1 RGO Regulated 5VDC Output 0.1 µF VRGO 4KBIT EEPROM MEMORY The X3100 and X3101 contain a CMOS 4k-bit serial EEPROM, internally organized as 512 x 8 bits. This memory is accessible via the SPI port, and features the IDLock function. 22 FN8110.1 January 3, 2008 X3100, X3101 The 4kbit EEPROM array can be accessed by the SPI port at any time, even during a protection mode, except during sleep mode. After power is applied to VCC of the X3100 or X3101, EEREAD and EEWRITE Instructions can be executed only after times tPUR (power-up to read time) and tPUW (power-up to write time) respectively. IDLock is a programmable locking mechanism which allows the user to lock data in different portions of the EEPROM memory space, ranging from as little as one page to as much as 1/2 of the total array. This is useful for storing information such as battery pack serial number, manufacturing codes, battery cell chemistry data, or cell characteristics. EEPROM Write Enable Latch The X3100 and X3101 contain an EEPROM “Write Enable” latch. This latch must be SET before a write to EEPROM operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 9). This latch is automatically reset upon a power-up condition and after the completion of a byte or page write cycle. IDLock Memory Intersil’s IDLock memory provides a flexible mechanism to store and lock battery cell/pack information. There are seven distinct IDLock memory areas within the array which vary in size from one page to as much as half of the entire array. Prior to any attempt to perform an IDLock operation, the WREN instruction must first be issued. This instruction sets the “Write Enable” latch and allows the part to respond to an IDLock sequence. The EEPROM memory may then be IDLocked by writing the SET IDL instruction (Table 30 and Figure 17), followed by the IDLock protection byte. Table 28. IDLock Partition Byte Definition IDLock Protection Bytes 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 The IDLock protection byte contains the IDLock bits IDL2-IDL0, which defines the particular partition to be locked (Table 28). The rest of the bits [7:3] are unused and must be written as zeroes. Bringing CS HIGH after the two byte IDLock instruction initiates a nonvolatile write to the status register. Writing more than one byte to the status register will overwrite the previously written IDLock byte. Once an IDLock instruction has been completed, that IDLock setup is held in a nonvolatile IDLock Register (Table 29) until the next IDLock instruction is issued. The sections of the memory array that are IDLocked can be read but not written until IDLock is removed or changed. Table 29. IDLock Register 7 0 Note: 6 0 5 0 4 0 3 0 2 IDL2 1 IDL1 0 IDL0 Bits [7:3] specified to be “0’s” X3100/X3101 SPI SERIAL COMMUNICATION The X3100 and X3101 are designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. This interface uses four signals, CS, SCK, SI and SO. The signal CS when low, enables communications with the device. The SI pin carries the input signal and SO provides the output signal. SCK clocks data in or out. The X3100 and X3101 operate in SPI mode 0 which requires SCK to be normally low when not transferring data. It also specifies that the rising edge of SCK clocks data into the device, while the falling edge of SCK clocks data out. This SPI port is used to set the various internal registers, write to the EEPROM array, and select various device functions. The X3100 and X3101 contain an 8-bit instruction register. It is accessed by clocking data into the SI input. CS must be LOW during the entire operation. Table 30 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock, and then start it again to resume operations where left off. EEPROM Memory Address IDLocked None 000h - 07Fh 080h - 0FFh 100h - 17Fh 180h - 1FFh 000h - 0FFh 000h - 00Fh 1F0h - 1FFh 23 FN8110.1 January 3, 2008 X3100, X3101 Table 30. X3100/X3101 Instruction Set Instruction Name WREN WRDI EEWRITE EEREAD STAT EEREAD WCFIG WCNTR RDSTAT SET IDL Instruction Format* 0000 0110 0000 0100 0000 0010 0000 0101 0000 0011 0000 1001 0000 1010 0000 1011 0000 0001 Description Set the write enable latch (write enable operation)—Figure 9 Reset the write enable latch (write disable operation)—Figure 9 Write command followed by address/data (4kbit EEPROM)—Figure 10, Figure 11 Reads IDLock settings & status of EEPROM EEWRITE instruction—Figure 12 Read operation followed by address (for 4kbit EEPROM)—Figure 13 Write to configuration register followed by two bytes of data—Figure 2, Figure 14. Data stored in SRAM only and will power-up to previous settings—Figure 1 Write to control register, followed by two bytes of data—Figure 15 Read contents of status register—Figure 16 Set EEPROM ID lock partition followed by partition byte—Figure 17 *Instructions have the MSB in leftmost position and are transferred MSB first. Write Enable/Write Disable (WREN/WRDI) Any write to a nonvolatile array or register, requires the WREN command be sent prior to the write command. This command sets an internal latch allowing the write operation to proceed. The WRDI command resets the internal latch if the system decides to abort a write operation. See Figure 9. Figure 9. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 WREN Instruction (1 Byte) SI High Impedance SO WRDI 24 FN8110.1 January 3, 2008 X3100, X3101 EEPROM Write Sequence (EEWRITE) Prior to any attempt to write data into the EEPROM of the X3100 or X3101, the “Write Enable” latch must first be set by issuing the WREN instruction (See Table 30 and Figure 9). CS is first taken LOW. Then the WREN instruction is clocked into the X3100 or X3101. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user issues the EEWRITE instruction, followed by the 16 bit address and the data to be written. Only the last 9 bits of the address are used and bits [15:9] are specified to be zeroes. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 16 bytes of data to the X3100 or X3101. The only restriction is the 16 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been previously written. For a byte or page write operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed. Refer to Figure 10 and Figure 11 for detailed illustration of the write sequences and time frames in which CS going HIGH are valid. EEPROM Read Status Operation (EEREAD STAT) If there is not a nonvolatile write in progress, the EEREAD STAT instruction returns the IDLock byte from the IDLock register which contains the IDLock bits IDL2-IDL0 (Table 29). The IDLock bits define the IDLock condition (Table 28). The other bits are reserved and will return ‘0’ when read. If a nonvolatile write to the EEPROM (i.e. EEWRITE instruction) is in progress, the EEREAD STAT returns a HIGH on SO. When the nonvolatile write cycle in the EEPROM is completed, the status register data is read out. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (See Figure 12). Figure 10. EEPROM Byte Write (EEWRITE) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 20 21 22 23 24 25 26 27 28 29 30 31 EEWRITE Instruction (1 Byte) SI Byte Address (2 Byte) 15 14 3 2 1 0 7 6 5 Data Byte 4 3 2 1 0 SO High Impedance 25 FN8110.1 January 3, 2008 X3100, X3101 Figure 11. EEPROM Page Write (EEWRITE) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 EEWRITE Instruction SI Byte Address (2 Byte) 15 14 13 3 2 1 0 7 6 5 Data Byte 1 4 3 2 1 0 CS 145 146 147 148 149 150 1 151 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5 Data Byte 3 4 3 2 1 0 6 5 Data Byte 16 4 3 2 Figure 12. EEPROM Read Status (EEREAD STAT) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 ... ... I D L 2 I D L 1 I D L 0 EEREAD STAT Instruction SI Nonvolatile EEWRITE in Progress SO ... SO High During Nonvolatile EEWRITE Cycle SO=Status Reg Bit When No Nonvolatile EEWRITE Cycle 26 FN8110.1 January 3, 2008 X3100, X3101 EEPROM Read Sequence (EEREAD) When reading from the X3100 or X3101 EEPROM memory, CS is first pulled LOW to select the device. The 8-bit EEREAD instruction is transmitted to the X3100 or X3101, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified to be zeroes). After the EEREAD opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in Figure 13. EEPROM (EEREAD) Read Operation Sequence CS memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the EEPROM Read (EEREAD) operation sequence illustrated in Figure 13. 0 SCK 1 2 3 4 5 6 7 8 9 20 21 22 23 24 25 26 27 28 29 30 31 EEREAD Instruction (1 Byte) SI Byte Address (2 Byte) 15 14 3 2 1 0 Data Out SO High Impedance 7 6 5 4 3 2 1 0 27 FN8110.1 January 3, 2008 X3100, X3101 Write Configuration Register (WCFIG) The Write Configuration Register (WCFIG) instruction updates the static part of the Configuration Register. These new values take effect immediately, for example writing a new Over-discharge voltage limit. However, to make these changes permanent, so they remain if the cell voltages are removed, an EEWRITE operation to the EEPROM array is required following the WCFIG command. This command is shown in Figure 14. Write Control Register (WCNTRL) The Write Control Register (WCNTRL) instruction updates the contents of the volatile Control Register. This command sets the status of the FET control pins, the cell balancing outputs, the current sense gain and external entry to the sleep mode. Since this instruction controls a volatile register, no other commands are required and there is no delay time needed after the instruction, before subsequent commands. The operation of the WCNTRL command is shown in Figure 15. Figure 14. Write Configuration Register (WCFIG) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 20 21 22 23 WCFIG Instruction SI (1 BYTE) High Impedance Configuration Register Data 15 14 (2 BYTE) 3 2 1 0 SO Figure 15. Write Control Register (WCNTR) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 WCNTR Instruction SI (1 Byte) High Impedance 15 14 Control Register Data 5 (2 Byte) 4 3 2 1 0 SO Control Bits Old Control Bits New Control Bits 28 FN8110.1 January 3, 2008 X3100, X3101 Read Status Register (RDSTAT) The Read Status Register (RDSTAT) command returns the status of the X3100 or X3101. The Status Register contains three bits that indicate whether the voltage regulator is stabilized, and if there are any protection failure conditions. The operation of the RDSTAT instruction is shown in Figure 16. Set ID Lock (SET IDL) The contents of the EEPROM memory array in the X3100 or X3101 can be locked in one of eight configurations using the SET ID lock command. When a section of the EEPROM array is locked, the contents cannot be changed, even when a valid write operation attempts a write to that area. The SET IDL command operation is shown in Figure 17. Figure 16. Read Status Register (RDSTAT) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDSTAT Instruction SI (1 Byte) High Impedance Status Register Output SO 2 1 0 Figure 17. EEPROM IDLock (SET IDL) Operation Sequence CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Set IDL Instruction SI IDLock Byte I D L 2 I D L 1 I D L 0 SO High Impedance 29 FN8110.1 January 3, 2008 X3100, X3101 ABSOLUTE MAXIMUM RATINGS Symbol Storage temperature Operating temperature DC output current Lead temperature (soldering 10 seconds) VCC VCELL VTERM1 VTERM2 VTERM3 Power supply voltage Cell voltage Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1, VCS2, OVT, UVT, OCT, AO) Terminal voltage (VCELL1) Terminal voltage (all other pins) VSS-0.5 -0.5 VSS-0.5 VSS-0.5 VSS-0.5 Parameter Min. -55 -40 Max. 125 85 5 300 VSS+27.0 6.75 VRGO + 0.5 VCC + 1.0 VCC + 0.5 Unit °C °C mA °C V V V V V Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Min. -20°C Max. +70°C Supply Voltage X3100/X3101 Limits 6V to 24V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Limits Symbol ILI ILO VIL (1) Parameter Input leakage current (SCK, SI, CS, ASO, AS1, AS2) Output leakage current (SO) Input LOW voltage (SCK, SI, CS, AS0, AS1, AS2) Input HIGH voltage (SCK, SI, CS, AS0, AS1, AS2) Output LOW voltage (SO) Output HIGH voltage (SO) Output LOW voltage (UVP/OCP, OVP/LMON, CB1-CB4) Output HIGH voltage (UVP/OCP, OVP/LMON, CB1-CB4) Output LOW voltage (RGC) Output HIGH voltage (RGC) Min. Max. ±10 ±10 Units µA µA V V V V V V Test Conditions - 0.3 VRGO x 0.7 VRGO x 0.3 VRGO + 0.3 0.4 VIH(1) VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 Note: IOL = 1.0mA IOH = -0.4mA IOL = 100uA IOH = -20uA IOL = 2mA, RGP = VCC, RGO = 5V IOH = -20µA, RGP = VCC - 4V, RGO = 5V VRGO - 0.8 0.4 VCC-0.4 0.4 VCC-4.0 V V (1) VIL min. and VIH max. are for reference only and are not 100% tested. 30 FN8110.1 January 3, 2008 X3100, X3101 OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage Sym VRGO Condition On power-up or at wake-up After self-tuning (@10mA VRGO current; 25oC) After self-tuning (@10mA VRGO current; 0 - 50oC)(5) After self-tuning (@50mA VRGO current)(5) Min 4.5 4.98 4.95 4.90 Typ(2) 4.99 Max 5.5 5.00 5.02 5.00 Unit V V mA 5VDC voltage regulator current limit VCC supply current (1) VCC supply current (2) VCC supply current (3) VCC supply current (4) VCC supply current (5) Cell over-charge protection mode voltage threshold (Default in Boldface) ILMT(3) Icc1 Icc2 Icc3 Icc4 Icc5 VOV(4) RLMT = 10Ω Normal operation during nonvolatile EEPROM write During EEPROM read SCK=3.3MHz Sleep mode Monitor mode AN2, AN1, AN0 not equal to 0. VOV = 4.20V (VOV1, VOV0 = 0,0) 0oC to 50oC VOV = 4.25V (VOV1, VOV0 = 0,1) 0oC to 50oC VOV = 4.30V (VOV1, VOV0 = 1,0) 0oC to 50oC VOV = 4.35V (VOV1, VOV0 = 1,1) 0oC to 50oC 4.10 4.15 4.15 4.20 4.2 4.25 4.25 4.30 250 85 1.3 0.9 250 2.5 1.2 1 365 600 4.275 4.25 4.325 4.30 4.375 4.35 4.425 4.40 VOV 0.20 µA mA mA µA µA V V V V V s Cell over-charge protection mode release voltage threshold Cell over-charge detection time Cell over-discharge protection mode (SLEEP) threshold. (Default in Boldface) VOVR TOV VUV (4) COV = 0.1uF VUV = 1.95V (VUV1, VUV0 = 0,0) VUV = 2.05V (VUV1, VUV0 = 0,1) VUV = 2.15V (VUV1, VUV0 = 1,0) VUV = 2.25V (VUV1, VUV0 = 1,1) 1.85 1.95 2.05 2.15 1 2.05 2.15 2.25 2.35 VUV + 0.7 V V V V V s ms ms µs Cell over-discharge protection mode release threshold Cell over-discharge detection time Cell over-discharge release time VUVR TUV TUVR CUV = 0.1µF CUV = 200pF CUV = 0.1µF CUV = 200pF 1 2 7 100 31 FN8110.1 January 3, 2008 X3100, X3101 Description Over-current mode detection voltage (Default in Boldface) Sym VOC (4) Condition VOC = 0.075V (VOC1, VOC0 = 0,0) 0oC to 50oC VOC = 0.100V (VOC1, VOC0 = 0,1) 0oC to 50oC VOC = 0.125V (VOC1, VOC0 = 1,0) 0oC to 50oC VOC = 0.150V (VOC1, VOC0 = 1,1) 0oC to 50oC Min 0.050 0.060 0.075 0.085 0.100 0.110 0.125 0.135 Typ(2) Max 0.100 0.090 0.125 0.115 0.150 0.140 0.175 0.165 Unit V V V V ms ms kΩ Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage TOC TOCR ROCR VCE(4) COC = 0.001µF COC = 200pF COC = 0.001µF COC = 200pF Releases when OVP/LMON pin > 2.5V VCE = 0.5V (Vce1, Vce0 = 0,0) VCE = 0.8V (Vce1, Vce0 = 0,1) VCE = 1.1V (Vce1, Vce0 = 1,0) VCE = 1.4V (Vce1, Vce0 = 1,1) 0.4 0.7 1 1.3 12.5 10 2 10 2 250 0.5 0.8 1.1 1.4 0.6 0.9 1.2 1.5 15.5 V V V V V X3100 wake-up voltage (For Vcc above this voltage, the device wakes up) VSLR See Wake-up test circuit X3100 sleep voltage (For Vcc above this voltage, the device cannot go to sleep) Notes: (2) (3) (4) (5) VSLP See Sleep test circuit 11.5 14.5 V Typical at 25°C. See Figure 10 on page 22. The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register. For reference only, this parameter is not 100% tested. Wake-up test circuit (X3100) Vcc Sleep test circuit (X3100) Vcc Vcc VCELL1 VCELL2 VCELL3 RGP RGC RGO Vcc VCELL1 RGP RGC RGO 1V VRGO VCELL2 VRGO 1V VCELL3 1V VCELL4 VCELL4 1V Vss Vss Increase Vcc until VRGO turns on Decrease Vcc until VRGO turns off 32 FN8110.1 January 3, 2008 X3100, X3101 OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified) Description 5V regulated voltage Sym VRGO Condition On power-up or at wake-up After self-tuning (@10mA VRGO current; 25oC) After self-tuning (@10mA VRGO current; 0 - 50oC)(5) After self-tuning (@50mA VRGO current)(5) Min 4.5 4.98 4.95 4.90 Typ(2) 4.99 Max 5.5 5.00 5.02 5.00 Unit V V mA 5VDC voltage regulator current limit VCC supply current (1) VCC supply current (2) VCC supply current (3) VCC supply current (4) VCC supply current (5) Cell over-charge protection mode voltage threshold (Default in Boldface) ILMT(3) Icc1 Icc2 Icc3 Icc4 Icc5 VOV(4) RLMT = 10Ω Normal operation during nonvolatile EEPROM write During EEPROM read SCK = 3.3MHz Sleep mode Monitor mode AN2, AN1, AN0 not equal to 0. VOV = 4.20V (VOV1, VOV0 = 0,0) 0oC to 50oC VOV = 4.25V (VOV1, VOV0 = 0,1) 0oC to 50oC VOV = 4.30V (VOV1, VOV0 = 1,0) 0oC to 50oC VOV = 4.35V (VOV1, VOV0 = 1,1) 0oC to 50oC 4.10 4.15 4.15 4.20 4.2 4.25 4.25 4.30 250 85 1.3 0.9 250 2.5 1.2 1 365 600 4.275 4.25 4.325 4.30 4.375 4.35 4.425 4.40 VOV 0.20 µA mA mA µA µA V V V V V s Cell over-charge protection mode release voltage threshold Cell over-charge detection time Cell over-discharge protection mode (SLEEP) threshold. (Default in Boldface) VOVR TOV VUV (4) COV = 0.1uF VUV = 2.25V (VUV1, VUV0 = 0,0) VUV = 2.35V (VUV1, VUV0 = 0,1) VUV = 2.45V (VUV1, VUV0 = 1,0) VUV = 2.55V (VUV1, VUV0 = 1,1) 2.15 2.25 2.35 2.45 1 2.35 2.45 2.55 2.65 VUV + 0.7 V V V V V s ms ms µs Cell over-discharge protection mode release threshold Cell over-discharge detection time Cell over-discharge release time VUVR TUV TUVR CUV = 0.1µF CUV = 200pF CUV = 0.1µF CUV = 200pF 1 2 7 100 33 FN8110.1 January 3, 2008 X3100, X3101 Description Over-current mode detection voltage (Default in Boldface) Sym VOC (4) Condition VOC = 0.075V (VOC1, VOC0 = 0,0) 0oC to 50oC VOC = 0.100V (VOC1, VOC0 = 0,1) 0oC to 50oC VOC = 0.125V (VOC1, VOC0 = 1,0) 0oC to 50oC VOC = 0.150V (VOC1, VOC0 = 1,1) 0oC to 50oC Min 0.050 0.060 0.075 0.085 0.100 0.110 0.125 0.135 Typ(2) Max 0.100 0.090 0.125 0.115 0.150 0.140 0.175 0.165 Unit V V V V ms ms kΩ Over-current mode detection time Over-current mode release time Load resistance over-current mode release condition Cell charge threshold voltage TOC TOCR ROCR VCE COC = 0.001µF COC = 200pF COC = 0.001µF COC = 200pF Releases when OVP/LMON pin > 2.5V VCE = 0.5V (Vce1, Vce0 = 0,0) VCE = 0.8V (Vce1, Vce0 = 0,1) VCE = 1.1V (Vce1, Vce0 = 1,0) VCE = 1.4V (Vce1, Vce0 = 1,1) 0.4 0.7 1 1.3 10.5 10 2 10 2 250 0.5 0.8 1.1 1.4 0.6 0.9 1.2 1.5 12.5 V V V V V X3101 wake-up voltage (For Vcc above this voltage, the device wakes up) VSLR See Wake-up test circuit X3101 sleep voltage (For Vcc above this voltage, the device cannot go to sleep) Notes: (2) (3) (4) (5) VSLP See Sleep test circuit 9.5 11.5 V Typical at 25°C. See Figure 10 on page 22. The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register. For reference only, this parameter is not 100% tested. Wake-up test circuit (X3101) Vcc Sleep test circuit (X3101) Vcc Vcc VCELL1 VCELL2 VCELL3 RGP RGC RGO Vcc VCELL1 RGP RGC RGO 1V VRGO VCELL2 VRGO 1V VCELL3 1V VCELL4 VCELL4 Vss Vss Increase Vcc until VRGO turns on Decrease Vcc until VRGO turns off 34 FN8110.1 January 3, 2008 X3100, X3101 POWER-UP TIMING Symbol tPUR (6) Parameter Power-up to SPI read operation (RDSTAT, EEREAD STAT) Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR) Power-up to SPI write operation (WCNTR - bits 10 and 11) Min. Max. TOC + 2ms TOC + 2ms TOV + 200ms or TUV + 200ms(7) tPUW1(6) tPUW2(6) Notes: (6) tPUR, tPUW1 and tPUW2 are the delays required from the time VCC is stable until a read or write can be initiated. These parameters are not 100% tested. (7) Whichever is longer. CAPACITANCE TA = +25°C, f = 1 MHz, VRGO = 5V Symbol COUT(8) CIN(8) Parameter Output capacitance (SO) Input capacitance (SCK, SI, CS) Max. 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V Notes: (8) This parameter is not 100% tested. Equivalent A.C. Load Circuit 5V 2061Ω SO 3025Ω 30pF A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level 0.5 - 4.5V 10ns 2.5V 35 FN8110.1 January 3, 2008 X3100, X3101 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) SERIAL INPUT TIMING Symbol fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(9) tFI(9) tCS tWC (10) Parameter Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Data in rise time Data in fall time CS deselect time Write cycle time Voltage Min. 0 300 150 150 130 130 20 20 Max. 3.3 Units MHz ns ns ns ns ns ns ns 2 2 100 5 µs µs ns ms Notes: (9) This parameter is not 100% tested (10)tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Input Timing tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO 36 FN8110.1 January 3, 2008 X3100, X3101 Serial Output Timing Symbol fSCK tDIS tV tHO tRO tFO (11) (11) Parameter Clock Frequency Output Disable Time Output Valid from Clock LOW Output Hold Time Output Rise Time Output Fall Time Voltage Min. 0 Max. 3.3 150 130 Units MHz ns ns ns ns ns 0 50 50 Notes: (11)This parameter is not 100% tested. Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB In SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 37 FN8110.1 January 3, 2008 X3100, X3101 Analog Output Response Time Symbol tVSC tCSGO tCO Parameter AO Output Stabilization Time (Voltage Source Change) AO Output Stabilization Time (Current Sense Gain Change) Control Outputs Response Time (UVP/OCP, OVP/MON, CB4, CB3, CB2, CB1, RGC) Min. Typ. Max. 1.0 1.0 1.0 Units ms ms µs ANALOG OUTPUT RESPONSE TIME Change in Voltage Source AS2:AS0 AO tVSC tVSC Change in Current Sense Gain Amplification and Control Bits CS SCK DI Control Reg OVPC Bit10 CSG1 CSG0 Bit9 Bit8 SLP Bit7 0 Bit6 0 Bit5 x AO Current Sense Gain Change Old Gain tCSGO New Gain UVP/OCP OVP/LMON CB4:CB1 RGC Control Outputs On Off tCO 38 FN8110.1 January 3, 2008 X3100, X3101 TYPICAL OPERATING CHARACTERISTICS Norm al Operating Current 150 Current (uA) Current (uA) 125 100 75 50 -20 25 Tem perature 80 450 Monitor Mode Current 400 350 300 -20 25 Tem perature 80 X3100/X3101 Over Charge Trip Voltage (Typical) 4.40 Voltage (V) Voltage (V) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 -25 X3100 Over Discharge Trip Voltage (Typical) 4.35 4.30 4.25 4.20 4.15 -25 25 Temperature (Deg C) 4.2V Setting 4.3V Setting 4.25V Setting 4.35V Setting 75 25 Temperature (Deg C) 1.95V Setting 2.15V Setting 2.05V Setting 2.25V Setting 75 X3101 Over Discharge Trip Voltage (Typical) 2.60 Voltage Regulator Output (Typical) Vcc = 10.8V to 16V Rlim = 15 Ohm (Ilim = 200mA) Regulator Voltage (V) 5.020 5.000 4.980 4.960 4.940 4.920 4.900 4.880 1 10 Load (mA) -25 degC 25 degC 75 degC 50 100 2.55 Voltage (V) 2.50 2.45 2.40 2.35 2.30 2.25 -25 25 Temperature (Deg C) 2.25V Setting 2.45V Setting 2.35V Setting 2.55V Setting 75 Voltage Regulator Output (Typical) Vcc = 10.8V to 16V Rlim = 15 Ohm (Ilim = 200mA) 5.020 5.000 4.980 4.960 4.940 4.920 4.900 4.880 -25 25 Temperature Regulated Voltage 75 1mA Load 10mA Load 50mA Load 100 mA Load For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143 39 FN8110.1 January 3, 2008 X3100, X3101 40 FN8110.1 January 3, 2008 X3100, X3101 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 0.246 0.0177 28 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 6.25 0.45 28 8o MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 0 6/98 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) D A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 41 FN8110.1 January 3, 2008