X4003M8IZ-4.5A

® X4003, X4005 Data Sheet May 11, 2006 FN8113.1 CPU Supervisor FEATURES • Selectable watchdog timer —Select 200ms, 600ms, 1.4s, off • Low VCC detection and reset assertion —Five standard reset threshold voltages nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —12µA typical standby current, watchdog on —800nA typical standby current watchdog off —3mA active current • 400kHz I2C interface • 1.8V to 5.5V power supply operation • Available packages —8 Ld SOIC —8 Ld MSOP • Pb-free plus anneal available (RoHS compliant) DESCRIPTION These devices combine three popular functions, Power-on Reset Control, Watchdog Timer, and Supply Voltage Supervision. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available; however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements, or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Transition Detector WP SDA Data Register Command Decode & Control Logic VCC Threshold Reset logic VCC VTRIP + Watchdog Timer Reset RESET (X4003) Control Register Reset & Watchdog Timebase RESET (X4005) SCL Power-on and Low Voltage Reset Generation 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X4003, X4005 Ordering Information PART NUMBER RESET (ACTIVE LOW) X4003M8-4.5A X4003M8Z-4.5A (Note) X4003M8I-4.5A X4003M8IZ-4.5A (Note) X4003S8-4.5A X4003S8Z-4.5A (Note) X4003S8I-4.5A X4003S8IZ-4.5A (Note) X4003M8 PART MARKING ACH DAH ACI DAD X4003 AL PART NUMBER RESET (ACTIVE HIGH) X4005M8-4.5A X4005M8Z-4.5A (Note) X4005M8I-4.5A PART VCC RANGE VTRIP RANGE TEMP. RANGE MARKING (V) (V) (°C) ACQ DAP ACR 4.5 to 5.5 4.5 to 4.75 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 4.25 to 4.5 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 2.7 to 5.5 2.85 to 3.0 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 PACKAGE 8 Ld MSOP (3.0mm) PKG. DWG. # M8.118 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 X4005M8IZ-4.5A DAM (Note) X4005S8-4.5A X4005 AL X4005 ZAL X4005 AM 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 X4003 ZAL X4005S8Z-4.5A (Note) X4003 AM X4005S8I-4.5A 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 X4003 ZAM X4005S8IZ-4.5A X4005 ZAM (Note) ACJ X4005M8 ACS 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 X4003M8Z (Note) DAE X4003M8I ACK X4005M8Z (Note) DER X4005M8I X4005M8IZ (Note) X4005S8 ACT DAJ X4005 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 X4003M8IZ (Note) DAA X4003S8 X4003 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 X4003S8Z (Note) X4003 Z X4003S8I X4003 I X4005S8Z (Note) X4005 Z X4005S8I X4005S8IZ (Note) X4005M8-2.7A X4005M8Z-2.7A (Note) X4005M8I-2.7A X4005 I X4005 ZI ACU DAO ACV 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 X4003S8IZ (Note) X4003 ZI X4003M8-2.7A X4003M8Z-2.7A (Note) X4003M8I-2.7A X4003M8IZ-2.7A (Note) X4003S8-2.7A X4003S8Z-2.7A (Note) X4003S8I-2.7A ACL DAG ACM DAC X4003 AN 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 X4005M8IZ-2.7A DAL (Note) X4005S8-2.7A X4005 AN X4005 ZAN X4005 AP 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 X4003 ZAN X4005S8Z-2.7A (Note) X4003 AP X4005S8I-2.7A 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 2 FN8113.1 May 11, 2006 X4003, X4005 Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) X4003S8IZ-2.7A (Note) X4003M8-2.7 X4003M8Z-2.7 (Note) X4003M8I-2.7 X4003M8IZ-2.7 (Note) X4003S8-2.7 X4003S8Z-2.7 (Note) X4003S8I-2.7 X4003S8IZ-2.7 (Note) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART VCC RANGE VTRIP RANGE TEMP. RANGE MARKING (V) (V) (°C) 2.7 to 5.5 2.85 to 3.0 2.55 to 2.7 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE PKG. DWG. # X4003 ZAP X4005S8IZ-2.7A X4005 ZAP (Note) ACN DAF ACO DAB X4003 F X4003 ZF X4003 G X4003 ZG X4005M8-2.7 X4005M8Z-2.7 (Note) X4005M8I-2.7 X4005M8IZ-2.7 (Note) X4005S8-2.7 X4005S8Z-2.7 (Note) X4005S8I-2.7 X4005S8IZ-2.7 (Note) ACW DAN ACX DAK X4005 F X4005 ZF X4005 G X4005 ZG 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) M8.118 8 Ld MSOP M8.118 (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 8 Ld SOIC MDP0027 (150 mil) (Pb-free) 8 Ld SOIC (150 mil) MDP0027 8 Ld SOIC MDP0027 (150 mil) (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN8113.1 May 11, 2006 X4003, X4005 PIN CONFIGURATION 8-Pin JEDEC SOIC, MSOP NC NC RESET VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA PIN DESCRIPTION Pin (SOIC/DIP) 1 2 3 Pin TSSOP 3 4 5 Pin (MSOP) Name NC NC No internal connections No internal connections Function 2 RESET/ RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/ RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a stop condition resets the watchdog timer. RESET/RESET goes active on powerup and remains active for 250ms after the power supply stabilizes. Ground Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop condition resets the watchdog timer. The absence of this procedure within the watchdog time out period results in RESET/RESET going active. Serial Clock. The serial clock controls the serial bus timing for data input and output. Write Protect. WP HIGH prevents changes to the watchdog timer setting. Supply voltage 4 5 6 7 3 4 VSS SDA 6 7 8 8 1 2 5 6 1 SCL WP VCC 4 FN8113.1 May 11, 2006 X4003, X4005 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4003/X4005 activates a power-on reset circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabilization of the oscillator. – It allows time for an FPGA to download its configuration prior to initialization of the circuit. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/RESET, allowing the system to begin operation. Low Voltage Monitoring During operation, the X4003/X4005 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL also toggles from HIGH to LOW (this is a start bit) followed by a stop condition prior to the expiration of the watchdog time out period to prevent a RESET/RESET signal. The state of two nonvolatile control bits in the control register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. Figure 1. Watchdog Restart .6µs SCL .6µs SDA Start Condition Stop Condition Restart Set VTRIP Level Sequence (VCC = desired VTRIP value) WP VP = 15-18V 01234567 SCL 01234567 01234567 SDA A0h 01h 00h VCC THRESHOLD RESET PROCEDURE The X4003/X4005 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4003/X4005 threshold may be adjusted. The procedure is described below, and uses the application of a nonvolatile control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. 5 FN8113.1 May 11, 2006 X4003, X4005 To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then write data 00hto address 01h. The stop bit following a valid write operation initiates the VTRIP programing sequence. Bring WP LOW to complete the operation. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then write 00h to address 03h. The stop bit of a valid write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V) WP VP = 15 - 18V 01234567 SCL 01234567 01234567 SDA A0h 03h 00h Figure 3. Sample VTRIP Reset Circuit VP 4.7K Adjust 1 8 Run SCL SDA µC 2 7 3 X4003/05 6 4 5 VTRIP Adj. RESET/ RESET 6 FN8113.1 May 11, 2006 X4003, X4005 Figure 4. VTRIP Programming Sequence VTRIP Programming Execute Reset VTRIP Sequence Set VCC = VCC Applied = Desired VTRIP New VCC Applied = Old VCC Applied - Error Execute Set VTRIP Sequence New VCC Applied = Old VCC applied + Error Execute Reset VTRIP Sequence Apply 5V to VCC Decrement VCC (VCC = VCC - 50mV) RESET pin goes active? YES Error ≥ Emax NO Measured VTRIP Desired VTRIP Error ≤ –Emax -Emax < Error < Emax DONE Emax = Maximum Allowable VTRIP Error Control Register The control register provides the user a mechanism for changing the watchdog timer settings. watchdog timer bits are nonvolatile and do not change when power is removed. The control register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a control register write operation. Only one data byte is allowed for each register write operation. Prior to writing to the control register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register" below. The user must issue a stop after sending the control byte to the register to initiate the nonvolatile cycle that stores WD1 and WD0. The X4003/X4005 will not acknowledge any data bytes written after the first byte is entered. The state of the control register can be read at any time by performing a serial read operation. Only one byte is read by each register read operation. The X4003/X4005 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. 7 0 6 WD1 5 WD0 4 0 3 0 2 RWEL 1 WEL 0 0 7 FN8113.1 May 11, 2006 X4003, X4005 RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the control register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the control register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes the control register will be ignored (no acknowledge will be issued after the data byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watchdog timer. The options are shown below. WD1 0 0 1 1 – Write a value to the control register that has all the control bits set to the desired state. This can be represented as 0xy0 0010 in binary, where xy are the WD bits. (Operation preceeded by a start and ended with a stop.) Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then the RWEL bit is set, but the WD1 and WD0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previous operations will not interrupt the register write operation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Serial Clock and Data Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 5. WD0 0 1 0 1 Watchdog Time Out Period 1.4 seconds 600 milliseconds 200 milliseconds Disabled (factory setting) Writing to the Control Register Changing any of the nonvolatile bits of the control register requires the following steps: – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop.) – Write a 06H to the control register to set both the register write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop.) 8 FN8113.1 May 11, 2006 X4003, X4005 Figure 5. Valid Data Changes on the SDA Bus SCL SDA Data Stable Data Change Data Stable Serial Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 6. Figure 6. Valid Start and Stop Conditions Serial Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. See Figure 6. SCL SDA Start Stop Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 7. The device will respond with an acknowledge after recognition of a start condition and the correct contents of the slave address byte. Acknowledge bits are also provided by the X4003/4005 after correct reception of the control register address byte, after receiving the byte written to the control register and after the second slave address in a read question (See Figure 8 and See Figure 9.) 9 FN8113.1 May 11, 2006 X4003, X4005 Figure 7. Acknowledge Response From Receiver SCL from Master Data Output from 1 8 9 Data Output from Receiver Start Acknowledge SERIAL WRITE OPERATIONS Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several parts: – a device type identifier that is always ‘1011’. – two bits of ‘0’. – one bit of the slave command byte is a R/W bit. The R/W bit of the slave address byte defines the operation to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Refer to Figure 8. – After loading the entire slave address byte from the SDA bus, the device compares the input slave byte data to the proper slave byte. Upon a correct compare, the device outputs an acknowledge on the SDA line. Write Control Register To write to the control register, the device requires the slave address byte and a byte address. This gives the master access to register. After receipt of the address Figure 8. Write Control Register Sequence Start byte, the device responds with an acknowledge, and awaits the data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. If WP is HIGH, the control register cannot be changed. A write to the control register will suppress the acknowledge bit and no data in the control register will change. With WP low, a second byte written to the control register terminates the operation and no write occurs. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. SDA Bus Signals from the Slave 10 11 0 010 A C K 11111111 A C K A C K 10 Stop Signals from the Master Slave Address Byte Address Data FN8113.1 May 11, 2006 X4003, X4005 Serial Read Operations The read operation allows the master to access the control register. To conform to the I2C standard, prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the byte address. After acknowledging receipt of the byte address, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit control register. The master terminates the read operation by Figure 9. Control Register Read Sequence Signals from the Master SDA Bus Signals from the Slave S t a r t Slave Address Byte Address S t a r t Slave Address S t o p not responding with an acknowledge and then issuing a stop condition. Refer to Figure 9 for the address, acknowledge, and data transfer sequences. Operational Notes The device powers-up in the following state: – The device is in the low power standby state. – The WEL bit is set to ‘0’. In this state it is not possible to write to the device. – SDA pin is the input mode. RESET/RESET signal is active for tPURST. 1 0 11 0 010 A C K 11111111 A C K 10 110 011 A C K Data Data Protection The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow a write operation. – The proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. – A three step sequence is required before writing into the control register to change watchdog timer or block lock settings. – The WP pin, when held HIGH, prevents all writes to the control register. – Communication to the device is inhibited below the VTRIP voltage. – Command to change the control register are terminated if in-progress when RESET/RESET go active. Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 11 FN8113.1 May 11, 2006 X4003, X4005 ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0°C -40°C Max. 70°C +85°C Option -1.8 -2.7 and -2.7A Blank and -4.5A Supply Voltage Limits 1.8V to 3.6V 2.7V to 5.5V 4.5V to 5.5V D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) VCC = 1.8 to 3.6V Symbol ICC(1) ICC2(1) ICC3(2) ICC4(2) ICC5(2) ILI ILO VIL(3) VIH(3) VHYS VCC = 2.7 to 5.5V Min Max 1.0 3.0 1 1 20 10 10 -0.5 VCC x 0.3 VCC + 0.5 Parameter Active supply current read control register Active supply current write control register Operating current AC (WDT off) Operating current DC (WDT off) Operating current DC (WDT on) Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Schmitt trigger input hysteresis fixed input level VCC related level Output LOW voltage Min Max 0.5 1.5 1 1 10 10 10 Unit mA mA µA µA µA µA µA V V V Test Conditions fSCL = 400kHz nonvolatile, SDA = Open VSDA = VSCL = VCC Others = GND or VSB VIN = GND to VCC VSDA = GND to VCC Device is in Standby(2) -0.5 VCC x 0.3 VCC x 0.7 VCC + 0.5 VCC x 0.7 0.2 .05 x VCC 0.4 0.2 .05 x VCC VOL 0.4 V IOL = 3.0mA (2.7-5.5V) IOL = 1.8mA (1.8-3.6V) Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte. (3) VIL min. and VIH max. are for reference only and are not tested. 12 FN8113.1 May 11, 2006 X4003, X4005 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Symbol COUT CIN Note: (4) (4) Parameter Output capacitance (SDA, RESET/RESET) Input capacitance (SCL, WP) Max. 8 6 Unit pF pF Test Conditions VOUT = 0V VIN = 0V (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V 1533Ω SDA 100pF For VOL = 0.4V and IOL = 3 mA RESET RESET 100pF 5V 4.6kΩ A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing levels Output load 0.1VCC to 0.9VCC 10ns 0.5VCC Standard output load A.C. CHARACTERISTICS (Continued)(Over recommended operating conditions, unless otherwise specified) 100kHz Symbol fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF tSU:WP tHD:WP Cb SCL clock frequency Pulse width suppression time at inputs SCL LOW to SDA data out valid Time the bus free before start of new transmission Clock LOW time Clock HIGH time Start condition setup time Start condition hold time Data in setup time Data in hold time Stop condition setup time Data output hold time SDA and SCL rise time SDA and SCL fall time WP setup time WP hold time Capacitive load for each bus line 0.4 0 400 400kHz Min. 0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 0.9 Parameter Min. 0 n/a 0.1 4.7 4.7 4.0 4.7 4.0 250 5.0 0.6 50 Max. 100 n/a 0.9 Max. 400 Unit kHz ns µs µs µs µs µs µs ns µs µs ns 1000 300 20 20 +.1Cb(6) +.1Cb(6) 0.6 0 300 300 ns ns µs µs 400 pF Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF. 13 FN8113.1 May 11, 2006 X4003, X4005 TIMING DIAGRAMS Bus Timing tF SCL tSU:STA SDA IN tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR tA SDA OUT tDH tBUF WP Pin Timing Start SCL Clk 1 Slave Address Byte SDA IN tSU:WP WP tHD:WP Clk 9 Write Cycle Timing SCL SDA 8th Bit of Last Byte ACK tWC Stop Condition Start Condition Nonvolatile Write Cycle Timing Symbol tWC(7) Note: Parameter Write cycle time Min. Typ.(1) 5 Max. 10 Unit ms (7) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 14 FN8113.1 May 11, 2006 X4003, X4005 Power-Up and Power-Down Timing VCC 0 Volts tR RESET VTRIP tPURST tRPD VRVALID tPURST tF RESET VRVALID RESET/RESET Output Timing Symbol VTRIP Parameter Reset trip point voltage, X4003-4.5A, X4005-4.5A Reset trip point voltage, X4003, X4005 Reset trip point voltage, X4003-2.7A, X4005-2.7A Reset trip point voltage, X4003-2.7, X4005-2.7 Reset trip point voltage, X4003-1.8, X4005-1.8 Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC Min. 4.5 4.25 2.85 2.55 1.7 100 10 0.1 1 Typ. 4.62 4.38 2.92 2.62 1.75 200 Max. 4.75 4.5 3.0 2.7 1.8 400 500 Unit V V V tPURST tRPD(8) tF(8) tR (8) ms ns ms ns V VRVALID Note: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET/RESET Timing SCL SDA tCST RESET tWDO RESET tRST tWDO tRST 15 FN8113.1 May 11, 2006 X4003, X4005 RESET/RESET Output Timing Symbol tWDO Parameter Watchdog time out period, WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset time out Min. Typ. OFF 200 600 1.4 200 Max. Unit 100 450 1 400 100 300 800 2 400 ms ms sec ns ms tCST tRST VTRIP Programming Timing Diagram VTRIP tTHD tTSU VP WP tVPO tVPH tVPS SCL tRP SDA 00h 01h or 03h A0h VCC (VTRIP) VTRIP Programming Parameters Parameter tVPS tVPH tTSU tTHD tWC tVPO tRP VP VTRAN Vta1 Vta2 Vtr Vtv Description VTRIP program enable voltage setup time VTRIP program enable voltage hold time VTRIP setup time VTRIP hold (stable) time VTRIP write cycle time VTRIP program enable voltage off time (between successive adjustments) VTRIP program recovery period (between successive adjustments) Programming voltage VTRIP programmed voltage range Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.) Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP. Programmed at 25°C.) VTRIP program voltage repeatability (Successive program operations. Programmed at 25°C.) VTRIP program variation after programming (0-75°C). (programmed at 25°C) Min. Max. 1 1 1 10 10 0 10 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 Unit µs µs µs ms ms µs ms V V V mV mV mV VTRIP programming parameters are periodically sampled and are not 100% tested. 16 FN8113.1 May 11, 2006 X4003, X4005 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 -BE INCHES SYMBOL A ABC MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03 MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028 INDEX AREA 12 TOP VIEW 0.20 (0.008) A1 A2 4X θ 0.25 (0.010) GAUGE PLANE SEATING PLANE -C- R1 R b c D E1 A A2 4X θ L L1 e E L L1 N R 0.026 BSC 0.65 BSC A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE 0.037 REF 0.95 REF C a C L E1 C R1 0 SIDE VIEW 15o 6o α -B- 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 17 FN8113.1 May 11, 2006 X4003, X4005 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8113.1 May 11, 2006