X5045

® X5043, X5045 4K, 512 x 8 Bit Data Sheet September 16, 2005 FN8126.1 CPU Supervisor with 4K SPI EEPROM These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Features • Low VCC Detection and Reset Assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V • Selectable Time Out Watchdog Timer • Long Battery Life with Low Power Consumption - 3.3V, IOH = –1.0mA 2V < VCC ≤ 3.3V, IOH = –0.4mA VCC ≤ 2V, IOH = –0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 -0.5 VCC x 0.7 0.1 0.1 10 10 VCC x 0.3 VCC + 0.5 0.4 VIH VOL VOH1 VOH2 VOH3 VOLRS 0.4 V Capacitance SYMBOL COUT CIN NOTES: (2) TA = +25°C, f = 1MHz, VCC = 5V TEST CONDITIONS VOUT = 0V VIN = 0V MAX 8 6 UNIT pF pF Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP) (2) 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 3. SCK frequency measured from VCC x 0.1/VCC x 0.9 13 FN8126.1 September 16, 2005 X5043, X5045 Equivalent A.C. Load Circuit at 5V VCC 5V 1.64kΩ Output 1.64kΩ 30pF RESET/RESET 30pF 5V 4.6kΩ A.C. Test Conditions Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 AC Electrical Specifications SYMBOL DATA INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(4) tFI(4) tCS tWC(5) Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time (Over recommended operating conditions, unless otherwise specified) 2.7V–5.5V PARAMETER MIN MAX UNIT 0 300 150 150 130 130 30 30 3.3 MHz ns ns ns ns ns ns ns 2 2 100 10 µs µs ns ms Data Output Timing 2.7–5.5V SYMBOL fSCK tDIS tV tHO tRO tFO (4) PARAMETER Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time MIN 0 MAX 3.3 150 120 UNIT MHz ns ns ns 0 50 50 ns ns (4) NOTES: 4. This parameter is periodically sampled and not 100% tested. 5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 14 FN8126.1 September 16, 2005 X5043, X5045 Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN Serial Input Timing tCS CS tLEAD SCK tSU SI MSB In tH tRI tFI tLAG LSB In High Impedance SO Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 15 FN8126.1 September 16, 2005 X5043, X5045 Power-Up and Power-Down Timing VCC VTRIP 0 Volts tR RESET (X5043) tPURST tPURST tF tRPD VTRIP RESET (X5045) RESET Output Timing SYMBOL VTRIP PARAMETER Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC 10 0.1 1 MIN 4.5 4.25 2.85 2.55 100 TYP 4.62 4.38 2.92 2.62 200 MAX 4.75 4.5 3.0 2.7 400 500 UNIT V tPURST tRPD tF (6) ms ns µs ns V (6) (6) tR VRVALID NOTE: 6. This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing CS/WDI tCST RESET (5043) tWDO RESET (5045) tRST tWDO tRST RESET/RESET Output Timing SYMBOL tWDO PARAMETER Watchdog Time Out Period, WD1 = 1, WD0 = 1 (default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out MIN TYP OFF 200 600 1.4 MAX UNIT 100 450 1 400 100 300 800 2 ms ms sec ns tCST tRST 200 400 ms 16 FN8126.1 September 16, 2005 X5043, X5045 VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU VP tTHD WP tVPS tVPH tVPO tPCS CS tRP SCK SI 06h 02h 01h or 03h VTRIP Programming Parameters PARAMETER tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vtv DESCRIPTION VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Programming CS inactive time VTRIP Setup time VTRIP Hold (stable) time VTRIP Write Cycle Time VTRIP Program Enable Voltage Off time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) 0 10 15 1.7 -25 18 4.75 +25 MIN 1 1 1 1 10 10 MAX UNIT µs µs µs µs ms ms µs ms V V mV VTRIP programming parameters are periodically sampled and are not 100% tested. 17 FN8126.1 September 16, 2005 X5043, X5045 Packaging Information 8-Lead Miniature Small Outline Gull Wing Package Type M 0.118 ± 0.002 (3.00 ± 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ. R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 0.030 (0.76) 0.0216 (0.55) 0.036 (0.91) 0.032 (0.81) 7° Typ. 0.040 ± 0.002 (1.02 ± 0.05) 0.008 (0.20) 0.004 (0.10) 0.0256" Typical 0.007 (0.18) 0.005 (0.13) 0.150 (3.81) Ref. 0.193 (4.90) Ref. 0.025" Typical 0.220" FOOTPRINT 0.020" Typical 8 Places NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS) 18 FN8126.1 September 16, 2005 X5043, X5045 Packaging Information 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51) Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18) 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Typ. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 19 FN8126.1 September 16, 2005 X5043, X5045 Packaging Information 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050"Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250" 0.050" Typical FOOTPRINT 0.030" Typical 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 FN8126.1 September 16, 2005 X5043, X5045 Packaging Information 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° .019 (.50) .029 (.75) Detail A (20X) Seating Plane .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8126.1 September 16, 2005