X5163PZ-2.7

DATASHEET X5163, X5165 FN8128 Rev 4.00 August 13, 2015 CPU Supervisor with 16Kbit SPI EEPROM Description Features These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. • Selectable watchdog timer Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. • Low VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Determine watchdog or low voltage reset with a volatile flag bit • Long battery life with low power consumption - 3.3V, IOL = 2.1mA 0.4 V VOL2 Output LOW Voltage 2V < VCC  3.3V, IOL = 1mA 0.4 V VOL3 Output LOW Voltage VCC  2V, IOL = 0.5mA 0.4 V VOH1 Output HIGH Voltage VCC > 3.3V, IOH = –1.0mA VCC - 0.8 V VOH2 Output HIGH Voltage 2V < VCC  3.3V, IOH = –0.4mA VCC - 0.4 V VOH3 Output HIGH Voltage VCC  2V, IOH = –0.25mA VCC - 0.2 V VOLS Reset Output LOW Voltage IOL = 1mA 0.4 Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL COUT CIN (2) (2) TEST MAX. UNIT CONDITIONS Output Capacitance (SO, RESET, RESET) 8 pF VOUT = 0V Input Capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. FN8128 Rev 4.00 August 13, 2015 Page 12 of 22 V X5163, X5165 5V A.C. Test Conditions 5V 3.3k 1.64k OUTPUT RESET/RESET 1.64k Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 30pF 100pF FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC AC Electrical Specifications Serial Input Timing (Over operating conditions unless otherwise specified.) 2.7-5.5V SYMBOL PARAMETER MIN MAX UNIT 0 2 MHz fSCK Clock Frequency tCYC Cycle Time 500 ns tLEAD CS Lead Time 250 ns tLAG CS Lag Time 250 ns tWH Clock HIGH Time 200 ns tWL Clock LOW Time 200 ns tSU Data Setup Time 50 ns tH Data Hold Time 50 ns (3) Input Rise Time 100 ns (3) Input Fall Time 100 ns tRI tFI tCS tWC (4) CS Deselect Time 500 ns Write Cycle Time 10 ms tCS CS tLEAD tLAG SCK tSU SI SO tH tRI MSB IN tFI LSB IN HIGH IMPEDANCE FIGURE 11. SERIAL INPUT TIMING FN8128 Rev 4.00 August 13, 2015 Page 13 of 22 X5163, X5165 AC Electrical Specifications Serial Output Timing(Over operating conditions unless otherwise specified.) 2.7-5.5V SYMBOL PARAMETER MIN MAX UNIT 0 2 MHz fSCK Clock Frequency tDIS Output Disable Time 250 ns Output Valid from Clock Low 200 ns tV tHO 0 ns Output Rise Time 100 ns (3) Output Fall Time 100 ns tRO tFO Output Hold Time (3) NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. CS tCYC tWH tLAG SCK tV SO SI tHO MSB OUT tWL MSB–1 OUT tDIS LSB OUT ADDR LSB IN TABLE 3. SERIAL OUTPUT TIMING VTRIP VTRIP VCC tPURST 0 Volts tPURST tR tF tRPD RESET (X5163) RESET (X5165) TABLE 4. POWER-UP AND POWER-DOWN TIMING FN8128 Rev 4.00 August 13, 2015 Page 14 of 22 X5163, X5165 RESET Output Timing SYMBOL VTRIP VTH tPURST tRPD tF (5) PARAMETER Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A Reset Trip Point Voltage, X5163, X5165 Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A Reset Trip Point Voltage, X5163-2.7, X5165-2.7 MIN TYP MAX UNIT 4.5 4.25 2.85 2.55 4.63 4.38 2.92 2.63 4.75 4.5 3.0 2.7 V VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) 20 Power-up Reset Time Out 100 200 VCC Detect to Reset/Output mV 280 ms 500 ns (5) VCC Fall Time 100 µs (5) VCC Rise Time 100 µs Reset Valid VCC 1 V tR VRVALID NOTES: 5. This parameter is periodically sampled and not 100% tested. 6. Typical values not tested. CS/WDI tCST RESET tWDO tWDO tRST tRST RESET FIGURE 12. CS/WDI VS. RESET/RESET TIMING RESET/RESET Output Timing SYMBOL PARAMETER MIN TYP MAX UNIT 200 600 1.4 300 800 2 ms ms sec tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 1 tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Time Out 100 FN8128 Rev 4.00 August 13, 2015 ns 200 300 ms Page 15 of 22 X5163, X5165 tTHD VCC VTRIP tTSU tVPS CS tRP tP tVPH tVPH tVPS tVPO VP SCK VP tVPO SI FIGURE 13. VTRIP SET CONDITIONS tTHD VCC VTRIP tTSU tVPS CS SCK tVPS tRP tP tVP1 tVPH tVPO VCC VP tVPO SI FIGURE 14. VTRIP RESET CONDITIONS FN8128 Rev 4.00 August 13, 2015 Page 16 of 22 X5163, X5165 VTRIP Programming Specifications: VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP Program Voltage Setup time 1 µs tVPH SCK VTRIP Program Voltage Hold time 1 µs VTRIP Program Pulse Width 1 µs tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 ms tWC VTRIP Write Cycle Time tRP VTRIP Program Cycle Recovery Period (Between successive programming cycles) 10 ms tVPO SCK VTRIP Program Voltage Off time before next cycle 0 ms Programming Voltage 15 18 V VTRIP Programed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV tP VP VTRAN 10 ms VTRIP programming parameters are periodically sampled and are not 100% tested. FN8128 Rev 4.00 August 13, 2015 Page 17 of 22 X5163, X5165 18 1.9 WATCHDOG TIMER ON (VCC = 5V) 16 1.8 14 RESET (SECONDS) 1.7 ISB (µA) 12 WATCHDOG TIMER ON (VCC = 5V) 10 8 6 4 WATCHDOG TIMER OFF (VCC = 3V, 5V) 2 25 TEMP (°C) 90°C 1.4 1.3 1.2 1 90 1.7 2.4 3.1 4.5 5.2 FIGURE 16. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1) 5.025 0.8 VTRIP = 5V 5.000 0.75 RESET (SECONDS) 4.975 3.525 VTRIP = 3.5V 3.500 3.475 2.525 -40°C 0.7 25°C 0.65 90°C 0.6 0.55 0.5 VTRIP = 2.5V 2.500 0.45 2.475 0 25 1.7 85 2.4 3.1 FIGURE 17. VTRIP vs. Temperature (programmed at 25°C) 200 195 195 RESET (SECONDS) 205 200 190 185 180 175 170 175 170 160 FIGURE 19. tPURST VS. TEMPERATURE FN8128 Rev 4.00 August 13, 2015 90°C 180 160 90 -40°C 185 165 25 5.2 25°C 190 165 DEGREES °C 4.5 FIGURE 18. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0) 205 -40 3.8 VOLTAGE TEMPERATURE TIME (MS) 3.8 VOLTAGE FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB) VOLTAGE 25°C 1.5 1.1 0 -40 -40°C 1.6 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE FIGURE 20. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1) Page 18 of 22 X5163, X5165 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION August 13, 2015 FN8128.4 CHANGE - Ordering Information Table on page 2. - Added Revision History beginning with Rev 1. - Added About Intersil Verbiage. - Updated POD MDP0027 to latest revision changes are as follow: Added dimensions (INCHES) to table. - Updated POD MDP0031 to latest revision changes are as follow: Added dimensions (INCHES) to table. - Updated POD M14.173 to most current version changes are as follow: Updated drawing to remove table and added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8128 Rev 4.00 August 13, 2015 Page 19 of 22 X5163, X5165 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 NOTES: Rev. M 2/07 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN8128 Rev 4.00 August 13, 2015 Page 20 of 22 X5163, X5165 Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. FN8128 Rev 4.00 August 13, 2015 Page 21 of 22 X5163, X5165 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN FN8128 Rev 4.00 August 13, 2015 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. Page 22 of 22