X5165

® X5163, X5165 Data Sheet June 1, 2006 FN8128.3 CPU Supervisor with 16Kbit SPI EEPROM Description These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. Features • Selectable watchdog timer • Low VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Determine watchdog or low voltage reset with a volatile flag bit • Long battery life with low power consumption - 3.3V, IOL = 2.1mA 2V < VCC ≤ 3.3V, IOL = 1mA VCC ≤ 2V, IOL = 0.5mA VCC > 3.3V, IOH = –1.0mA 2V < VCC ≤ 3.3V, IOH = –0.4mA VCC ≤ 2V, IOH = –0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4 V Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL COUT CIN NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. (2) TEST Output Capacitance (SO, RESET, RESET) Input Capacitance (SCK, SI, CS, WP) MAX. 8 6 UNIT pF pF CONDITIONS VOUT = 0V VIN = 0V (2) 12 FN8128.3 June 1, 2006 X5163, X5165 5V 5V A.C. Test Conditions Input pulse levels 3.3kΩ VCC x 0.1 to VCC x 0.9 10ns VCC x0.5 1.64kΩ OUTPUT RESET/RESET 100pF Input rise and fall times Input and output timing level 30pF 1.64kΩ FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC AC Electrical Specifications SYMBOL fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time Serial Input Timing (Over operating conditions unless otherwise specified.) 2.7-5.5V PARAMETER MIN 0 500 250 250 200 200 50 50 100 100 500 10 MAX 2 UNIT MHz ns ns ns ns ns ns ns ns ns ns ms tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO HIGH IMPEDANCE FIGURE 11. SERIAL INPUT TIMING 13 FN8128.3 June 1, 2006 X5163, X5165 AC Electrical Specifications Serial Output Timing(Over operating conditions unless otherwise specified.) 2.7-5.5V SYMBOL fSCK tDIS tV tHO tRO tFO NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. (3) PARAMETER Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time MIN 0 MAX 2 250 200 UNIT MHz ns ns ns 0 100 100 ns ns (3) CS tCYC SCK tV SO MSB OUT MSB–1 OUT tHO tWL LSB OUT tDIS tWH tLAG SI ADDR LSB IN TABLE 3. SERIAL OUTPUT TIMING VTRIP VCC 0 Volts tPURST tPURST tR RESET (X5163) VTRIP tF tRPD RESET (X5165) TABLE 4. POWER-UP AND POWER-DOWN TIMING 14 FN8128.3 June 1, 2006 X5163, X5165 RESET Output Timing SYMBOL VTRIP PARAMETER Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A Reset Trip Point Voltage, X5163, X5165 Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A Reset Trip Point Voltage, X5163-2.7, X5165-2.7 VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up Reset Time Out VCC Detect to Reset/Output VCC Fall Time VCC Rise Time Reset Valid VCC 100 100 1 100 MIN 4.5 4.25 2.85 2.55 TYP 4.63 4.38 2.92 2.63 20 200 280 500 MAX 4.75 4.5 3.0 2.7 UNIT V VTH tPURST tRPD(5) tF(5) tR(5) VRVALID NOTES: mV ms ns µs µs V 5. This parameter is periodically sampled and not 100% tested. 6. Typical values not tested. CS/WDI tCST RESET tWDO tRST tWDO tRST RESET FIGURE 12. CS/WDI VS. RESET/RESET TIMING RESET/RESET Output Timing SYMBOL tWDO PARAMETER Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out MIN 100 450 1 400 100 200 300 TYP 200 600 1.4 MAX 300 800 2 UNIT ms ms sec ns ms tCST tRST 15 FN8128.3 June 1, 2006 X5163, X5165 tTHD VCC VTRIP tTSU tVPS tP tVPH tRP CS tVPS VP tVPH tVPO SCK VP SI tVPO FIGURE 13. VTRIP SET CONDITIONS tTHD VCC VTRIP tTSU tVPS tP tVP1 tRP CS tVPS tVPH tVPO SCK VCC VP SI tVPO FIGURE 14. VTRIP RESET CONDITIONS 16 FN8128.3 June 1, 2006 X5163, X5165 VTRIP Programming Specifications: VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv SCK VTRIP Program Voltage Setup time SCK VTRIP Program Voltage Hold time VTRIP Program Pulse Width VTRIP Level Setup time VTRIP Level Hold (stable) time VTRIP Write Cycle Time VTRIP Program Cycle Recovery Period (Between successive programming cycles) SCK VTRIP Program Voltage Off time before next cycle Programming Voltage VTRIP Programed Voltage Range Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.) Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25°C.) VTRIP Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.) VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 DESCRIPTION MIN 1 1 1 10 10 10 MAX UNIT µs µs µs µs ms ms ms ms V V V mV mV mV VTRIP programming parameters are periodically sampled and are not 100% tested. 17 FN8128.3 June 1, 2006 X5163, X5165 18 16 14 12 ISB (µA) 10 8 6 4 2 0 -40 25 TEMP (°C) 90 WATCHDOG TIMER OFF (VCC = 3V, 5V) WATCHDOG TIMER ON (VCC = 5V) RESET (SECONDS) WATCHDOG TIMER ON (VCC = 5V) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE 90°C 25°C -40°C FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB) 5.025 5.000 4.975 VOLTAGE 3.525 3.500 3.475 2.525 2.500 2.475 0 25 TEMPERATURE 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V FIGURE 16. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1) 0.8 0.75 RESET (SECONDS) 0.7 0.65 0.6 0.55 0.5 0.45 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE 90°C 25°C -40°C FIGURE 17. VTRIP vs. Temperature (programmed at 25°C) 205 200 195 FIGURE 18. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0) 205 200 195 RESET (SECONDS) 190 185 180 175 170 165 160 1.7 2.4 3.1 VOLTAGE 3.8 4.5 5.2 90°C 25°C -40°C 190 TIME (MS) 185 180 175 170 165 160 -40 25 DEGREES °C 90 FIGURE 19. tPURST VS. TEMPERATURE FIGURE 20. tWDO VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1) 18 FN8128.3 June 1, 2006 X5163, X5165 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01 19 FN8128.3 June 1, 2006 X5163, X5165 Plastic Dual-In-Line Packages (PDIP) D E N PIN #1 INDEX SEATING PLANE L e b A2 A c E1 A1 NOTE 5 eA eB 1 2 b2 N/2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN ±0.005 ±0.002 +0.010/-0.015 +0.004/-0.002 ±0.010 +0.015/-0.010 ±0.005 Basic Basic ±0.025 ±0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES 20 FN8128.3 June 1, 2006 X5163, X5165 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8128.3 June 1, 2006