®
X5168, X5169
(Replaces X25268, X25169)
Data Sheet September 16, 2005 FN8130.1
CPU Supervisor with 16Kbit SPI EEPROM
These devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions by holding RESET/RESET active when VCC falls below a minimum VCC trip point. RESET/RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision.
Features
• Low VCC Detection and Reset Assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Long Battery Life with Low Power Consumption - 3.3V, IOH = -1.0mA 2V < VCC ≤ 3.3V, IOH = -0.4mA VCC ≤ 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4 0.1 0.1 MIN TYP MAX 5 0.4 1 10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4 UNIT mA mA µA µA µA V V V V V V V V V
VCC standby current WDT = OFF Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
Capacitance
SYMBOL COUT (NOTE 2)
TA = +25°C, f = 1MHz, VCC = 5V. TEST CONDITIONS VOUT = 0V VIN = 0V MAX. 8 6 UNIT pF pF
Output capacitance (SO, RESET/RESET)
CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP) NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested.
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FN8130.1 September 16, 2005
X5168, X5169
Equivalent A.C. Load Circuit at 5V VCC
5V 5V
A.C. Test Conditions
Input pulse levels Input rise and fall times VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
2.06kΩ
4.6kΩ
Input and output timing level
Output 3.03kΩ 100pF
RESET/RESET 30pF
AC Electrical Specifications
SYMBOL SERIAL INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock frequency Cycle time CS lead time CS lag time
(Over recommended operating conditions, unless otherwise specified.) 2.7-5.5V PARAMETER MIN MAX UNIT
0 500 250 250 200 200 50 50
2
MHz ns ns ns ns ns ns ns
Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time
100 100 500 10
ns ns ns ms
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FN8130.1 September 16, 2005
X5168, X5169
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
High Impedance
Serial Output Timing
2.7-5.5V SYMBOL fSCK tDIS tV tHO tRO(3) tFO(3) Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 100 100 PARAMETER MIN 0 MAX 2 250 200 UNIT MHz ns ns ns ns ns
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
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FN8130.1 September 16, 2005
X5168, X5169
Power-Up and Power-Down Timing
VTRIP VCC 0 Volts tR RESET (X5168) tPURST tPURST tF tRPD VTRIP
RESET (X5169)
RESET Output Timing
SYMBOL VTRIP PARAMETER Reset trip point voltage, X5168-4.5A, X5168-4.5A Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC 100 100 1 100 MIN 4.5 4.25 2.85 2.55 TYP 4.63 4.38 2.93 2.63 20 200 280 500 MAX 4.75 4.5 3.0 2.7 UNIT V
VTH tPURST tRPD tF
(5)
mV ms ns µs µs V
(5) (5)
tR
VRVALID Note:
(5) This parameter is periodically sampled and not 100% tested.
VTRIP Set Conditions
tTHD VCC VTRIP tTSU tVPS tP tVPH tRP
CS
tVPS VP
tVPH
tVPO
SCK VP SI tVPO
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FN8130.1 September 16, 2005
X5168, X5169
VTRIP Reset Conditions
VCC* tRP tVPS tP tVP1
CS
tVPS
tVPH
tVPO
SCK
VCC
VP SI
tVPO
*VCC > Programmed VTRIP
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
PARAMETER tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) VTRIP Program variation after programming (0-75°C). (programmed at 25°C) 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 DESCRIPTION MIN 1 1 1 10 10 10 MAX UNIT µs µs µs µs ms ms ms ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
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FN8130.1 September 16, 2005
X5168, X5169 Typical Performance
VCC Supply Current vs. Temperature (ISB)
18 16 14 Watchdog Timer On (VCC = 5V) Time (ms) 12 Isb (µA) 10 8 6 4 2 0 -40C Watchdog Timer Off (VCC = 3V, 5V) Watchdog Timer On (VCC = 5V)
tPURST vs. Temperature
205 200 195 190 185 180 175 170 165 160 -40 90C 25 Degrees °C 90
25C Temp (°C)
VTRIP vs. Temperature (programmed at 25°C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V
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FN8130.1 September 16, 2005
X5168, X5169 Packaging Information
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0° 15°
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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FN8130.1 September 16, 2005
X5168, X5169 Packaging Information
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7°
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45° 0.020 (0.50)
0.050" Typical
0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8130.1 September 16, 2005
X5168, X5169 Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0° - 8° .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN8130.1 September 16, 2005
