X5329V14IT1

DATASHEET X5328, X5329 FN8132 Rev 3.00 Nov 11, 2021 CPU Supervisor with 32Kbit SPI EEPROM The X5328 and X5329 devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions by holding RESET/RESET active when VCC falls below a minimum VCC trip point. RESET/RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, the unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision. FEATURES • Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Long battery life with low power consumption — 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC  3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VCC  2V, IOL = 0.5mA VOH1 Output HIGH Voltage VCC - 0.8 V VCC > 3.3V, IOH = -1.0mA VOH2 Output HIGH Voltage VCC - 0.4 V 2V < VCC  3.3V, IOH = -0.4mA VOH3 Output HIGH Voltage VCC - 0.2 V VCC  2V, IOH = -0.25mA VOLS Reset Output LOW Voltage V IOL = 1mA 0.4 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT(2) CIN(2) Test Max. Unit Conditions Output Capacitance (SO, RESET, RESET) 8 pF VOUT = 0V Input Capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. FN8132 Rev 3.00 Nov 11, 2021 Page 11 of 18 X5328, X5329 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC 5V 5V 4.6k 2.06k Output A.C. TEST CONDITIONS Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x0.5 RESET/RESET 3.03k 100pF 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 2.7-5.5V Symbol Parameter Min. Max. Unit 0 2 MHz fSCK Clock Frequency tCYC Cycle Time 500 ns tLEAD CS Lead Time 250 ns tLAG CS Lag Time 250 ns tWH Clock HIGH Time 200 ns tWL Clock LOW Time 250 ns tSU Data Setup Time 50 ns tH Data Hold Time 50 ns tRI(3) Input Rise Time 100 ns tFI(3) Input Fall Time 100 ns tCS CS Deselect Time tWC (4) Write Cycle Time FN8132 Rev 3.00 Nov 11, 2021 500 ns 10 ms Page 12 of 18 X5328, X5329 Serial Input Timing tCS CS tLEAD tLAG SCK tSU tH SI tRI tFI MSB IN LSB IN High Impedance SO Serial Output Timing 2.7-5.5V Symbol Parameter Min. Max. Unit 0 2 MHz fSCK Clock Frequency tDIS Output Disable Time 250 ns Output Valid from Clock Low 250 ns tV tHO Output Hold Time tRO(3) Output Rise Time 100 ns Output Fall Time 100 ns tFO (3) 0 ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC tWH tLAG SCK tV SO SI MSB Out tHO MSB–1 Out tWL tDIS LSB Out ADDR LSB IN FN8132 Rev 3.00 Nov 11, 2021 Page 13 of 18 X5328, X5329 Power-Up and Power-Down Timing VCC VTRIP VTRIP tPURST 0 Volts tF tPURST tRPD tR RESET (X5328) RESET (X5329) RESET Output Timing Symbol VTRIP VTH Parameter Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A Reset Trip Point Voltage, X5328, X5329 Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A Reset Trip Point Voltage, X5328-2.7, X5329-2.7 Power-up Reset Time Out tRPD(5) VCC Detect to Reset/Output tF tR(5) VRVALID Note: Typ. Max. Unit 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 V VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) tPURST (5) Min. 20 100 200 mV 280 ms 500 ns VCC Fall Time 100 µs VCC Rise Time 100 µs 1 V Reset Valid VCC (5) This parameter is periodically sampled and not 100% tested. FN8132 Rev 3.00 Nov 11, 2021 Page 14 of 18 X5328, X5329 VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS CS tRP tP tVPH tVPH tVPS tVPO VP SCK VP tVPO SI VTRIP Reset Conditions VCC* tRP tVPS CS SCK tVPS tP tVP1 tVPH tVPO VCC VP tVPO SI *VCC > Programmed VTRIP FN8132 Rev 3.00 Nov 11, 2021 Page 15 of 18 X5328, X5329 VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter Description Min. Max. Unit tVPS SCK VTRIP Program Voltage Setup time 1 µs tVPH SCK VTRIP Program Voltage Hold time 1 µs VTRIP Program Pulse Width 1 µs tTSU VTRIP Level Setup time 10 µs tTHD VTRIP Level Hold (stable) time 10 ms tWC VTRIP Write Cycle Time tRP VTRIP Program Cycle Recovery Period (Between successive programming cycles) 10 ms tVPO SCK VTRIP Program Voltage Off time before next cycle 0 ms Programming Voltage 15 18 V VTRIP Programed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (Programmed at 25°C.) -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations.) (programmed at 25°C) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV tP VP VTRAN 10 ms VTRIP programming parameters are periodically sampled and are not 100% tested. FN8132 Rev 3.00 Nov 11, 2021 Page 16 of 18 X5328, X5329 TYPICAL PERFORMANCE tPURST vs. Temperature VCC Supply Current vs. Temperature (ISB) 205 2 200 195 Time (ms) Isb (µA) 190 (VCC = 3V, 5V) 1 185 180 175 170 165 160 -40 0 -40C 25C Temp°C 90C 25 Degrees °C 90 VTRIP vs. Temperature (programmed at 25°C) 5.025 VTRIP = 5V 5.000 4.975 Voltage 3.525 VTRIP = 3.5V 3.500 3.475 2.525 VTRIP = 2.5V 2.500 2.475 0 25 Temperature 85 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION Nov 11, 2021 3.00 Removed About Intersil section. Removed TSSOP and PDIP information from document. Updated Pin Configuration. Updated Ordering information table formatting. Oct16, 2015 2.00 Updated the Ordering Information table on page 2. Added Revision History and About Intersil sections. Replaced all Package Outline drawings with the most recent versions. FN8132 Rev 3.00 Nov 11, 2021 CHANGE Page 17 of 18 X5328, X5329 Package Outline Drawing For the most recent package outline drawing, see M8.15E. M8.15E 8 Lead Narrow Body Small Outline Plastic Package Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN8132 Rev 3.00 Nov 11, 2021 Page 18 of 18 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.