X5645S14-2.7A

® X5643, X5645 (Replaces X25643, X25645) Data Sheet July 18, 2005 FN8135.1 CPU Supervisor with 64Kbit SPI EEPROM FEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Determine watchdog or low voltage reset with a volatile flag bit • Long battery life with low power consumption — 3.3V, IOL = 2.1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4 2V < VCC ≤ 3.3V, IOH = -0.4mA V 10 FN8135.1 July 18, 2005 X5643, X5645 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT CIN (2) (2) Test Output Capacitance (SO, RESET/RESET) Input Capacitance (SCK, SI, CS, WP) Max. 8 6 Unit pF pF Conditions VOUT = 0V VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC 5V 2.06kΩ Output 3.03kΩ 100pF RESET/RESET 30pF 5V 4.6kΩ A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 2.7-5.5V Symbol fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time 500 10 Parameter Min. 0 500 250 250 200 250 50 50 Max. 2 Unit MHz ns ns ns ns ns ns ns 100 100 ns ns ns ms 11 FN8135.1 July 18, 2005 X5643, X5645 Serial Input Timing tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO High Impedance Serial Output Timing 2.7-5.5V Symbol fSCK tDIS tV tHO tRO(3) tFO(3) Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 100 100 Parameter Min. 0 Max. 2 250 250 Unit MHz ns ns ns ns ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN 12 FN8135.1 July 18, 2005 X5643, X5645 Power-Up and Power-Down Timing VTRIP VCC 0 Volts tR RESET (X5643) tPURST tPURST tF tRPD VTRIP RESET (X5645) RESET Output Timing Symbol VTRIP Parameter Reset trip point voltage, X5643-4.5A, X5643-4.5A Reset trip point voltage, X5643, X5645 Reset trip point voltage, X5643-2.7A, X5645-2.7A Reset trip point voltage, X5643-2.7, X5645-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC Min. 4.5 4.25 2.85 2.55 100 100 100 1 Typ. 4.63 4.38 2.93 2.63 20 200 Max. 4.75 4.5 3.0 2.7 280 500 Unit V VTH tPURST tRPD tF tR (5) (5) (5) mV ms ns µs µs V VRVALID Note: (5) This parameter is periodically sampled and not 100% tested. CS/WDI vs. RESET/RESET Timing CS/WDI tCST RESET tWDO tRST tWDO tRST RESET 13 FN8135.1 July 18, 2005 X5643, X5645 RESET/RESET Output Timing Symbol tWDO Parameter Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset time out Min. 100 450 1 400 100 Typ. 200 600 1.4 200 Max. 300 800 2 300 Unit ms ms sec ns ms tCST tRST VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS tP tVPH tRP CS tVPS VP tVPH tVPO SCK VP SI tVPO VTRIP Reset Conditions VCC* tRP tVPS tP tVP1 CS tVPS tVPH tVPO SCK VCC VP SI tVPO *VCC > Programmed VTRIP 14 FN8135.1 July 18, 2005 X5643, X5645 VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv Description SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) VTRIP Program Voltage repeatability (successive program operations) (programmed at 25°C) VTRIP program variation after programming (0-75°C). (programmed at 25°C) Min. 1 1 1 10 10 Max. Unit µs µs µs µs ms 10 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 ms ms ms V V V mV mV mV VTRIP programming parameters are periodically sampled and are not 100% tested. 15 FN8135.1 July 18, 2005 X5643, X5645 TYPICAL PERFORMANCE VCC Supply Current vs. Temperature (ISB) 18 16 14 Reset (seconds) 12 Isb (µA) 10 8 6 4 2 0 -40 25 Temp (°C) 90 Watchdog Timer Off (VCC = 3V, 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) tWDO vs. Voltage/Temperature (WD1, 0 = 1, 1) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 Voltage 4.5 5.2 90°C 25°C -40°C VTRIP vs. Temperature (programmed at 25°C) 5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0) 0.8 0.75 Reset (seconds) 0.7 0.65 0.6 0.55 0.5 0.45 90°C 25°C -40°C 85 1.7 2.4 3.1 3.8 Voltage 4.5 5.2 tPURST vs. Temperature 205 200 195 tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1) 205 200 195 Reset (seconds) 190 185 180 175 170 165 160 1.7 2.4 3.1 3.8 4.5 5.2 90°C 25°C -40°C 190 Time (ms) 185 180 175 170 165 160 -40 25 Degrees °C 90 Voltage 16 FN8135.1 July 18, 2005 X5643, X5645 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51) Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18) 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Typ. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 17 FN8135.1 July 18, 2005 X5643, X5645 PACKAGING INFORMATION 14-Lead Plastic Small Outline Gullwing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050" Typical 0.010 (0.25) 0.020 (0.50) X 45° 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.030" Typical 14 Places 0.250" FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 18 FN8135.1 July 18, 2005 X5643, X5645 Ordering Information VCC Range 4.5-5.5V VTRIP Range 4.5.4.75 Package 8 pin PDIP 14L SOIC Operating Temperature Range 0-70°C 0-70°C -40-85°C 0-70°C 0-70°C -40-85°C 0-70°C 0-70°C Part Number RESET (Active LOW) X5643P-4.5A X5643S14-4.5A X5643S14I-4.5A X5643P X5643S14 X5643S14I X5643S14-2.7A X5643S14-2.7 Part Number RESET (Active HIGH) X5645P-4.5A X5645S14-4.5A X5645S14I-4.5A X5645P X5645S14 X5645S14I X5645S14-2.7A X5645S14-2.7 4.5-5.5V 4.25.4.5 8 pin PDIP 14L SOIC 2.7-5.5V 2.7-5.5V 2.85-3.0 2.55-2.7 14L SOIC 14L SOIC Part Mark Information X5643/45 W X P = 8-Lead PDIP S14 = 14 Lead SOIC Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 I = 5V ±10%, -40°C to +85°C, VTRIP = 4.25-4.5 AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN8135.1 July 18, 2005