X5648

® X5648, X5649 (Replaces X25648, X25649) Data Sheet March 17, 2005 FN8136.0 CPU Supervisor with 64Kbit SPI EEPROM FEATURES • Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Long battery life with low power consumption — 3.3V, IOH = –1.0mA V CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol COUT CIN (2) (2) Test Output capacitance (SO, RESET/RESET) Input capacitance (SCK, SI, CS, WP) Max. 8 6 Unit pF pF Conditions VOUT = 0V VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 10 FN8136.0 March 17, 2005 X5648, X5649 EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC 5V 2.06kΩ Output 3.03kΩ 100pF RESET/RESET 30pF 5V 4.6kΩ A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 2.7-5.5V Symbol fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC (4) Parameter Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time Min. 0 500 250 250 200 250 50 50 Max. 2 Unit MHz ns ns ns ns ns ns ns 100 100 500 10 ns ns ns ms Serial Input Timing tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO High Impedance 11 FN8136.0 March 17, 2005 X5648, X5649 Serial Output Timing 2.7-5.5V Symbol fSCK tDIS tV tHO tRO(3) tFO(3) Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 100 100 Parameter Min. 0 Max. 2 250 250 Unit MHz ns ns ns ns ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN Power-Up and Power-Down Timing VTRIP VCC 0 Volts tR RESET (X5648) tPURST tPURST tF tRPD VTRIP RESET (X5649) 12 FN8136.0 March 17, 2005 X5648, X5649 RESET Output Timing Symbol VTRIP Parameter Reset trip point voltage, X5648-4.5A, X5648-4.5A Reset trip point voltage, X5648, X5649 Reset trip point voltage, X5648-2.7A, X5649-2.7A Reset trip point voltage, X5648-2.7, X5649-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC Min. 4.5 4.25 2.85 2.55 100 100 100 1 Typ. 4.63 4.38 2.93 2.63 20 200 Max. 4.75 4.5 3.0 2.7 280 500 Unit V VTH tPURST tRPD (5) mV ms ns µs µs V tF(5) tR(5) VRVALID Note: (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS tP tVPH tRP CS tVPS VP tVPH tVPO SCK VP SI tVPO 13 FN8136.0 March 17, 2005 X5648, X5649 VTRIP Reset Conditions VCC* tRP tVPS tP tVP1 CS tVPS tVPH tVPO SCK VCC VP SI tVPO *VCC > Programmed VTRIP VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C Parameter tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv Description SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programed voltage range Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (programmed at 25°C) Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP) (programmed at 25°C) VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) VTRIP program variation after programming (0 - 75°C). (programmed at 25°C.) Min. 1 1 1 10 10 Max. Unit µs µs µs µs ms 10 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 ms ms ms V V V mV mV mV VTRIP programming parameters are periodically sampled and are not 100% tested. 14 FN8136.0 March 17, 2005 X5648, X5649 TYPICAL PERFORMANCE VCC Supply Current vs. Temperature (ISB) 18 16 14 Time (ms) 12 Isb (µA) 10 8 6 4 2 0 -40 25 Temp (°C) 90 Watchdog Timer Off (VCC = 3V, 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V) tPURST vs. Temperature 205 200 195 190 185 180 175 170 165 160 -40 25 Degrees °C 90 VTRIP vs. Temperature (programmed at 25°C) 5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V 85 15 FN8136.0 March 17, 2005 X5648, X5649 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51) Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18) 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. 0.325 (8.25) 0.300 (7.62) Typ. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 16 FN8136.0 March 17, 2005 X5648, X5649 PACKAGING INFORMATION 14-Lead Plastic, SOIC, Package Code S14 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.10) 0.010 (0.25) 0.050 (1.27) 0.050"T ypical 0.010 (0.25) 0.020 (0.50) X 45° 0.050"Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.030" Typical 14 Places 0.250" FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 17 FN8136.0 March 17, 2005 X5648, X5649 Ordering Information VCC Range 4.5-5.5V VTRIP Range 4.5.4.75 Package 8 pin PDIP 14L SOIC Operating Temperature Range 0-70°C 0-70°C -40-85°C 0-70°C 0-70°C -40-85°C 0-70°C 0-70°C Part Number RESET (Active LOW) X5648P-4.5A X5648S14-4.5A X5648S14I-4.5A X5648P X5648S14 X5648S14I X5648S14-2.7A X5648S14-2.7 Part Number RESET (Active HIGH) X5649P-4.5A X5649S14-4.5A X5649S14I-4.5A X5649P X5649S14 X5649S14I X5649S14-2.7A X5649S14-2.7 4.5-5.5V 4.25.4.5 8 pin PDIP 14L SOIC 2.7-5.5V 2.7-5.5V 2.85-3.0 2.55-2.7 14L SOIC 14L SOIC Part Mark Information X5648/49 W X Blank = 14-Lead SOIC P = 8 Pin DIP Blank = 5V ±10%, 0°C to +70°C, VTRIP = 4.25-4.5 AL = 5V±10%, 0°C to +70°C, VTRIP = 4.5-4.75 I = 5V ±10%, -40°C to +85°C, VTRIP = 4.25-4.5 AM = 5V ±10%, -40°C to +85°C, VTRIP = 4.5-4.75 F = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.55-2.7 AN = 2.7V to 5.5V, 0°C to +70°C, VTRIP = 2.85-3.0 G = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.55-2.7 AP = 2.7V to 5.5V, -40°C to +85°C, VTRIP = 2.85-3.0 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN8136.0 March 17, 2005