X9119_08

® X9119 Single Supply/Low Power/1024-Tap/2-Wire Bus Data Sheet July 9, 2008 FN8162.4 Single Digitally-Controlled (XDCP™) Potentiometer The X9119 integrates a single digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP™ can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • 1024 Resistor Taps – 10-Bit Resolution • 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Wiper Resistance, 40Ω Typical @ VCC = 5V • Four Non-Volatile Data Registers • Non-Volatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 3µA Max • VCC: 2.7V to 5.5V Operation • 100kΩ End-to-End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes Per Bit Per Register • 14 Ld TSSOP • Low Power CMOS • Single Supply Version of the X9118 • Pb-Free available (RoHS compliant) Functional Diagram VCC RH 2-WIRE BUS INTERFACE ADDRESS DATA STATUS BUS INTERFACE AND CONTROL WRITE READ TRANSFER POWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3) WIPER 100kΩ 1024-TAPS POT CONTROL VSS NC NC RW RL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners X9119 Ordering Information PART NUMBER X9119TV14I X9119TV14IZ (Note) X9119TV14 X9119TV14Z (Note) X9119TV14-2.7* X9119TV14Z-2.7* (Note) X9119TV14I-2.7 X9119TV14IZ-2.7* (Note) PART MARKING X9119 TVI X9119 TVZI X9119 TV X9119 TVZ X9119 TVF X9119 TVZF X9119 TVG X9119 TVZG 2.7 to 5.5 VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (kΩ) 100 TEMP RANGE (°C) PKG. DWG.# PACKAGE M14.173 -40 to +85 14 Ld TSSOP (4.4mm) -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 0 to +70 0 to +70 0 to +70 0 to +70 14 Ld TSSOP (4.4mm) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 M14.173 -40 to +85 14 Ld TSSOP (4.4mm) -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Detailed Functional Diagram VCC POWER ON RECALL SCL SDA A2 A1 A0 WP DR0 INTERFACE AND CONTROL CIRCUITRY DATA DR2 CONTROL RW DR3 DR1 RH 100KΩ 1024-TAPS RL WIPER COUNTER REGISTER (WCR) VSS 2 FN8162.4 July 9, 2008 X9119 Applications Circuit Level • Vary the gain of a voltage amplifier • Provide programmable DC reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the DC biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits Pin Assignments PIN NUMBER 1, 3, 10 2 4 5 6 7 8 9 11 12 13 14 PIN NAME NC A0 A2 SCL SDA VSS WP A1 RW RH RL VCC No Connect Device Address for 2-wire bus Device Address for 2-wire bus Serial Clock for 2-wire bus Serial Data Input/Output for 2-wire bus System Ground Hardware Write Protect Device Address for 2-wire bus Wiper terminal of the Potentiometer High terminal of the Potentiometer Low terminal of the Potentiometer System Supply Voltage FUNCTION System Level • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9119. DEVICE ADDRESS (A2–A0) Pinout X9119 (14 LD TSSOP) TOP VIEW NC A0 NC A2 SCL SDA VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RL RH RW NC A1 WP The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. 3 FN8162.4 July 9, 2008 X9119 RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Serial Interface Description SERIAL INTERFACE The X9119 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9119 will be considered a slave device in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 3). START CONDITION All commands to the X9119 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9119 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (Figure 3). Principals of Operation The X9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides detail description of the following: • Resistor Array Description • Serial Interface Description • Instruction and Register Description Resistor Array Description The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) REGISTER 1 (DR1) SERIAL BUS INPUT C O U N T E R D E C O D E R RH 10 10 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) REGISTER 2 (DR2) REGISTER 3 (DR3) IF WCR = 000[HEX] THEN RW = RL IF WCR = 3FF[HEX] THEN RW = RH RL R W FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION 4 FN8162.4 July 9, 2008 X9119 STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 3). ACKNOWLEDGE Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9119 will respond with a final acknowledge (see Figure 2). SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ST AR T ACKNO WLEDGE FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER ACKNOWLEDGE POLLING The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9119 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9119 is still busy with the write operation, no ACK will be returned. If the X9119 has completed the write operation, an ACK will be returned and the master can then proceed with the next operation. FLOW 1. ACK Polling Sequence NONVOLATILE WRITE COMMAND COMPLETED ENTERACK POLLING ISSUE START ISSUE SLAVE ADDRESS ISSUE STOP ACK RETURNED? YES NO FURTHER OPERATION? NO YES ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED 5 FN8162.4 July 9, 2008 X9119 Instruction and Register Description Device Addressing: Identification Byte (ID and A) Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device id for the X9119; this is fixed as 0101[B] (refer to Table 1). The A2–A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2–A0 input pins. The slave address is externally specified by the user. The X9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9119 to successfully continue the command sequence. Only the device which TABLE 1. IDENTIFICATION BYTE FORMAT DEVICE TYPE IDENTIFIES INTERNAL SLAVE ADDRESS READ OR WRITE BIT slave address matches the incoming device address sent by the master executes the instruction. The A2–A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is the LSB and is be used to program the device for read or write operations. INSTRUCTION BYTE AND REGISTER SELECTION The next byte sent to the X9119 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (IOP[2:0]). The RB and RA bits point to one of the four registers. The format is shown below in Table 2. Table 3 provides a complete summary of the instruction set opcodes. ID3 0 (MSB) ID2 1 ID1 0 ID0 1 A2 A1 A0 R/W (LSB) TABLE 2. INSTRUCTION BYTE FORMAT INSTRUCTION OPCODE REGISTER SELECTION I2 (MSB) I1 I0 0 RB RA 0 0 (LSB) REGISTER SELECTED DR0 DR1 DR2 DR3 TABLE 3. INSTRUCTION SET RB 0 0 1 1 RA 0 1 0 1 INSTRUCTION SET INSTRUCTION Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register NOTE: 1/0 = data is one or zero. R/W 1 0 1 0 1 I2 1 1 1 1 1 I1 0 0 0 1 1 I0 0 1 1 0 0 0 0 0 0 0 0 RB 0 0 1/0 1/0 1/0 RA 0 0 1/0 1/0 1/0 0 0 0 0 0 0 0 0 0 0 0 0 OPERATION Read the contents of the Wiper Counter Register Write new value to the Wiper Counter Register Read the contents of the Data Register pointed to RB-RA. Write new value to the Data Register pointed to RB-RA. Transfer the contents of the Data Register pointed to by RB-RA.to the Wiper Counter Register Transfer the contents of the Wiper Counter Register to the Data Register pointed to by RB-RA. 0 1 1 1 0 1/0 1/0 0 0 6 FN8162.4 July 9, 2008 X9119 Instruction and Register Description Device Addressing WIPER COUNTER REGISTER (WCR) The X9119 contains a Wiper Counter Registers (refer to Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. it may be written directly by the host via the write wiper counter register instruction (serial load) 2. it may be written indirectly by transferring the contents of one of four associated data registers via the XFR data register 3. it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9119 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR0 TO DR3) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9–Bit 0 are used to store one of the 1024 wiper position (0 ~1023). TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V) WCR9 V (MSB) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV) Bit 9 NV MSB Bit 8 NV Bit 7 NV Bit 6 NV Bit 5 NV Bit 4 NV Bit 3 NV Bit 2 NV Bit 1 NV Bit 0 NV LSB WCR8 V WCR7 V WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB) Four of the six instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – read the current wiper position of the selected potentiometer, • Write Wiper Counter Register – change current wiper position of the selected potentiometer, • Read Data Register – read the contents of the selected Data Register; • Write Data Register – write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write-to-nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers. Two instructions (Figure 4) require a two-byte sequence to complete. These instructions transfer data between the host and the X9119; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: • XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register. • XFR Wiper Counter Register to Data Register – This transfers the contents of the Wiper Counter Register to the specified Data Register. See “Instruction Format” on page 8 for more details. POWER-UP AND DOWN REQUIREMENTS There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the VCC is always more positive than or equal to the voltages at RH, RL, and RW, i.e. VCC ≥ RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1ms after VCC reaches its final value. 7 FN8162.4 July 9, 2008 X9119 SCL SDA 0 1 0 1 A C K I2 I0 I1 0 0 RB RA 0 REGISTER ADDRESS 0 A C K S T O P S ID3 ID2 ID1 ID0 A2 A1 A0 R/W T A INTERNAL DEVICE ID R ADDRESS T 0 INSTRUCTION OPCODE FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE SCL SDA 0 1 0 1 0 0X X 0 0 A C K X X XX XX W C R 9 WAWWW CCCCC RKRRR 8 765 W C R 4 W C R 3 W C R 2 W C R 1 WA CC RK 0 S T O P S ID3 ID2 ID1 ID0 A2 A1 A0 R/W A I2 I1 I0 0 RB RA 0 T C K A DEVICE ID INTERNAL INSTRUCTION REGISTER R ADDRESS OPCODE ADDRESS T WIPER OR DATA POSITION FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) Instruction Format READ WIPER COUNTER REGISTER (WCR) DEVICE TYPE IDENTIFIER 1 0 DEVICE ADDRESSES S A C K R/W=1 INSTRUCTION REGISTER OPCODE ADDRESSES 1 0 0 0 0 0 0 0 WIPER POSITION (SENT BY SLAVE ON SDA) S WW AXXXXXXCC C RR K 98 M A C K WIPER POSITION (SENT BY SLAVE ON SDA) W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 M A C K S T O P S T A0 R T 1 A2 A1 A0 WRITE WIPER COUNTER REGISTER (WCR) DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES S A C K R/W=0 INSTRUCTION REGISTER OPCODE ADDRESSES 1 0 1 0 0 0 0 0 WIPER POSITION (SENT BY MASTER ON SDA) S W AXXXXXXC C R K 9 W C R 8 WIPER POSITION (SENT BY MASTER ON SDA) SWWW ACCC CRRR K765 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 SS AT CO KP S T A R T 1 A2 A1 A0 READ DATA REGISTER (DR) DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES S A C K R/W=1 INSTRUCTION REGISTER OPCODE ADDRESSES 1 0 1 0 RB RA 0 0 WIPER POSITION (SENT BY SLAVE ON SDA) S W AXXXXXXC C R K 9 W C R 8 WIPER POSITION OR DATA (SENT BY SLAVE ON SDA) MWW ACC CRR K76 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 MS AT CO KP S T A R T 1 A2 A1 A0 8 FN8162.4 July 9, 2008 X9119 WRITE DATA REGISTER (DR) DEVICE TYPE DEVICE IDENTIFIER ADDRESSES 1 0 1 A2 A1 A0 S A C K R/W=0 S T A0 R T INSTRUCTION REGISTER OPCODE ADDRESSES 1 1 0 0 RB RA 0 S WW 0AXXXXXXCC C RR K 98 SWWWW ACCCC CRRRR K7654 W C R 3 W C R 2 W C R 1 W C R 0 S A C K S T O P TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A2 1 A0 R/W=0 S A C K INSTRUCTION OPCODE 1 1 1 0 REGISTER ADDRESSES RB RA 0 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR) DEVICE TYPE DEVICE S IDENTIFIER ADDRESSES T A 0 1 0 1 A2 A1 A0 R T NOTES: 1. A2 ~ A0”: stand for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register INSTRUCTION OPCODE S A C K 1 1 0 0 REGISTER ADDRESSES RB RA 0 0 S A C K S T O P R/W=1 9 FN8162.4 July 9, 2008 HIGH-VOLTAGE WRITE CYCLE WIPER POSITION OR DATA (SENT BY MASTER ON SDA) WIPER POSITION OR DATA (SENT BY MASTER ON SDA) X9119 Absolute Maximum Ratings Voltage on SCL, SDA, or any address input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V ΔV = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Thermal Information Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° to +85°C Supply Voltage (VCC) Limits (Note 4) X9119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% X9119-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications PARAMETER End-to-End Resistance (Over recommended operation conditions unless otherwise stated.) SYMBOL RTOTAL TEST CONDITIONS MIN (Note 8) TYP 100 ±20 +25°C, each pot IW RW Wiper Current = ± 50µA, VCC = 5V Wiper Current = ± 50µA, VCC = 3V 40 150 VSS -120 0.1 Rw(n)(actual) – Rw(n)(expected), where n = 8 to 1006 Rw(n)(actual) – Rw(n)(expected) (Note 4) ±1.5 ±1 ±2.0 ±0.5 ±0.5 ±300 20 CH/CL/CW See Macro model 10/10/25 ±1.0 50 ±3 110 300 5 MAX (Note 8) UNITS kΩ % mW mA Ω Ω V dBV % MI (Note 3) MI (Note 3) MI (Note 3) MI (Note 3) ppm/°C ppm/°C pF End-to-End Resistance Tolerance Power Rating Wiper Current Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (Note 1) VTERM VSS = 0V Ref: 1V Relative Linearity (Note 2) Rw(m + 1) – [Rw(m) + MI], where m = 8 to 1006 Rw(m + 1) – [Rw(m) + MI] (Note 4) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient Potentiometer Capacitancies NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/1023 or (RH – RL)/1023, single pot 4. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022. 5. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV. 10 FN8162.4 July 9, 2008 X9119 Operating Specifications (Over the recommended operating conditions unless otherwise specified.) PARAMETER VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) SYMBOL ICC1 TEST CONDITIONS fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Read and Volatile Write States only) fSCL = 400kHz; VCC = +5.5V; SDA = Open; (for 2-wire, Active, Non-volatile Write State only) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-wire, Standby State only) VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 -1 IOL = 3mA MIN. TYP. MAX. 3 UNITS mA ICC2 5 mA ISB 3 µA Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage ILI ILO VIH VIL VOL VOH 10 10 VCC + 1 VCC x 0.3 0.4 µA µA V V V Endurance and Data Retention PARAMETER Minimum Endurance Data Retention MIN 100,000 100 UNITS Data changes per bit per register years Capacitance TEST Input/Output capacitance (SI) Input capacitance (SCL, WP, A1 and A0) SYMBOL CIN/OUT (Note 6) CIN (Note 6) MAX 8 6 UNITS pF pF TEST CONDITIONS VOUT = 0V VIN = 0V Power-Up Timing PARAMETER VCC Power-up Rate Power-up to Initiation of read operation Power-up to Initiation of write operation NOTES: 6. Limits should be considered typical and are not production tested. 7. tPUR and tPUW are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These parameters are not 100% tested. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL tr VCC (Note 6) tPUR (Note 7) tPUW (Note 7) MIN 0.2 MAX 50 1 50 UNITS V/ms ms ms AC Test Conditions Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 11 FN8162.4 July 9, 2008 X9119 Equivalent A.C. Load Circuit 5V 1533Ω SDA OUTPUT 100pF 3V 867Ω RH SDA OUTPUT 100pF RW CL 10pF CW 25pF CL 10pF SPICE MACROMODEL RTOTAL RL AC Timing High-Voltage Write Cycle Timing PARAMETER Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA Inputs Bus Free Time (Prior to Any Transmission) A0, A1, A2 Setup Time A0, A1, A2 Hold Time SYMBOL fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA 250 0 50 1300 0 0 2500 600 1300 600 600 600 100 0 300 300 MIN MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns High-Voltage Write Cycle Timing PARAMETER High-Voltage Write CycleTime (Store Instructions) SYMBOL tWR TYP 5 MAX 10 UNITS ms XDCP Timing PARAMETER Wiper Response Time After theThird (Last) Power Supply is Stable WiperResponse Time After Instruction Issued (All Load Instructions) SYMBOL tWRPO tWRL MIN 5 5 MAX 10 10 UNITS µs µs 12 FN8162.4 July 9, 2008 X9119 Symbol Table WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance Timing Diagrams Start and Stop Timing ( START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF (STOP) Input Timing tCYC SCL tLOW SDA tSU:DAT tHD:DAT tBUF tHIGH Output Timing SCL SDA tAA tDH 13 FN8162.4 July 9, 2008 X9119 XDCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL RW Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (ANY INSTRUCTION) ... SDA ... TSU:WPA THD:WPA WP A0, A1, A2 14 FN8162.4 July 9, 2008 X9119 Applications information Basic Configurations of Electronic Potentiometers VR +VR RW I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Application Circuits NONINVERTING AMPLIFIER VS + – VO VIN 317 R1 R2 R1 VO (REG) VOLTAGE REGULATOR IADJ R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS R1 VS 100kΩ R2 VS – + VO – + TL072 10kΩ 10kΩ +12V -12V 10kΩ VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 15 FN8162.4 July 9, 2008 X9119 Application Circuits (Continued) ATTENUATOR C VS R1 VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 R2 FILTER + – VO – + VO R R2 V O = G VS -1/2 £ G £ +1/2 GO = 1 + R2/R1 fc = 1/(2pRC) INVERTING AMPLIFIER R1 R2 EQUIVALENT L-R CIRCUIT } VS } – + VO C1 VS R2 + – ZIN R1 R3 V O = G VS G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR C – + R2 R1 – } RA } RB FREQUENCY µ R1, R2, C AMPLITUDE µ RA, RB + 16 FN8162.4 July 9, 2008 X9119 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c D E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN8162.4 July 9, 2008