X9241A

® X9241A Low Power/2-Wire Serial Bus Data Sheet September 15, 2005 FN8164.1 Quad Digitally Controlled Potentiometer (XDCP™) The X9241A integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers in one package • 2-wire serial interface • Register oriented format - Direct read/write/transfer of wiper positions - Store as many as four positions per potentiometer • Terminal Voltages: +5V, -3.0V • Cascade resistor arrays • Low power CMOS • High Reliability - Endurance–100,000 data changes per bit per register - Register data retention–100 years • 16-bytes of nonvolatile memory • 3 resistor array values - 2kΩ to 50kΩ mask programmable - Cascadable for values of 500Ω to 200kΩ • Resolution: 64 taps each pot • 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC packages • Pb-free plus anneal available (RoHS compliant) Block Diagram VCC VSS R0 R1 Wiper Counter Register (WCR) VH0/RH0 R0 R1 Wiper Counter Register (WCR) Register Array Pot 2 VH2/ RH2 VL2/RL2 VW2/RW2 R2 R3 SCL SDA A0 A1 A2 A3 VL0/RL0 VW0/RW0 R2 R3 Interface and Control Circuitry Data 8 R0 R1 Wiper Counter Register (WCR) Register Array Pot 1 VH1/RH1 R0 R1 Wiper Counter Register (WCR) Register Array Pot 3 VH3/RH3 R2 R3 VL1/RL1 VW1/RW1 R2 R3 VL3/RL3 VW3/RW3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9241A Ordering Information PART NUMBER X9241AMP X9241AMPZ (Note) X9241AMPI X9241AMPIZ (Note) X9241AMS* X9241AMSZ* (Note) X9241AMSI* X9241AMSIZ* (Note) X9241AMV* X9241AMVZ* (Note) X9241AMVI* X9241AMVIZ* (Note) X9241AWP X9241AWPZ (Note) X9241AWPI X9241AWPIZ (Note) X9241AWS* X9241AWSZ* (Note) X9241AWSI* X9241AWSIZ* (Note) X9241AWV* X9241AWVZ* (Note) X9241AWVI* X9241AWVIZ* (Note) X9241AYP X9241AYPZ (Note) X9241AYPI X9241AYPIZ (Note) X9241AYS* X9241AYSZ* (Note) X9241AYSI* X9241AYSIZ* (Note) X9241AYV* X9241AYVZ* (Note) X9241AYVI* X9241AYVIZ* (Note) X9241AYV X9241AYV Z X9241AYVI X9241AYVI Z X9241AWPI X9241AWPI Z X9241AWS X9241AWS Z X9241AWSI X9241AWSI Z X9241AWV X9241AWVZ X9241AWVI X9241AWVI Z X9241AYP X9241AYP Z X9241AYPI X9241AYPI Z X9241AYS X9241AYS Z X9241AYSI 2 PART MARKING X9241AMP X9241AMPZ X9241AMPI X9241AMPIZ X9241AMS X9241AMS Z X9241AMSI X9241AMSI Z X9241AMV X9241AMV Z X9241AMVI X9241AMVI Z X9241AWP 10 VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (K) 2/10/50 TEMP RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 2 FN8164.1 September 15, 2005 X9241A Ordering Information (Continued) PART NUMBER X9241AUP X9241AUPZ (Note) X9241AUPI X9241AUPIZ (Note) X9241AUS* X9241AUSZ* (Note) X9241AUSI* X9241AUSIZ* (Note) X9241AUV* X9241AUVZ* (Note) X9241AUVI* X9241AUVIZ* (Note) PART MARKING X9241AUP X9241AUP Z X9241AUPI X9241AUPI Z X9241AUS X9241AUS Z X9241AUSI X9241AUSI Z X9241AUV X9241AUV Z X9241AUVI X9241AUVI Z VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (K) 50 TEMP RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld SOIC 20 Ld SOIC (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) 20 Ld TSSOP 20 Ld TSSOP (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Descriptions Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241A. Pin Configuration DIP/SOIC/TSSOP VW0/RW0 VL0/RL0 VH0/RH0 A0 A2 VW1/RW1 VL1/RL1 VH1/RH1 SDA VSS 1 2 3 4 5 6 7 8 9 10 X9241A 20 19 18 17 16 15 14 13 12 11 VCC VW3/RW3 VL3/RL3 VH3/RH3 A1 A3 SCL VW2/RW2 VL2/RL2 VH2/RH2 Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241A. Pin Names SYMBOL SCL SDA A0–A3 VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 VW0/RW0–VW3/RW3 Serial Clock Serial Data Address Potentiometer Pins (terminal equivalent) Potentiometer Pins (wiper equivalent) DESCRIPTION Potentiometer Pins VH/RH(VH0/RH0—VH3/RH3), VL/RL (VL0/RL0—VL3/RL3) The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0—VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. 3 FN8164.1 September 15, 2005 X9241A Principles of Operation The X9241A is a highly integrated microcircuit incorporating four resistor arrays, their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. At both ends of each array and between each resistor segment is a FET switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six least significant bits of the WCR are decoded to select, and enable, one of sixtyfour switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Serial Interface The X9241A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9241A will be considered a slave device in all applications. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9241A this is fixed as 0101[B]. Device Type Identifier 0 1 0 1 A3 A2 A1 A0 Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9241A are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9241A continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Device Address FIGURE 1. SLAVE ADDRESS Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. See Figure 7. The X9241A will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9241A will respond with a final acknowledge. The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9241A compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9241A to respond with an acknowledge. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9241A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9241A is still busy with the write operation no ACK will be returned. If the X9241A has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Array Description The X9241A is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). 4 FN8164.1 September 15, 2005 X9241A Flow 1. ACK Polling Sequence The four high order bits define the instruction. The next two bits (P1 and P0) select which one of the four potentiometers is to be affected by the instruction. The last two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM. The response of the wiper to this action will be delayed tSTPWV. A transfer from WCR current wiper position, to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all four of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9241A; either between the host and one of the Data Registers or directly between the host and the WCR. These instructions are: Read WCR, read the current wiper position of the selected pot; Write WCR, change current wiper position of the selected pot; Read Data Register, read the contents of the selected nonvolatile register; Write Data Register, write a new value to the selected Data Register. The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9241A has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Nonvolatile Write Command Completed Enter ACK Polling Issue START Issue Slave Address Issue STOP ACK Returned? Yes No FurTher OperaTion? Yes Issue Instruction No Issue STOP Proceed Proceed Instruction Structure The next byte sent to the X9241A contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of four pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Potentiometer Select I3 I2 I1 I0 P1 P0 R1 R0 Instructions Register Select FIGURE 2. INSTRUCTION BYTE FORMAT 5 FN8164.1 September 15, 2005 X9241A SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 P1 P0 R1 R0 A C K S T O P FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 P1 P0 R1 R0 A CM DW D5 D4 D3 D2 D1 D0 A C C K K S T O P FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 X X P1 P0 R1 R0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE INC/DEC CMD ISSUED SCL tCLWV SDA Voltage Out VW/RW FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS 6 FN8164.1 September 15, 2005 X9241A TABLE 1. INSTRUCTION SET INSTRUCTION FORMAT INSTRUCTION Read WCR Write WCR Read Data Register Write Data Register XFR Data Register to WCR XFR WCR to Data Register Global XFR Data Register to WCR Global XFR WCR to Data Register Increment/ Decrement Wiper I3 1 1 1 1 1 1 0 I2 0 0 0 1 1 1 0 I1 0 1 1 0 0 1 0 I0 1 0 1 0 1 0 1 P1 1/0(10) 1/0 1/0 1/0 1/0 1/0 X P0 1/0 1/0 1/0 1/0 1/0 1/0 X R1 X(11) X 1/0 1/0 1/0 1/0 1/0 R0 X X 1/0 1/0 1/0 1/0 1/0 OPERATION Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Register pointed to by P1 - P0 and R1 - R0 Write new value to the Register pointed to by P1 - P0 and R1 - R0 Transfer the contents of the Register pointed to by P1 - P0 and R1 - R0 to its associated WCR Transfer the contents of the WCR pointed to by P1 - P0 to the Register pointed to by R1 - R0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective WCR Transfer the contents of all WCRs to their respective data Registers pointed to by R1 - R0 of all four pots Enable Increment/decrement of the WCR pointed to by P1 - P0 1 0 0 0 X X 1/0 1/0 0 0 1 0 1/0 1/0 X X Notes: (10) 1/0 = data is one or zero (11) X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical) SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver START FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER Acknowledge 7 FN8164.1 September 15, 2005 X9241A Detailed Operation All four XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer is comprised of a resistor array, a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. The WCR is a volatile register; that is, its contents are lost when the X9241A is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Wiper Counter Register The X9241A contains four volatile Wiper Counter Registers (WCR), one for each XDCP potentiometer. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write WCR instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the increment/decrement instruction; finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. Serial Data Path From Interface Circuitry Register 0 8 Register 1 6 Serial Bus Input VH/RH Parallel Bus Input Wiper Counter Register Register 2 Register 3 C o u n t e r 2 If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH UP/DN Modified SCL INC/DEC Logic UP/DN CLK D e c o d e VL/RL DW Cascade Control Logic CM FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM VW/RW 8 FN8164.1 September 15, 2005 X9241A Cascade Mode The X9241A provides a mechanism for cascading the arrays. That is, the sixty-three resistor elements of one array may be cascaded (linked) with the resistor elements of an adjacent array. The VL/RL of the higher order array must be connected to the VH/RH of the lower order array (See Figure 9). set to “1” the wiper is disabled. If the wiper is disabled, the wiper terminal will be electrically isolated and float. When operating in cascade mode VH/RH, VL/RL and the wiper terminals of the cascaded arrays must be electrically connected externally. All but one of the wipers must be disabled. The user can alter the wiper position by writing directly to the WCR or indirectly by transferring the contents of the Data Registers to the WCR or by using the Increment/Decrement command. When using the Increment/Decrement command the wiper position will automatically transition between arrays. The current position of the wiper can be determined by reading the WCR registers; if the DW bit is “0”, the wiper in that array is active. If the current wiper position is to be maintained on power-down a global XFR WCR to Data Register command must be issued to store the position in NV memory before power-down. It is possible to connect three or all four potentiometers in cascade mode. It is also possible to connect POT 3 to POT 0 as a cascade. The requirements for external connections of VL/RL, VH/RH and the wipers are the same in these cases. Cascade Control Bits The data byte, for the three-byte commands, contains 6 bits (LSBs) for defining the wiper position plus two high order bits, CM (Cascade Mode) and DW (Disable Wiper, normal operation). The state of the CM bit (bit 7 of WCR) enables or disables cascade mode. When the CM bit of the WCR is set to “0” the potentiometer is in the normal operation mode. When the CM bit of the WCR is set to “1” the potentiometer is cascaded with its adjacent higher order potentiometer. For example; if bit 7 of WCR2 is set to “1”, pot 2 will be cascaded to pot 3. The state of DW enables or disables the wiper. When the DW bit of the WCR is set to “0” the wiper is enabled; when Pot 0 WCR0 VL0/RL0 VH0/RH0 VW0/RW0 Pot 1 WCR1 VL1/RL1 VH1/RH1 VW1/RW1 Pot 2 WCR2 VL2/RL2 VH2/RH2 VW2/RW2 Pot 3 WCR3 External = Connection VL3/RL3 VH3/RH3 VW3/RW3 FIGURE 9. CASCADING ARRAYS 9 FN8164.1 September 15, 2005 X9241A Absolute Maximum Ratings Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C Voltage on SCK, SCL or any address input with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on any VH/RH, VW/RW or VL/RL referenced to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V/-4V ∆V = |VH/RH - VL/RL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Recommended Operating Conditions Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VCC) Limits X9241A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10% CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Specifications SYMBOL RTOTAL (Over recommended operating conditions unless otherwise stated.) LIMITS PARAMETER TEST CONDITION MIN -20 25°C, each pot See Note 7, 8 Wiper Current = ± 1mA (Note 7) -3.0 Ref: 1kHz See Note 5 See Note 5 Rw(n)(actual) - Rw(n)(expected) Rw(n + 1) - [Rw(n) + MI] See Note 5 See Note 5 See Circuit #3 and Note 5 VIN = VTERM. Device is in stand-by mode. 15/15/25 0.1 1 ±300 ±20 ≤120 1.6 0.4 ±1 ±0.2 40 130 +5 TYP MAX +20 50 UNIT % mW mA Ω V dBV % MI(3) MI(3) ppm/°C ppm/C pF µA End to end resistance Power rating IW RW VTERM Wiper current Wiper resistance Voltage on any VH/RH, VW/RW or VL/RL Pin Noise Resolution(4) Absolute linearity(1) Relative linearity(2) Temperature Coefficient of RTOTAL Ratiometric temperature coefficient CH/CL/CW lAL Potentiometer capacitances RH, RI, RW leakage current DC Electrical Specifications SYMBOL lCC ISB ILI ILO VIH VIL VOL PARAMETER Supply current (active) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage (Over recommended operating conditions unless otherwise stated.) LIMITS TEST CONDITION fSCL = 100kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC 2 -1 IOL = 3mA 200 MIN TYP MAX 3 500 10 10 VCC + 1 0.8 0.4 UNIT mA µA µA µA V V V Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (RH–RL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. 10 FN8164.1 September 15, 2005 X9241A Endurance and Data Retention PARAMETER Minimum endurance Data retention MIN 100,000 100 UNIT Data changes per bit per register Years Capacitance SYMBOL CI/O(5) CIN(5) PARAMETER Input/output capacitance (SDA) Input capacitance (A0, A1, A2, A3 and SCL) TEST CONDITION VI/O = 0V VIN = 0V MAX 19 12 UNIT pF pF Power-up Timing SYMBOL tPUR(6) tPUW(6) tRVCC PARAMETER Power-up to initiation of read operation Power-up to initiation of write operation VCC Power up ramp rate 0.2 MIN TYP MAX 1 5 50 UNIT ms ms V/msec Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification should be met, and any glitches or slope changes in the Vcc line should be held to