X9250

® X9250 Low Noise/Low Power/SPI Bus/256 Taps Data Sheet August 29, 2006 FN8165.3 Quad Digitally Controlled Potentiometers (XDCP™) FEATURES • • • • • • • • Four potentiometers in one package 256 resistor taps/pot - 0.4% resolution SPI serial interface Wiper resistance, 40Ω typical @ VCC = 5V Four nonvolatile data registers for each pot Nonvolatile storage of wiper position Standby current < 5µA max (total package) Power supplies —VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V 100kΩ, 50kΩ total pot resistance High reliability —Endurance – 100,000 data changes per bit per register —Register data retention - 100 years 24 Ld SOIC, 24 Ld TSSOP Dual supply version of X9251 Pb-free plus anneal available (RoHS compliant) DESCRIPTION The X9250 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • • • • • BLOCK DIAGRAM VCC VSS V+ VR0 R1 Wiper Counter Register (WCR) Pot 0 VH0/RH0 R0 R1 Wiper Counter Register (WCR) VH2/RH2 HOLD CS SCK SO SI A0 A1 WP R2 R3 VL0/RL0 VW0/RW0 R2 R3 Resistor Array Pot 2 VL2/RL2 VW2/RW2 Interface and Control Circuitry Data 8 VW1/RW1 R0 R1 Wiper Counter Register (WCR) VH1/RH1 R0 R1 Wiper Counter Register (WCR) VW3/RW3 VH3/RH3 R2 R3 Resistor Array Pot1 VL1/RL1 R2 R3 Resistor Array Pot 3 VL3/RH3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9250 Ordering Information PART NUMBER X9250TS24I X9250TS24IZ (Note) X9250TV24I X9250TV24IZ (Note) X9250US24 X9250US24Z (Note) X9250US24I X9250US24IZ (Note) X9250UV24I X9250UV24IZ (Note) X9250TS24-2.7 PART MARKING X9250TS I X9250TS ZI X9250TV I X9250TV ZI X9250US X9250US Z X9250US I X9250US ZI X9250UV I X9250UV ZI X9250TS F -2.7 to 5.5 100 50 VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (kΩ) 100 TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -40 to +85 50 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 PACKAGE 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) PKG. DWG. # M24.3 M24.3 MDP0044 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 MDP0044 MDP0044 X9250TS24Z-2.7 (Note) X9250TS ZF X9250TS24I-2.7* X9250TS24IZ-2.7* (Note) X9250TV24I-2.7 X9250TS G X9250TS ZG X9250TV G X9250TV24IZ-2.7 (Note) X9250TV ZG X9250US24-2.7* X9250US F X9250US24Z-2.7* (Note) X9250US ZF X9250US24I-2.7 X9250US G X9250US24IZ-2.7 (Note) X9250US ZG X9250UV24-2.7 X9250UV F X9250UV24Z-2.7 (Note) X9250UV ZF X9250UV24I-2.7 X9250UV G X9250UV24IZ-2.7 (Note) X9250UV ZG *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN8165.3 August 29, 2006 X9250 PIN DESCRIPTIONS Serial Output (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9250. Chip Select (CS) When CS is HIGH, the X9250 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9250, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A0 - A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9250. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 VL3/RL3) The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. S0 A0 VW3/RW3 VH3/RH3 VL3/RL3 V+ VCC VL0/RL0 VH0/RH0 VW0/RW0 CS WP VW/RW (VW0/RW0 - VW3/RW3) The wiper pins are equivalent to the wiper terminal of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Analog Supplies (V+, V-) The analog supplies V+, V- are the supply voltages for the XDCP analog section. PIN CONFIGURATION SOIC/TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 X9250 24 23 22 21 20 19 18 17 16 15 14 13 HOLD SCK VL2/RL2 VH2/RL2 VW2/RW2 V– VSS VW1/RW1 VH1/RH1 VL1/RL1 A1 SI PIN NAMES Symbol SCK SI, SO A0-A1 VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 VW0/RW0–VW3/RW3 WP V+,VVCC VSS NC Description Serial Clock Serial Data Device Address Potentiometer Pins (terminal equivalent) Potentiometer Pins (wiper equivalent) Hardware Write Protection Analog Supplies System Supply Voltage System Ground No Connection 3 FN8165.3 August 29, 2006 X9250 DEVICE DESCRIPTION Serial Interface The X9250 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9250 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches. Wiper Counter Register (WCR) The X9250 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the increment/decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9250 is powereddown. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. Data Registers Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Data Register Detail (MSB) D7 NV D6 NV D5 NV D4 NV D3 NV D2 NV D1 NV (LSB) D0 NV 4 FN8165.3 August 29, 2006 X9250 Figure 1. Detailed Potentiometer Block Diagram (One of Four Arrays) Serial Data Path From Interface Circuitry Register 0 8 Register 1 8 Parallel Bus Input Wiper Counter Register (WCR) Serial Bus Input C o u n t e r D e c o d e VH/RH Register 2 Register 3 If WCR = 00[H] then VW/RW = VL/RL If WCR = FF[H] then VW/RW = VH/RH UP/DN Modified SCK Inc/Dec Logic UP/DN CLK VL/RL VW/RW Write in Process The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a write in process bit (WIP). The WIP bit is read with a read status command. INSTRUCTIONS Identification (ID) Byte The first byte sent to the X9250 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9250 this is fixed as 0101[B] (refer to Figure 2). The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A0 - A1 input pins. The X9250 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9250 to successfully continue the command sequence. The A0 - A1 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the slave byte must be set to 0. Figure 2. Identification Byte Format Device Type Identifier 0 1 0 1 0 0 A1 A0 Device Address Instruction Byte The next byte sent to the X9250 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 3. Figure 3. Instruction Byte Format Register Select I3 I2 I1 I0 R1 R0 P1 P0 Instructions Pot Select 5 FN8165.3 August 29, 2006 X9250 The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register—This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Regiter— This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Regiter— This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9250; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – Read Wiper Counter Register—read the current wiper position of the selected pot, – Write Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and Figure 8. 6 FN8165.3 August 29, 2006 X9250 Figure 4. Two-Byte Instruction Sequence CS SCK SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Figure 5. Three-Byte Instruction Sequence (Write) CS SCL SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 6. Three-Byte Instruction Sequence (Read) CS SCL SI 0 S0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Don’t Care Figure 7. Increment/Decrement Instruction Sequence CS SCK SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 0 0 P1 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n 7 FN8165.3 August 29, 2006 X9250 Figure 8. Increment/Decrement Timing Limits tWRID SCK SI VW/RW INC/DEC CMD Issued Voltage Out Table 1. Instruction Set Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Register to Wiper Counter Register Global XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP bit) I3 1 1 1 1 1 1 I2 0 0 0 1 1 1 Instruction Set I1 I0 R1 R0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 R1 R1 R1 R1 R1 R1 0 0 0 R0 R0 R0 R0 R0 R0 0 0 P1 P1 P1 P1 P1 P1 P1 0 0 P1 0 P0 P0 P0 P0 P0 P0 P0 0 0 P0 1 Operation Read the contents of the Wiper Counter Register pointed to by P1- P0 Write new value to the Wiper Counter Register pointed to by P1- P0 Read the contents of the Data Register pointed to by P1- P0 and R1- R0 Write new value to the Data Register pointed to by P1- P0 and R1- R0 Transfer the contents of the Data Register pointed to by R1- R0 to the Wiper Counter Register pointed to by P1- P0 Transfer the contents of the Wiper Counter Register pointed to by P1- P0 to the Register pointed to by R1- R0 Transfer the contents of the Data Registers pointed to by R1- R0 of all four pots to their respective Wiper Counter Register Transfer the contents of all Wiper Counter Registers to their respective data Registers pointed to by R1- R0 of all four pots Enable Increment/decrement of the Wiper Counter Register pointed to by P1- P0 Read the status of the internal write cycle, by checking the WIP bit. 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 8 FN8165.3 August 29, 2006 X9250 Instruction Format Notes: (1) (2) (2) (3) “A1 ~ A0”: stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register(WCR) device type identifier device addresses instruction opcode 1 0 0 1 WCR addresses 0 0 P 1 wiper position (sent by X9250 on SO) CS Falling Edge 0 1 0 1 0 0 A A 10 CS W W W W W W W W Rising P P P P P P P P P Edge 0 76543210 Write Wiper Counter Register (WCR) device type identifier device addresses instruction opcode 1 0 1 0 0 WCR addresses 0 P 1 Data Byte (sent by Host on SI) CS Falling Edge 0 1 0 1 0 0 A A 10 CS W W W W W W W W Rising P P P P P P P P P Edge 0 76543210 Read Data Register (DR) device type identifier device addresses A 1 A 0 instruction opcode 1011 DR and WCR addresses R 1 R 0 P 1 Data Byte (sent by X9250 on SO) CS Falling Edge 0 1 0 1 0 0 CS W W W W W W W W Rising P P P P P P P P P Edge 0 76543210 Write Data Register (DR) device type identifier device addresses A 1 A 0 instruction opcode 1100 DR and WCR addresses R 1 R 0 P 1 Data Byte (sent by host on SI) CS Falling Edge 0 1 0 1 0 0 CS W W W W W W W W Rising P P P P P P P P P Edge 0 76543210 HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) device type device instruction DR and WCR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 1 0 1 R1 R0 P1 P0 Edge 10 9 FN8165.3 August 29, 2006 X9250 Transfer Wiper Counter Register (WCR) to Data Register (DR) device type device CS identifier addresses Falling Edge 0 1 0 1 0 0 A A 10 instruction opcode 1110 DR and WCR addresses R 1 R 0 P 1 CS Rising P Edge 0 HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) device type device instruction WCR increment/decrement CS CS identifier addresses opcode addresses (sent by master on SI) Falling Rising Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/D I/D . . . . I/D I/D Edge 10 10 Global Transfer Data Register (DR) to Wiper Counter Register (WCR) device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge 10 10 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge 10 10 HIGH-VOLTAGE WRITE CYCLE Read Status device type identifier device addresses instruction opcode Data Byte (sent by X9250 on SO) CS CS Falling W Rising Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge 10 P 10 FN8165.3 August 29, 2006 X9250 ABSOLUTE MAXIMUM RATINGS Temperature under bias ........................ -65 to +135°C Storage temperature ............................. -65 to +150°C Voltage on SCK, SCL or any address input with respect to VSS ................................. -1V to +7V Voltage on V+ (referenced to VSS)........................ 10V Voltage on V- (referenced to VSS)........................-10V (V+) - (V-) .............................................................. 12V Any VH/RH ..............................................................V+ Any VL/RL.................................................................VLead temperature (soldering, 10s) .................. +300°C IW (10s) ............................................................±15mA RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Device X9250 X9250-2.7 Supply Voltage (VCC) Limits(4) 5V ±10% 2.7V to 5.5V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter End to end resistance tolerance Power rating IW RW Vv+ VvVTERM Wiper current Wiper resistance Voltage on V+ pin Voltage on V- pin X9250 X9250-2.7 X9250 X9250-2.7 Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitances 10/10/25 ±300 ±20 +4.5 +2.7 -5.5 -5.5 V-120 0.6 ±1 ±0.6 150 Min. Typ. Max. ±20 50 ±7.5 250 +5.5 +5.5 -4.5 -2.7 V+ Unit % mW mA Ω V V V dBV % MI(3) MI(3) ppm/°C ppm/°C pF Test Conditions +25°C, each pot Wiper current = ± 1mA Ref: 1kHz Vw(n)(actual) - Vw(n)(expected) Vw(n + 1 - [Vw(n) + MI] See Circuit #3 Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/255 or (VH/RH - VL/RL)/255, single pot (4) Individual array resolutions. 11 FN8165.3 August 29, 2006 X9250 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB ILI ILO VIH VIL VOL Parameter VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Min. Typ. Max. 400 1 5 10 10 Unit µA mA µA µA µA V V V Test Conditions fSCK = 2MHz, SO = Open, Other Inputs = VSS fSCK = 2MHz, SO = Open, Other Inputs = VSS SCK = SI = VSS, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 -0.5 VCC + 0.1 VCC x 0.3 0.4 IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Unit Data changes per bit per register Years CAPACITANCE Symbol COUT (5) Test Output capacitance (SO) Input capacitance (A0, A1, SI, and SCK, CS) Max. 8 6 Unit pF pF Test Conditions VOUT = 0V VIN = 0V CIN(5) POWER-UP TIMING Symbol tPUR(6) tPUW(6) tR VCC(7) Parameter Power-up to initiation of read operation Power-up to initiation of write operation VCC power up ramp rate Min. Max. 1 5 Unit ms ms V/msec 0.2 50 POWER UP AND DOWN REQUIREMENT The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate spec is always in effect. Notes: (5) This parameter is periodically sampled and not 100% tested (6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (7) Sample tested only. A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 12 FN8165.3 August 29, 2006 X9250 Circuit #3 SPICE Macro Model RTOTAL RH CH 10pF CW 25pF 100pF RW 100pF CL 10pF SDA Output RL EQUIVALENT A.C. LOAD CIRCUIT 5V 1533Ω 2.7V AC TIMING Symbol fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle time SSI/SPI clock high time SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable Time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 and A1 setup time WP, A0 and A1 hold time 2 0 0 400 100 100 100 100 TBD 0 50 50 0 500 200 200 250 250 50 75 2 2 500 100 Parameter Min. Max. 2.0 Unit MHz ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns µs ns ns 13 FN8165.3 August 29, 2006 X9250 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage write cycle time (store instructions) Typ. 5 Max. 10 Unit ms XDCP TIMING Symbol tWRPO tWRL tWRID Parameter Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Wiper response time from an active SCL/SCK edge (increment/decrement instruction) Min. Max. 10 10 40 Unit µs µs µs SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance TIMING DIAGRAMS Input Timing tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC tLAG ... tWH tFI LSB tRI ... SO High Impedance 14 FN8165.3 August 29, 2006 X9250 Output Timing CS SCK tV SO MSB tHO ... tDIS ... LSB SI ADDR Hold Timing CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ... XDCP Timing (for all Load Instructions) CS SCK ... MSB tWRL LSB SI ... VWx SO High Impedance 15 FN8165.3 August 29, 2006 X9250 XDCP Timing (for Increment/Decrement Instruction) CS SCK ... tWRID VWx ... ... SI ADDR Inc/Dec Inc/Dec SO High Impedance Write Protect and Device Address Pins Timing CS WP A0 A1 tWPASU (Any Instruction) tWPAH 16 FN8165.3 August 29, 2006 X9250 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers VR +VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS + – VO VIN 317 R1 R2 R1 Iadj R2 VO (REG) Voltage Regulator VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 VS 100kΩ – + TL072 10kΩ 10kΩ +12V 10kΩ -12V VO R2 Comparator with Hysterisis VS – + VO VUL = {R1/(R1+R2) VO(max) VLL = {R1/(R1+R2) VO(min) } R1 } R2 17 FN8165.3 August 29, 2006 X9250 Application Circuits (continued) Attenuator C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 R2 – + VO VS R R2 + – VO Filter V O = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + C1 VO VS R2 + – V O = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 18 FN8165.3 August 29, 2006 X9250 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE A PIN #1 I.D. 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max ±0.05 ±0.05 +0.05/-0.06 +0.05/-0.06 ±0.10 Basic ±0.10 Basic ±0.15 Reference Rev. E 12/02 A1 A2 b c D E E1 e L H E E1 0.20 C B A 1 B TOP VIEW (N/2) 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 L1 NOTES: b 0.10 C N LEADS SIDE VIEW 0.10 M C A B 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0° - 8° 19 FN8165.3 August 29, 2006 X9250 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8° Rev. 1 4/06 MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 A1 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.010 0.016 24 0° 8° 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 24 0° 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8165.3 August 29, 2006