X9252

® X9252 Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface Data Sheet September 14, 2005 FN8167.1 Quad Digitally-Controlled (XDCP™) Potentiometer The X9252 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented using 255 resistive elements in a series array. Between each pair of elements are tap points connected to wiper terminals through switches. The position of each wiper on the array is controlled by the user through the Up/Down (U/D) or 2-wire bus interface. The wiper of each potentiometer has an associated volatile Wiper Counter Register (WCR) and four non-volatile Data Registers (DRs) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. At power-up, the device recalls the contents of the default data registers DR00, DR10, DR20, DR30, to the corresponding WCR. Each DCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, the implementation of ladder networks, and three resistor programmable networks. Features • Quad Solid State Potentiometer • 256 Wiper Tap Points-0.4% Resolution • 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Up/Down Interface for Individual Potentiometers • Wiper Resistance: 40Ω Typical • Non-Volatile Storage of Wiper Positions • Power On Recall. Loads Saved Wiper Position on PowerUp. • Standby Current < 20µA Max • Maximum Wiper Current: 3mA • VCC: 2.7V to 5.5V Operation • 2.8kΩ,10kΩ, 50kΩ, 100kΩ Version of Total Pot Resistance • Endurance: 100, 000 Data Changes per Bit per Register • 100 yr. Data Retention • 24 Ld TSSOP • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout X9252 (24 LD TSSOP) TOP VIEW DS0 A0 RW3 RH3 RL3 U/D VCC RL0 RH0 RW0 A2 WP 1 2 3 4 5 6 7 8 9 10 11 12 X9252 24 23 22 21 20 19 18 17 16 15 14 13 DS1 SCL RL2 RH2 RW2 CS VSS RW1 RH1 RL1 A1 SDA 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9252 Ordering Information PART NUMBER X9252YV24I-2.7 X9252YV24IZ-2.7 (Note) X9252WS24I-2.7 X9252WS24IZ-2.7 (Note) X9252WV24I-2.7 X9252WV24IZ-2.7 (Note) X9252US24I-2.7 X9252US24IZ-2.7 (Note) X9252UV24I-2.7 X9252UV24IZ-2.7 (Note) X9252TS24I-2.7 X9252TS24IZ-2.7 (Note) X9252TV24I-2.7 X9252TV24IZ-2.7 (Note) X9252TS Z G X9252TV G X9252TV Z G X9252US Z G X9252UV G X9252UV Z G 100 PART MARKING X9252YV G X9252YV Z G X9252WS G X9252WS Z G X9252WV G X9252WV Z G 50 10 RTOTAL (kΩ) 2.8 TEMP RANGE (°C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-Free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagram VCC A2 A1 A0 SDA SCL Up-Down Interface POWER UP, INTERFACE CONTROL AND STATUS 2-Wire Interface WCR0 DR00 DR01 DR02 DR03 DCP0 WCR1 DR10 DR11 DR12 DR13 DCP1 WCR2 DR20 DR21 DR22 DR23 DCP2 WCR3 DR30 DR31 DR32 DR33 DCP3 RH0 RH1 RH2 RH3 DS0 DS1 CS U/D VSS WP RW0 RL0 RW1 RL1 RW2 RL2 RW3 RL3 Pin Descriptions TSSOP PIN 1 2 3 4 5 SYMBOL DS0 A0 RW3 RH3 RL3 DCP select for Up/Down interface. Device address for 2-wire bus. Wiper terminal of DCP3. High terminal of DCP3. Low terminal of DCP3. BRIEF DESCRIPTION 2 FN8167.1 September 14, 2005 X9252 Pin Descriptions (Continued) TSSOP PIN 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SYMBOL U/D VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 VSS CS RW2 RH2 RL2 SCL DS1 BRIEF DESCRIPTION Increment/decrement for up/down interface. System supply voltage Low terminal of DCP0. High terminal of DCP0. Wiper terminal of DCP0. Device address for 2-wire bus. Hardware write protect Serial data input/output for 2-wire bus. Device address for 2-wire bus. Low terminal of DCP1. High terminal of DCP1. Wiper terminal DCP1. System ground Chip select for Up/Down interface. Wiper terminal of DCP2. High terminal of DCP2. Low terminal of DCP2. Serial clock for 2-wire bus. DCP select for up/down interface. Pin Descriptions Bus Interface Pins Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for the 2-wire interface. It receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. SDA requires an external pull-up resistor, since it’s an open drain output. Serial Clock (SCL) This input is the serial clock of the 2-wire and Up/Down interface. Device Address (A2-A0) The Address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the X9252. A maximum of 8 devices may occupy the 2-wire serial bus. Chip Select (CS) When the CS pin is low, increment or decrement operations are possible using the SCL and U/D pins. The 2-wire interface is disabled at this time. When CS is high, the 2-wire interface is enabled. Up or Down Control (U/D) The U/D input pin is held HIGH during increment operations and held LOW during decrement operations. DCP Select (DS1-DS0) The DS1-DS0 select one of the four DCPs for an Up/Down interface operation. Hardware Write Protect Input (WP) When the WP pin is set low, “write” operations to non volatile DCP Data Registers are disabled. This includes both 2-wire interface non-volatile “Write”, and Up/Down interface “Store” operations. DCP Pins RH0, RL0, RH1, RL1, RH2, RL2, RH3, and RL3 These pins are equivalent to the terminal connections on mechanical potentiometers. Since there are 4 DCPs, there is one set of RH and RL for each DCP. RW0, RW1, RW2, and RW3 The wiper pins are equivalent to the wiper terminal of mechanical potentiometers. Since there are four DCPs, there are 4 RW pins. 3 FN8167.1 September 14, 2005 X9252 Absolute Maximum Ratings Junction Temperature under bias. . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any digital interface pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage at any DCP pin with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to VCC Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Recommended Operating Conditions Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VCC)(Note 4) Limits . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. TEST CONDITIONS Y, W, U, T versions respectively -20 25°C, each DCP 0.75 See test circuit Wiper current = VCC RTOTAL Vss Ref: 1kHz -120 0.4 V(RH0)=V(RH1)=V(RH2)=V(RH3)=VCC V(RL0)=V(RL1)=V(RL2)=V(RL3)=VSS -1 -0.3 ±300 -20 See equivalent circuit Voltage at pin from VSS to VCC Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS fSCL = 400kHz;SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) fSCL = 200kHz; (for U/D interface, increment, decrement) fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) MIN MAX 3 3 5 20 UNITS mA mA mA µA 10/10/25 0.1 10 +20 +1 +0.3 -3.0 50 MIN TYP (Note 4) 2.8, 10, 50, 100 +20 50 2.0 +3.0 150 MAX UNIT kΩ % mW % mA Ω PARAMETER End to end resistance End to end resistance tolerance Power rating RTOTAL Matching IW (Note 5) RW DCP to DCP resistance matching Wiper current Wiper resistance VTERM Voltage on any DCP pin Noise (Note 5) Resolution Absolute linearity (Note 1) Relative linearity (Note 2) Temperature coefficient of resistance (Note 5) Ratiometric Temperature (Note 5) Coefficient Vcc V dBV % MI (Note 3) MI (Note 3) ppm/°C ppm/°C pF µA CH/CL/CW IOL Potentiometer Capacitance (Note 5) Leakage on DCP pins DC Electrical Specifications SYMBOL ICC1 ICC2 ICC3 ISB PARAMETER VCC supply current (Volatile write/read) VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) 4 FN8167.1 September 14, 2005 X9252 DC Electrical Specifications SYMBOL IL VIH VIL VOL Over the recommended operating conditions unless otherwise specified. (Continued) TEST CONDITIONS Voltage at pin from VSS to VCC MIN -10 VCC x 0.7 -1 IOL = 3mA MAX 10 VCC + 1 VCC x 0.3 0.4 UNITS µA V V V PARAMETER Leakage current, bus interface pins Input HIGH voltage Input LOW voltage SDA pin output LOW voltage Endurance and Data Retention PARAMETER Minimum endurance Data retention MIN 100,000 100 UNITS Data changes per bit Years Capacitance Symbol Test Test Conditions VOUT = 0V VIN = 0V Max. 8 6 Units pF pF CIN/OUT (Note 5) Input / Output capacitance (SDA) CIN (Note 5) Input capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and A0) Power-Up Timing SYMBOL tD (Notes 5, 9) PARAMETER Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall completed, and communication interfaces ready for operation. MAX 2 UNITS ms A.C. Test Conditions Input Pulse Levels Input rise and fall times Input and output timing threshold level External load at pin SDA VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 2.3kΩ to VCC and 100pF to VSS 2-Wire Interface timing (s) SYMBOL fSCL tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR (Note 5) tF (Note 5) tAA (Note 5) tDH tIN (Note 5) Clock Frequency Clock High Time Clock Low Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Pulse Width Suppression Time at SCL and SDA inputs 0 50 600 1300 600 600 600 100 30 300 300 0.9 PARAMETER MIN MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns µs ns ns 5 FN8167.1 September 14, 2005 X9252 2-Wire Interface timing (s) (Continued) SYMBOL tBUF (Note 5) tSU:WPA (Note 5) tHD:WPA (Note 5) PARAMETER Bus Free Time (Prior to Any Transmission) A0, A1, A2 and WP Setup Time A0, A1, A2 and WP Hold Time MIN 1200 600 600 MAX UNITS ns ns ns SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:STA SDA (Input Timing) tSU:DAT tHD:DAT tSU:STO tHD:STA tAA SDA (Output Timing) tDH tBUF WP, A0, A1, and A2 Pin Timing START SCL STOP Clk 1 SDA IN tSU:WP WP, A0, A1, or A2 tHD:WP Increment/Decrement Timing SYMBOL tCI tID (Note 5) tDI (Note 5) tIL tIH tIC tCPHS tCPHNS (Note 5) tIW (Note 5) tCYC CS to SCL Setup SCL HIGH to U/D, DS0 or DS1 change U/D, DS0 or DS1 to SCL setup SCL LOW period SCL HIGH period SCL inactive to CS inactive (Nonvolatile Store Setup Time) CS deselect time (STORE) CS deselect time (NO STORE) SCL to RW change SCL cycle time 5 500 PARAMETER MIN 600 600 600 2.5 2.5 1 10 1 100 500 TYP (Note 4) MAX UNITS ns ns ns µs µs µs ms µs µs µs µs tR, tF (Note 5) SCL input rise and fall time 6 FN8167.1 September 14, 2005 X9252 Increment/Decrement Timing CS tCYC tCI SCL tIL tIH tIC tCPHS 90% 90% 10% tID tDI tF tR tCPHNS U/D DS0, DS1 tIW RW MI (3) High-Voltage Write Cycle Timing SYMBOL tWC (Notes 5, 8) Non-volatile write cycle time PARAMETER TYP 5 MAX 10 UNITS ms XDCP Timing SYMBOL tWRL (Note 5) PARAMETER SCL rising edge to wiper code changed, wiper response time after instruction issued (all load instructions) MIN 5 MAX 20 UNITS µs NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/255 + V(RL), with n from 0 to 255. 2. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) + MI)]/MI, with n from 0 to 254 3. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/255. 4. Typical values are for TA = 25°C and nominal supply voltage. 5. This parameter is not 100% tested. 6. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2)] x 106, with T1 & T2 being 2 temperatures, and n from 0 to 255. 7. Measured with wiper at tap position 255, RL grounded, using test circuit. 8. tWC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle. 9. The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power up, the data sheet parameters for the DCP do not fully apply until tD after VCC reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant store, bring the CS pin high before or concurrently with the VCC pin on power up. 7 FN8167.1 September 14, 2005 X9252 Test Circuit Test Point Equivalent Circuit RTOTAL RH CH Force Current RW CW CL RL RW Principles of Operation The X9252 is an integrated circuit incorporating four resistor arrays, their associated registers and counters, and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: - Resistor Array - Up/Down Interface - 2-wire Interface Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select and enable one of 256 switches (see Table 1). Note that each wiper has a dedicated WCR. When all bits of a WCR are zeroes, the switch closest to the corresponding RL pin is selected. When all bits of a WCR are ones, the switch closest to the corresponding RH pin is selected. The WCR is volatile and may be written directly. There are four non-volatile Data Registers (DR) associated with each WCR. Each DR can be loaded into WCR. All DRs and WCRs can be read or written. Resistor Array Description The X9252 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi inputs) (See Figure 1.) At both ends of each array and between each resistor segment is a switch connected to the wiper (RWi) pin. Power Up and Down Requirements During power up, CS must be high, to avoid inadvertant “store” operations. At power up, the contents of Data Registers DR00, DR10, DR20, and DR30, are loaded into the corresponding wiper counter register. i = 0, 1, 2, and 3 WCR[7:0] = FF hex Volatile 8-bit Wiper Counter Register WCRi 255 RHi 254 Four Non-Volatile Data Registers DRi0, DRi1, DRi2, and DRi3 253 252 One of 256 Decoder WP SCL SDA A2, A1, A0 CS U/D DS1, DS0 WCR[7:0] = 00 hex 0 RLi RWi Interface Control and Volatile Status Register (SR) (Shared by the Four DCPs) 1 2 FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP 8 FN8167.1 September 14, 2005 X9252 Up/Down Interface Operation The SCL, U/D, CS, DS0 and DS1 inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and SCL inputs. HIGH to LOW transitions on SCL will increment or decrement (depending on the state of the U/D input) a wiper counter register selected by DS0 and DS1. The output of this counter is decoded to select one of 256 wiper positions along the resistor array. The value of the counter is stored in nonvolatile Data Registers DRi0 whenever CS transitions HIGH while the SCL and WP inputs are HIGH. “i” indicates the DCP number selected with pins DS1 and DS0. During a “Store” operation bits DRSel1 and DRSel0 in the Status Register must be both “0”, which is their power up default value. Other combinations are reserved and must not be used. The system may select the X9252, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep SCL LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperate drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. The 2-wire interface is disabled while CS remains LOW. TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL DS1 0 0 1 1 DS0 0 1 0 1 SELECTED DCP DCP0 DCP1 DCP2 DCP3 Mode Selection for Up/Down Control CS L L H SCL U/D H L X Wiper Up Wiper Down Store Wiper Position to nonvolatile memory if WP pin is high. No store, return to standby, if WP pin is low. Standby No Store, Return to Standby Wiper Up (not recommended) Wiper Down (not recommended) MODE H X L L L X X H L 2-Wire Serial Interface Protocol Overview The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X9252 operates as a slave in all applications. All 2-wire interface operations must begin with a START, followed by a Slave Address byte. The Slave Address selects the X9252, and specifies if a Read or Write operation is to be performed. All Communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions (See Figure 2). On power up of the X9252, the SDA pin is in the input mode. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met (See Figure 2). Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus (See Figure 2). 9 FN8167.1 September 14, 2005 X9252 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL from Master 1 8 9 SDA Output from Transmitter SDA Output from Receiver START ACK FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER Serial Acknowledge An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 3). The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 0101, and the Device Address bits matching the logic state of pins A2, A1, and A0 (See Figure 4). If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to figure 4.). This byte includes three parts: - The four MSBs (SA7-SA4) are the Device Type Identifier, which must always be set to 0101 in order to select the X9252. - The next three bits (SA3-SA1) are the Device Address bits (AS2-AS0). To access any part of the X9252’s memory, the value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. - The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. When the R/W bit is “1”, then a Read operation is selected. A “0” selects a Write operation. SA7 0 SA6 1 SA5 0 SA4 1 SA3 AS2 SA2 AS1 SA1 AS0 SA0 R/W Device Type Identifier Device Address Read or Write SLAVE ADDRESS BIT(S) SA7-SA4 SA3-SA1 SA0 DESCRIPTION Device Type Identifier Device Address Read or Write Operation Select FIGURE 4. SLAVE ADDRESS (SA) FORMAT 10 FN8167.1 September 14, 2005 X9252 Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X9252 initiates an internal high voltage write cycle. This cycle typically requires 5ms. During this time, any Read or Write command is ignored by the X9252. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed. During acknowledge polling, the master first issues a START condition followed by a Slave Address Byte. The Slave Address Byte contains the X9252’s Device Type Identifier and Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is busy within the high voltage cycle, then no ACK is returned. If the high voltage cycle is completed, an ACK is returned and the master can then proceed with a new Read or Write operation. (Refer to figure 5.) Byte load completed by issuing STOP. Enter ACK Polling 2-Wire Serial Interface Operation X9252 Digital Potentiometer Register Organization Refer to the Functional Diagram on page 2. There are four Digitally Controlled Potentiometers, referred to as DCPi, i=0,1,2,3. Each potentiometer has one volatile Wiper Control Register (WCR) with the corresponding number, WCRi, i=0,1,2,3. Each potentiometer also has four nonvolatile registers to store wiper position or general data, these are numbered DRi0, DRi1, DRi2 and DRi3, i=0,1,2,3. The registers are organized in five pages of four, with one page consisting of the WCRi (i=0-3), a second page containing the DRi0 (i=0-3), a third page containing the DRi1, and so forth. These pages can be written to four bytes at time. In this manner all four potentiometer WCRs can be updated in a single serial write (see “Page Write Operation”), as well as all four registers of a given page in the DR array. The unique feature of the X9252 device is that writing or reading to a Data Register of a given DCP automatically updates/moves the WCR of that DCP with the content of the DR. In this manner data can be moved from a particular DCP register to that DCP’s WCR just by performing a 2-wire read operation. Simultaneously, that data byte can be utilized by the host. Issue START Issue Slave Address Byte (Read or Write) Issue STOP Status Register Organization The Status Register (SR) is used in read and write operations to select the appropriate DCP register. Before any DCP register can be accessed, the SR must be set to the correct value. It is accessed by setting the Address Byte to 07h (See Table 3). Do this by Writing the Slave Address followed by a Byte Address of 07h. The SR is volatile and defaults to 00h on power up. It is an 8-bit register containing three control bits in the 3 LSBs as follows: 7 6 5 Reserved 4 3 2 DRSel1 1 DRSel0 0 NVEnable ACK returned? NO YES High Voltage complete. Continue command sequence. NO YES Continue normal Read or Write command sequence Issue STOP Bits DRSel1 and DRSel0 determine which Data Register of a DCP is selected for a given operation. NVEnable is used to select the volatile WCR if “0”, and one of the nonvolatile DCP registers if “1”. Table 2 shows this register organization. “Store” operations using the Up/Down interface require that bits DRSel1 and DRSel0 are set to “0”. PROCEED FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE 11 FN8167.1 September 14, 2005 X9252 TABLE 2. REGISTER NUMBERING STATUS REG (Note 1) (Addr: 07H) RESERVED BITS 7-3 Reserved DRSel1 bit 2 X 0 0 1 1 DRSel0 bit 1 X 0 1 0 1 NVEnable bit 0 0 1 1 1 1 DCP0 (Addr: 00h) WCR0 DR00 DR01 DR02 DR03 REGISTERED SELECTED (Note 2) DCP1 (Addr: 01h) WCR1 DR10 DR11 DR12 DR13 DCP2 (Addr: 02h) WCR2 DR20 DR21 DR22 DR23 DCP3 (Addr: 03h) WCR3 DR30 DR31 DR32 DR33 To read or write the contents of a single Data Register or Wiper Register: 1. Load the status register (using a write command) to select the row (See Figure 6) Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This Status Register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example, writing ‘03h’ to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to move to WCR3. Writing a 0 to bit ‘0’ of the Status Register specifies that the subsequent read or write command will access a Wiper Counter Register. Each WCR can be written to individually, without affecting the contents of any other. 2. Access the desired DR or WCR using a new write or read command (see Figure 7 for write and Figure 9 for read.) Specify the desired column (DCP number) by sending the DCP address as part of this read or write command. If bit 0 of data byte = 1, DR contents move to WCR during this ACK period S t a r t Signals from the Master Slave Address Status Register Address DR select Data S t o p Signal at SDA 0101 Signals from the Slave 0 A C K 00000111 A C K 00000x x1 A C K FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER) 12 FN8167.1 September 14, 2005 X9252 DCP Addressing for 2-Wire Interface Once the register number has been selected by a 2-wire instruction, then the DCP number is determined by the Address Byte of the following instruction. Note again that this enables a complete page write of the DRs of all four potentiometers at once. The register addresses accessible in the X9252 include: TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE ADDRESS (HEX) 0 1 2 3 4 5 6 7 CONTENTS DCP 0 DCP 1 DCP 2 DCP 3 Not Used Not Used Not Used Status Register not respond to any requests from the master. The SDA output is at high impedance. The SR bits and WP pin determine the register being accessed through the 2-wire interface (See Table 2). As noted before, any write operation to a Data Register (DR), also transfers the contents of all the data registers in that row to their corresponding WCR. For example, to write 3Ahex to the Data Register 1 of DCP2 the following sequence is required: START Slave Address ACK Address Byte ACK Data Byte ACK STOP START Slave Address ACK Address Byte ACK Data Byte ACK STOP 0101 0000 0000 0010 0011 1010 (Hardware address = 000, Write command) (Access DCP2) (Write Data Byte 3Ah) 0101 0000 0000 0111 0000 0011 (Hardware Address = 000, and a Write command) (Indicates Status Register address) (Data Register 1 and NVEnable selected) note: at this ACK, the WCRs are all updated with their respective DR. All other address bits in the Address Byte must be set to “0” during 2-wire write operations and their value should be ignored when read. Byte Write Operation For any Byte Write operation, the X9252 requires the Slave Address byte, an Address Byte, and a Data Byte (See Figure 7). After each of them, the X9252 responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if the write operation is to a volatile register (WCR, or SR), the X9252 is ready for the next read or write operation. If the write operation is to a nonvolatile register (DR), and the WP pin is high, the X9252 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X9252 does Write Signals from the Master S t a r t Slave Address During the sequence of this example, WP pin must be high, and A0, A1, and A2 pins must be low. When completed, the DR21 register and the WCR2 will be set to 3Ah and the other Data Register in Row 1 will transfer their other contents to the respective WCR’s. Address Byte Data Byte S t o p Signal at SDA Signals from the Slave 01 01 0 A C K A C K A C K FIGURE 7. BYTE WRITE SEQUENCE 13 FN8167.1 September 14, 2005 X9252 Page Write Operation As stated previously, the memory is organized as a single Status Register (SR), and four pages of four registers each. Each page contains one Data Register for each DCP. The order of the bytes within a page is DR0i, followed by DR1i, followed by DR2i, and then DR3i, with i being the Data Register number (0, 1, 2, or 3). Normally a page write operation will be used to efficiently update all four data registers and WCR in a single write command, starting at DCP0 and finishing with DCP3. In order to perform a Page Write operation to the memory array, the NVEnable bit in the SR must first be set to “1”. A Page Write operation is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 4 bytes (See Figure 8). After the receipt of each byte, the X9252 responds with an ACK, and the internal DCP address counter is incremented by one. The page address remains constant. When the counter reaches Write Signals from the Master S t a r t the end of the page (DR3i, 03hex), it “rolls over” and goes back to the first byte of the same page (DR0i, 00hex). For example, if the master writes 3 bytes to a page starting at location DR22, the first 2 bytes are written to locations DR22 and DR32, while the last byte is written to locations DR02. Afterwards, the DCP counter would point to location DR12. If the master supplies more than 4 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the loading of Data Bytes by issuing a STOP condition, which initiates the nonvolatile write cycle. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. If the WP pin is low, the nonvolatile write cycle doesn’t start and the bytes are discarded. Notice that the Data Bytes are also written to the WCR of the corresponding DCPs, therefore in the above example, WCR2, WCR3, and WCR0 are also written and WCR1 is updated with the contents of DR12. 2 R2 FUNCTION GENERATOR C + } RA R2 R1 + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 17 FN8167.1 September 14, 2005 X9252 Application Circuits (Continued) V+ WINDOW COMPARATOR mR nR } } VUL + VS V+ + VLL VR + SHUNT LIMITER pR } VS VO + VO FUNCTION GENERATOR C mR nR } } pR } + VO + 18 FN8167.1 September 14, 2005 X9252 Packaging Information 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0°-8° .020 (.50) .030 (.75) Detail A (20X) Seating Plane (1.78) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) (4.16) (7.72) ALL MEASUREMENTS ARE TYPICAL All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN8167.1 September 14, 2005