X9259EVAL

DATASHEET X9259 FN8169 Rev 6.00 December 12, 2014 Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled (XDCP™) Potentiometers Features The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. • Four separate potentiometers in one package The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. • 256 resistor taps–0.4% resolution • 2-wire serial interface for write, read, and transfer operations of the potentiometer • Wiper resistance: 100Ω typical at VCC = 5V • 4 nonvolatile data registers for each potentiometer • Nonvolatile storage of multiple wiper positions • Standby current VH, VL, and VW. 14. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254. FN8169 Rev 6.00 December 12, 2014 Page 12 of 21 X9259 DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC supply current (active) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) 3 mA ICC2 VCC supply current (nonvolatile write) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) 5 mA ISB VCC current (standby) VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) 5 µA ILI Input leakage current VIN = VSS to VCC 10 µA ILO Output leakage current VOUT = VSS to VCC 10 µA VIH Input HIGH voltage VIL Input LOW voltage VOL Output LOW voltage IOL = 3mA VOH Output HIGH voltage IOH = -1mA, VCC  +3V VCC - 0.8 V VOH Output HIGH voltage IOH = -0.4mA, VCC  +3V VCC - 0.4 V VCC x 0.7 V VCC x 0.3 V 0.4 V Endurance and Data Retention PARAMETER Minimum endurance MIN UNITS 100,000 Data changes per bit per register 100 years Data retention Capacitance SYMBOL TEST MAX UNITS TEST CONDITIONS CIN/OUT (Note 15) Input / Output capacitance (SDA) 8 pF VOUT = 0V CIN (Note 15) 6 pF VIN = 0V Input capacitance (SCL, WP, A2, A1 and A0) Power-up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 15) VCC Power-up rate tPUR (Note 16) Power-up to initiation of read operation 1 ms tPUW (Note 16) Power-up to initiation of write operation 50 ms 0.2 V/ms AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 NOTES: 15. This parameter is not 100% tested 16. tPUR and tPUW are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. FN8169 Rev 6.00 December 12, 2014 Page 13 of 21 X9259 Equivalent AC Load Circuit 5V SPICE Macromodel 1533Ω RTOTAL RH SDA pin RL CW CL CL 10pF 100pF 25pF 10pF RW AC Timing SYMBOL PARAMETER MIN MAX UNITS 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns Noise Suppression Time Constant at SCL and SDA inputs 50 ns 1200 ns TI tBUF Bus Free Time (Prior to Any Transmission) tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL PARAMETER tWR High-voltage write cycle time (store instructions) TYP MAX UNITS 5 10 ms XDCP Timing SYMBOL tWRPO tWRL PARAMETER MIN MAX UNITS Wiper response time after the third (last) power supply is stable 5 10 µs Wiper response time after instruction issued (all load instructions) 5 10 µs FN8169 Rev 6.00 December 12, 2014 Page 14 of 21 X9259 Symbol Table WAVEFORM . INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA FN8169 Rev 6.00 December 12, 2014 tDH Page 15 of 21 X9259 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 FN8169 Rev 6.00 December 12, 2014 Page 16 of 21 X9259 Applications Information Basic Configurations of Electronic Potentiometers +VR VR RW I Three-terminal Potentiometer; Variable voltage divider Two-terminal Variable Resistor; Variable current Application Circuits Non inverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS – + VO 100kΩ – VO + +12V FN8169 Rev 6.00 December 12, 2014 10kΩ } 10kΩ } TL072 10kΩ R1 R2 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) -12V Page 17 of 21 X9259 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO – – R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G VS -1/2  G  +1/2 R2 } VS R1 } Inverting Amplifier Equivalent L-R Circuit R2 C1 – VS VO + + – R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – R1 – + } RA + } RB frequency  R1, R2, C amplitude  RA, RB FN8169 Rev 6.00 December 12, 2014 Page 18 of 21 X9259 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 12, 2014 FN8169.6 CHANGE Updated Datasheet to Intersil new standards. Updated Ordering Information Table on page 2, by removing obsoleted parts and 100kΩ referenced parts, adding Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”. On page 3. in the Pin Descriptions table removed duplicate entry for Pin 6. Added Revision History and About Intersil Verbiage Updated M24.3 POD to the latest revision. -“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern.” Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24LD version. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2005-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8169 Rev 6.00 December 12, 2014 Page 19 of 21 X9259 Package Outline Drawing M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 2, 3/11 24 INDEX AREA 7.60 (0.299) 7.40 (0.291) 10.65 (0.419) 10.00 (0.394) DETAIL "A" 1 2 3 TOP VIEW 1.27 (0.050) 0.40 (0.016) SEATING PLANE 2.65 (0.104) 2.35 (0.093) 15.60 (0.614) 15.20 (0.598) 0.75 (0.029) x 45° 0.25 (0.010) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 8° 0° 0.32 (0.012) 0.23 (0.009) SIDE VIEW “B” SIDE VIEW “A” 1.981 (0.078) 9.373 (0.369) 1.27 (0.050) NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. 0.533 (0.021) TYPICAL RECOMMENDED LAND PATTERN FN8169 Rev 6.00 December 12, 2014 Page 20 of 21 X9259 Package Outline Drawing M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 SEE DETAIL "X" 13 24 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 12 0.15 +0.05 -0.06 B 0.65 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90 +0.15 -0.10 1.20 MAX GAUGE PLANE SEATING PLANE 0.25 +0.05 -0.06 0.10 M C B A 0.10 C 5 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.25 0.60± 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153. FN8169 Rev 6.00 December 12, 2014 Page 21 of 21