X9259TV24Z-2.7

® X9259 Single Supply/Low Power/256-Tap/2-Wire bus Data Sheet April 13, 2007 FN8169.5 Quad Digitally-Controlled (XDCP™) Potentiometers The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four Separate Potentiometers in One Package • 256 Resistor Taps–0.4% Resolution • 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Wiper Resistance: 100Ω typical @ VCC = 5V • 4 Non-volatile Data Registers for Each Potentiometer • Non-volatile Storage of Multiple Wiper Positions • Standby Current VH, VL, and VW. 5. n = 0, 1, 2, …,255; m =0, 1, 2, …, 254. 13 FN8169.5 April 13, 2007 X9259 DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. LIMITS SYMBOL ICC1 PARAMETER VCC supply current (active) VCC supply current (non-volatile write) TEST CONDITIONS fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Non-volatile Write State only) VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 VCC x 0.3 IOL = 3mA IOH = -1mA, VCC ≥ +3V IOH = -0.4mA, VCC ≤ +3V VCC - 0.8 VCC - 0.4 0.4 MIN TYP MAX 3 UNITS mA ICC2 5 mA ISB ILI ILO VIH VIL VOL VOH VOH VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage 5 10 10 μA μA μA V V V V V Endurance and Data Retention PARAMETER Minimum endurance Data retention MIN 100,000 100 UNITS Data changes per bit per register years Capacitance SYMBOL CIN/OUT (Note 6) CIN (Note 6) TEST Input / Output capacitance (SDA) Input capacitance (SCL, WP, A2, A1 and A0) MAX 8 6 UNITS pF pF TEST CONDITIONS VOUT = 0V VIN = 0V Power-up Timing SYMBOL tr VCC (Note 6) tPUR (Note 7) tPUW (Note 7) PARAMETER VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation MIN 0.2 1 50 MAX UNITS V/ms ms ms A.C. Test Conditions Input Pulse Levels Input rise and fall times Input and output timing level NOTES: 6. This parameter is not 100% tested 7. tPUR and tPUW are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 14 FN8169.5 April 13, 2007 X9259 Equivalent A.C. Load Circuit 5V 1533Ω SDA pin 100pF 10pF RH SPICE Macromodel RTOTAL RL CL CW 25pF CL 10pF RW AC Timing SYMBOL fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) A0, A1 Setup Time A0, A1 Hold Time 0 50 1200 0 0 2500 600 1300 600 600 600 100 30 300 300 0.9 PARAMETER MIN MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns ns μs ns ns ns ns ns High-Voltage Write Cycle Timing SYMBOL tWR PARAMETER High-voltage write cycle time (store instructions) TYP 5 MAX 10 UNITS ms XDCP Timing SYMBOL tWRPO tWRL PARAMETER Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) MIN 5 5 MAX 10 10 UNITS μs μs 15 FN8169.5 April 13, 2007 X9259 Symbol Table WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance . Timing Diagrams Start and Stop Timing (START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF (STOP) Input Timing tCYC SCL tLOW SDA tSU:DAT tHD:DAT tBUF tHIGH Output Timing SCL SDA tAA tDH 16 FN8169.5 April 13, 2007 X9259 XDCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL VWx Write Protect and Device Address Pins Timing (START) SCL ... (Any Instruction) ... SDA ... tSU:WPA WP A0, A1 tHD:WPA (STOP) 17 FN8169.5 April 13, 2007 X9259 Applications Information Basic Configurations of Electronic Potentiometers VR +VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Non inverting Amplifier VS + – VO VIN 317 R1 R2 R1 Iadj R2 VO (REG) Voltage Regulator VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 VS 100kΩ – + TL072 10kΩ 10kΩ +12V 10kΩ -12V VO R2 Comparator with Hysteresis VS – + VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 18 FN8169.5 April 13, 2007 X9259 Application Circuits (continued) Attenuator C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 R2 – + VO VS R R2 + – VO Filter VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + C1 VO VS R2 + – VO = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 19 FN8169.5 April 13, 2007 X9259 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8° Rev. 1 4/06 MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 A1 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.010 0.016 24 0° 8° 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 24 0° 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 20 FN8169.5 April 13, 2007 X9259 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. A A1 A2 b c D E E1 e H 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max ±0.05 ±0.05 +0.05/-0.06 +0.05/-0.06 ±0.10 Basic ±0.10 Basic ±0.15 Reference Rev. F 2/07 E E1 1 B TOP VIEW (N/2) 0.20 C B A 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 L L1 NOTES: b 0.10 C N LEADS SIDE VIEW 0.10 M C A B 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0° - 8° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8169.5 April 13, 2007