X9271_11

X9271 Single Supply/Low Power/256-Tap/SPI Bus Data Sheet June 23, 2011 FN8174.3 Single, Digitally Controlled (XDCP™) Potentiometer FEATURES • 256 Resistor Taps • SPI Serial Interface for Write, Read, and Transfer Operations of Potentiometer • Wiper Resistance, 100Ω typical @ VCC = 5V • 16 Nonvolatile Data Registers • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall; Loads Saved Wiper Position on Power-up • Standby Current < 3µA Max • VCC = 2.7V to 5.5V Operation • 50kΩ, 100kΩ Versions of End-to-End Resistance • 100-yr Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 14-Lead TSSOP • Low-power CMOS • Pb-free Plus Anneal Available (RoHS Compliant) FUNCTIONAL DIAGRAM DESCRIPTION The X9271 integrates a single, digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented by using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to and read by the user. The contents of the WCR control the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications. including control, parameter adjustments, and signal processing. VCC RH SPI Bus Interface Address Data Status Write Read Transfer Inc/Dec Bus Interface and Control Control Power-on Recall Wiper Counter Register (WCR) Data Registers 16 Bytes 50kΩ and 100kΩ 256 Taps POT VSS RW RL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2011. All Rights Reserved XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. X9271 Ordering Information PART NUMBER (Notes 1, 3) X9271UV14IZ (Note 2) X9271UV14Z (Note 2) X9271TV14 (Note 4) PART MARKING X9271 UVZI X9271 UVZ X9271 TV VCC LIMITS (V) 5 ±10% 5 ±10% 5 ±10% 2.7 to 5.5 5 ±10% 5 ±10% 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 POTENTIOMETER TEMP. RANGE ORGANIZATION (kΩ) (°C) 50 50 100 100 100 100 50 50 50 50 100 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 0 to +70 PACKAGE PKG. DWG. # 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) 14 Ld TSSOP (4.4mm) M14.173 M14.173 X9271TV14I-2.7T1 (Note 4) X9271 TVG X9271TV14IZ (Note 2) X9271TV14Z (Note 2) X9271UV14I-2.7 (Note 4) X9271UV14IZ-2.7 (Note 2) X9271UV14Z-2.7 (Note 2) X9271TV14IZ-2.7 (Note 2) X9271TV14Z-2.7 (Note 2) NOTES: X9271 TVZI X9271 TVZ X9271 UVG X9271 UVZG X9271 UVZF X9271 TVZG X9271 TVZF 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363. 4. Not recommended for new designs. 2 FN8174.3 June 23, 2011 X9271 DETAILED FUNCTIONAL DIAGRAM VCC 50kΩ and 100kΩ 256 Taps Bank 0 Power-on Recall HOLD CS SCK SO SI A0 A1 WP R0 R1 Wiper Counter Register (WCR) RH Interface and Control Circuitry DATA R2 R3 RL RW Bank 1 R0 R1 Bank 2 R0 R1 Bank 3 R0 R1 Control R2 R3 R2 R3 R2 R3 12 Additional Nonvolatile Registers 3 Banks of 4 Registers x 8 Bits VSS CIRCUIT-LEVEL APPLICATIONS • Vary the gain of a voltage amplifier. • Provide programmable DC reference voltages for comparators and detectors. • Control the volume in audio circuits. • Trim out the offset voltage error in a voltage amplifier circuit. • Set the output voltage of a voltage regulator. • Trim the resistance in Wheatstone bridge circuits. • Control the gain, characteristic frequency, and Q-factor in filter circuits. • Set the scale factor and zero point in sensor signal conditioning circuits. • Vary the frequency and duty cycle of timer ICs. • Vary the DC biasing of a pin diode attenuator in RF circuits. • Provide a control variable (I, V, or R) in feedback circuits. SYSTEM-LEVEL APPLICATIONS • Adjust the contrast in LCD displays. • Control the power level of LED transmitters in communication systems. • Set and regulate the DC biasing point in an RF power amplifier in wireless systems. • Control the gain in audio and home entertainment systems. • Provide the variable DC bias for tuners in RF wireless systems. • Set the operating points in temperature control systems. • Control the operating point for sensors in industrial systems. • Trim offset and gain errors in artificial intelligence systems. 3 FN8174.3 June 23, 2011 X9271 PIN CONFIGURATION TSSOP S0 A0 NC CS SCK SI VSS 1 2 3 4 5 6 7 X9271 14 13 12 11 10 9 8 VCC RL RH RW HOLD A1 WP PIN ASSIGNMENTS TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol SO A0 NC CS SCK SI VSS WP A1 HOLD RW RH RL VCC Serial Data Output Device Address No Connect Chip Select Serial Clock Serial Data Input System Ground Hardware Write Protect Device Address Function Device Select. Pause the serial bus. Wiper Terminal of Potentiometer High Terminal of Potentiometer Low Terminal of Potentiometer System Supply Voltage 4 FN8174.3 June 23, 2011 X9271 PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The Serial Output (SO) is the serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) The wiper pin (RW) is equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The Serial Input (SI) is the serial data input pin. All operational codes, byte addresses, and data to be written to the potentiometers and potentiometer registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The System Supply Voltage (VCC) pin is the system supply voltage. The Supply Ground (VSS) pin is the system ground. Other Pins HARDWARE WRITE PROTECT INPUT (WP) The Serial Clock (SCK) input is used to clock data into and out of the X9271. HOLD (HOLD) The Hardware Write Protect Input (WP) pin, when LOW, prevents nonvolatile writes to the data registers. NO CONNECT HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is under way, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. DEVICE ADDRESS (A1 - A0) No Connect pins should be left floating. These pins are used for Intersil manufacturing and testing purposes. The Device Address (A1 - A0) inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. CHIP SELECT (CS) When Chip Select (CS) is HIGH, the X9271 is deselected, the SO pin is at high impedance, and (unless an internal write cycle is under way) the device is in standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. 5 FN8174.3 June 23, 2011 X9271 PRINCIPLES OF OPERATION Device Description SERIAL INTERFACE physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array, only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The eight bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (Table 1). POWER-UP AND POWER-DOWN RECOMMENDATIONS The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is composed of a resistor array (Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins, provided that VCC is always more positive than or equal to VH, VL, and VW; i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. SERIAL DATA PATH FROM INTERFACE CIRCUITRY SERIAL BUS INPUT REGISTER 0 (DR0) 8 BANK_0 Only RH C O U N T E R D E C O D E REGISTER 1 (DR1) 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC UP/DN MODIFIED SCK UP/DN CLK REGISTER 2 (DR2) REGISTER 3 (DR3) IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH RL RW FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM 6 FN8174.3 June 23, 2011 X9271 DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9271 contains a Wiper Counter Register (WCR) for the DCP potentiometer. The WCR can be envisioned as an 8-bit parallel and serial load counter, with its outputs decoded to select one of 256 switches along its resistor array (Table 1). The contents of the WCR can be altered in four ways: 1. It can be written directly by the host via the Write Wiper Counter Register instruction (serial load). 2. It can be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load). 3. It can be modified one step at a time by the Increment/ Decrement instruction. 4. It is loaded with the contents of its Data Register zero (DR0) upon power-up. . TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: Used to store current wiper position (Volatile, V) WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V (MSB) V V V V V V V (LSB) . TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV) BIT 7 NV MSB BIT 6 NV BIT 5 NV BIT 4 NV BIT 3 NV BIT 2 NV BIT 1 NV BIT 0 NV LSB TABLE 3. STATUS REGISTER, SR (WIP is 1-bit) WIP (LSB) The WCR is a volatile register; that is, its contents are lost when the X9271 is powered down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loading of the R0 value into the WCR. The DR0 value of Bank 0 is the default value. Data Registers (DR3–DR0) The potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host (Table 2). Data can also be transferred between any of the four Data Registers and the associated WCR. All operations changing data in one of the Data Registers are nonvolatile operations and take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0 ~255). Status Register (SR) The 1-bit Status Register is used to store the system status (Table 3). WIP: Write In Progress status bit; read only. – WIP = 1 indicates that a high-voltage write cycle is in progress. – WIP = 0 indicates that no high-voltage write cycle is in progress 7 FN8174.3 June 23, 2011 X9271 DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE (ID AND A) Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for SPI write and read operations. The data registers in Banks 1, 2, and 3 cannot be used for direct read/write operations to the Wiper Counter Register (Tables 5 and 6). TABLE 4. IDENTIFICATION BYTE FORMAT SET TO 0 FOR PROPER OPERATION 0 0 INTERNAL SLAVE ADDRESS A1 A0 (LSB) The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bit is the device ID for the X9271; this is fixed as 0101[B] (Table 4). The A1 - A0 bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1 - A0 input pins. The slave address is externally specified by the user. The X9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9271 to successfully continue the command sequence. Only the device for which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I[3:0]) DEVICE TYPE IDENTIFIER ID3 0 (MSB) ID2 1 ID1 0 ID0 1 TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE RB 0 0 1 1 RA 0 1 0 1 REGISTER SELECTION 0 1 2 3 OPERATIONS Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write; Wiper Counter Register Operations The next byte sent to the X9271 contains the instruction and register pointer information. The three most significant bits are used to provide the instruction operation code (I[3:0]). The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9271 is single POT, P0 = 0. The format is shown in Table 7. REGISTER BANK SELECTION (R1, R0, P1, P0) TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3) P1 0 0 1 1 P0 0 1 0 1 BANK SELECTION 0 1 2 3 OPERATIONS Data Register Read and Write; Wiper Counter Register Operations Data Register Read and Write Only Data Register Read and Write Only Data Register Read and Write Only There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for the data register to Wiper Counter Register operations. TABLE 7. INSTRUCTION BYTE FORMAT REGISTER BANK SELECTION FOR SP1 REGISTER WRITE AND READ OPERATIONS) INSTRUCTION OPCODE I3 (MSB) NOTE: 5. Set to P0 = 0 for potentiometer operations. I2 I1 P0 REGISTER SELECTION RB RA P1 POTENTIOMETER SELECTION (WCR SELECTION) (Note 5) P0 (LSB) 8 FN8174.3 June 23, 2011 X9271 DEVICE DESCRIPTION Instructions Five of the eight instructions are three bytes in length. These instructions are: – Read Wiper Counter Register: Read the current wiper position of the potentiometer. – Write Wiper Counter Register: Change current wiper position of the potentiometer. – Read Data Register: Read the contents of the selected Data Register. – Write Data Register: Write a new value to the selected Data Register. – Read Status: This command returns the contents of the WIP bit, which indicates if the internal write cycle is in progress. See Table 8 for details of the instruction set. The basic sequence of the 3-byte instruction is shown in Figure 2. These 3-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position) to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers, or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (Figure 3). Two instructions require a 2-byte sequence to complete (Figure 4). These instructions transfer data between the host and the X9271; either between the host and one of the data registers, or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register: Transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register: Transfers the contents of the specified Wiper Counter Register to the associated Data Register. The final command is Increment/Decrement (Figures 5 and 6). It is different from the other commands, because its length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment step, thereby providing a fine-tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper moves one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper moves one resistor segment towards the RL terminal. Write-in-Process (WIP) Bit The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by the Write-in-Process bit (WIP). The WIP bit is read with a Read Status command. 9 FN8174.3 June 23, 2011 X9271 CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 ID3 ID2 ID1 ID0 Device ID Instruction Opcode Pot/BankWCR[7:0] valid only when P1 = P0 = 0; Address or Data Register Bit [7:0] for all values of P1 and P0 FIGURE 2. THREE-BYTE INSTRUCTION SEQUENCE (WRITE) CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address Pot/Bank Address X X X X X X X X ID3 ID2 ID1 ID0 Device ID Don’t Care Instruction Opcode S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] valid only when P1 = P0 = 0; or Data Register Bit [7:0] for all values of P1 and P0 FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE (READ) CS SCK SI 0 1 0 1 0 0 0 0 A1 A0 I3 I2 I1 I0 0 0 ID3 ID2 ID1 ID0 Device ID RB RA P1 P0 Register Address Pot/Bank Address Internal Address Instruction Opcode These commands only valid when P1 = P0 = 0 FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE 10 FN8174.3 June 23, 2011 X9271 CS SCL SI 0 1 0 1 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n ID3 ID2 ID1 ID0 Device ID RA RB P1 P0 Register Address Pot/Bank Address Instruction Opcode FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE tWRID SCK SI V W VOLTAGE OUT INC/DEC CMD ISSUED FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS TABLE 8. INSTRUCTION SET INSTRUCTION SET (1/0 = DATA IS ONE OR ZERO) INSTRUCTION Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP Bit) I3 1 1 1 1 1 1 0 0 I2 0 0 0 1 1 1 0 1 I1 0 1 1 0 0 1 1 0 I0 1 0 1 0 1 0 0 1 RB 0 0 1/0 1/0 1/0 1/0 0 0 RA 0 0 1/0 1/0 1/0 1/0 0 0 P1 0 0 1/0 1/0 0 0 0 0 P0 1/0 1/0 1/0 1/0 0 0 0 1 OPERATION Read contents of Wiper Counter Register. Write new value to Wiper Counter Register. Read contents of Data Register pointed to by P1 - P0 and RB - RA. Write new value to Data Register pointed to by P1 - P0 and RB - RA. Transfer contents of Data Register pointed to by RB - RA (Bank 0 only) to Wiper Counter Register. Transfer contents of Wiper Counter Register to Register pointed to by RB-RA (Bank 0 only). Enable increment/decrement of the Wiper Counter Register. Read status of internal write cycle by checking WIP bit. 11 FN8174.3 June 23, 2011 X9271 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 0 1 DR/Bank Addresses 0 0 0 Wiper Position (Sent by X9271 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS Falling Edge 0 0 0 A1 A0 1 W C 0 R 7 CS W Rising C Edge R 0 Write Wiper Counter Register (WCR) Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 1 0 DR/Bank Addresses 0 0 0 W C 0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS Falling Edge 0 0 0 A1 A0 1 CS W Rising C Edge R 0 Read Data Register (DR) Device Type Device Instruction DR/Bank Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge Write Data Register (DR) HIGH-VOLTAGE WRITE CYCLE FN8174.3 June 23, 2011 CS Falling Edge 0 Device Type Identifier CS Rising 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier 0 1 0 1 Device Addresses Instruction Opcode DR/Bank Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 0 A1 A0 1 1 1 0 12 X9271 Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 6, 7) Device Type Device CS Identifier Addresses Falling Edge 0 1 0 1 0 0 A1 A0 Instruction Opcode DR/Bank Addresses 0 0 CS Rising Edge 1 1 0 1 RB RA Increment/Decrement Wiper Counter Register (WCR) (Notes 6, 7, 8, 9, 10) Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 00 A1 A0 Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) . . . . CS Rising I/D I/D Edge 0 0 1 0 X X 0 0 I/D I/D Read Status Register (SR) (Note 6) Device Type CS Identifier Falling Edge 0 1 0 1 NOTES: 6. “A1 ~ A0”: stands for the device addresses sent by the master. 7. WCRx refers to wiper position data in the Wiper Counter Register. 8. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high). 9. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high). 10. “X:”: Don’t Care. Device Addresses 00 A1 A0 Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) WIP 010100010000000 CS Rising Edge 13 FN8174.3 June 23, 2011 X9271 ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature.......................... -65°C to +150°C Voltage on SCK, any address input, with respect to VSS ................................. -1V to +7V ΔV = |(VH - VL)|..................................................... 5.5V Lead temperature (soldering, 10 seconds) ........ 300°C IW (10 seconds).................................................. ±6mA Pb-Free Reflow Profile .......................... see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min. 0°C -40°C Max. +70°C +85°C Device X9271 X9271-2.7 Supply Voltage (VCC) Limits (Note 14) 5V ± 10% 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Limits Symbol RTOTAL RTOTAL Parameter End to End Resistance End to End Resistance End to End Resistance Tolerance Power Rating Min. (Note 18) Typ. 100 50 Max. (Note 18) Units kΩ kΩ T version U version Test Conditions ±20 50 ±3 300 150 VSS -120 0.4 ±1 ±0.2 ±300 20 10/10/25 VCC % mW mA W W V dBV/√Hz % MI (Note 13) MI (Note 13) ppm/°C ppm/°C pF See macro model Rw(n)(actual) - Rw(n)(expected) (Note 15) Rw(n + 1) - [Rw(n) + MI] (Note 15) IW = ± 3mA @ VCC = 3V IW = ± 3mA @ VCC = 5V VSS = 0V Ref: 1V +25°C, each pot IW RW RW VTERM Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (Note 11) Relative Linearity (Note 12) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW NOTES: Potentiometer Capacitance 11. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 12. Relative linearity is used to determine actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 13. MI = RTOT / 255 or (RH - RL) / 255, single pot. 14. During power-up, VCC > VH, VL, and VW. 15. n = 0, 1, 2, …,255; m =0, 1, 2, …., 254. 14 FN8174.3 June 23, 2011 X9271 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH Parameter VCC Supply Current (Active) VCC Supply Current (Nonvolatile Write) VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Min. Max. (Note 18) Typ. (Note 18) Units 400 1 5 3 10 10 VCC x 0.7 -1 VCC - 0.8 VCC - 0.4 VCC + 1 VCC x 0.3 0.4 μA mA μA μA μA V V V V V IOL = 3mA Test Conditions fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC IOH = -1mA, VCC ≥ +3V IOH = -0.4mA, VCC ≤ +3V ENDURANCE AND DATA RETENTION Parameter Minimum Endurance Data Retention Min. (Note 18) 100,000 100 Units Data changes per bit per register Years CAPACITANCE Symbol CIN/OUT (Note 16) COUT (Note 16) CIN (Note 16) Test Input / Output Capacitance (SI) Output Capacitance (SO) Input Capacitance (A0, CS, WP, HOLD, and SCK) Max. (Note 18) 8 8 6 Units pF pF pF Test Conditions VOUT = 0V VOUT = 0V VIN = 0V POWER-UP TIMING Symbol tr VCC (Note 16) tPUR (Note 17) tPUW (Note 17) Parameter VCC Power-up Rate Power-up to Initiation of Read Operation Power-up to Initiation of Write Operation Min. (Note 18) 0.2 Max. (Note 18) 50 1 50 Units V/ms ms ms A.C. TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level NOTES: 16. This parameter is not 100% tested. 17. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and are not 100% tested. 18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 15 FN8174.3 June 23, 2011 X9271 EQUIVALENT A.C. LOAD CIRCUIT 5V 1462 Ω SO pin 2714 Ω 100pF SO pin 1217 Ω 100pF 10pF RW 3V 1382 Ω RH CL CW 25pF CL 10pF SPICE Macromodel RTOTAL RL AC TIMING Symbol fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI Clock Frequency SSI/SPI Clock Cycle Time SSI/SPI Clock High Time SSI/SPI Clock Low Time Lead Time Lag Time SI, SCK, HOLD and CS Input Setup Time SI, SCK, HOLD and CS Input Hold Time SI, SCK, HOLD and CS Input Rise Time SI, SCK, HOLD and CS Input Fall Time SO Output Disable Time SO Output Valid Time SO Output Hold Time SO Output Rise Time SO Output Fall Time HOLD Time HOLD Setup Time HOLD Hold Time HOLD Low to Output in High Z HOLD High to Output in Low Z Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs CS Deselect Time WP, A0 Setup Time WP, A0 Hold Time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200 Parameter Min. Max. 2.5 Units MHz ns ns ns ns ns ns ns μs μs ns ns ns ns ns ns ns ns ns ns ns μs ns ns 16 FN8174.3 June 23, 2011 X9271 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage Write Cycle Time (Store Instructions) Typ. 5 Max. 10 Units ms XDCP TIMING Symbol tWRPO tWRL Parameter Wiper Response Time After Third (Last) Power Supply is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Min. 5 5 Max. 10 10 Units μs μs SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 17 FN8174.3 June 23, 2011 X9271 TIMING DIAGRAMS Input Timing tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG tFI LSB tRI SO High Impedance Output Timing CS SCK tV SO MSB tHO ... ... LSB tDIS SI ADDR Hold Timing CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ... 18 FN8174.3 June 23, 2011 X9271 XDCP Timing (for All Load Instructions) CS SCK ... MSB ... tWRL LSB SI VWx SO High Impedance Write Protect and Device Address Pins Timing CS WP A0 A1 tWPASU (Any Instruction) tWPAH 19 FN8174.3 June 23, 2011 X9271 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers VR +VR RW I 3-terminal Potentiometer; Variable Voltage Divider 2-terminal Variable Resistor; Variable Current Application Circuits Noninverting Amplifier VS + – VO VIN 317 R1 R2 R1 Iadj R2 VO (REG) Voltage Regulator VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 VS 100kΩ – + TL072 10kΩ 10kΩ +12V 10kΩ -12V VO R2 Comparator with Hysterisis VS – + VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 20 FN8174.3 June 23, 2011 X9271 Application Circuits (continued) Attenuator C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 R2 – + VO VS R R2 + – VO Filter V O = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + C1 VO VS R2 + – V O = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C – + R2 R1 – + } RA } RB Frequency ∝ R1, R2, C Amplitude ∝ RA, RB All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8174.3 June 23, 2011 X9271 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 5.00 ±0.10 14 8 SEE DETAIL "X" 3 6.40 4.40 ±0.10 2 3 PIN #1 I.D. MARK 0.20 C B A 1 0.65 TOP VIEW 7 B 0.09-0.20 END VIEW 1.00 REF H C SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 SIDE VIEW CBA 1.20 MAX 0.05 0.90 +0.15/-0.10 GAUGE PLANE 0.05 MIN 0.15 MAX DETAIL "X" 0°-8° 0.60 ±0.15 0.25 5 (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN 22 FN8174.3 June 23, 2011