X9315

® X9315 Low Noise, Low Power, 32 Taps Data Sheet December 21, 2009 FN8179.2 Digitally Controlled Potentiometer (XDCP™) The Intersil X9315 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: • Control • Parameter Adjustments • Signal Processing Features • Solid-state potentiometer • 3-wire serial interface • 32 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 31 resistive elements - Temperature compensated - End to end resistance range ± 20% - Terminal voltage, 0 to VCC • Low power CMOS - VCC = 2.7V or 5V - Active current, 80/400µA max. - Standby current, 5µA max. • High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years • RTOTAL values = 10kΩ, 50kΩ, 100kΩ • Packages - 8 Ld SOIC, MSOP and PDIP • Pb-free available (RoHS compliant) Block Diagram U/D INC CS RH/VH Control and Memory RW/VW RL/VL Store and Recall Control Circuitry 5-Bit Nonvolatile Memory 5-Bit Up/Down Counter 31 30 29 28 One of Thirty Two Decoder 2 VSS (Ground) General VCC VSS 1 0 RL/VL RW/VW Detailed RH/VH VCC (Supply Voltage) Up/Down (U/D) Increment (INC) Device Select (CS) Transfer Gates Resistor Array 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9315 Ordering Information PART NUMBER X9315WMZ (Note 2) X9315WMZT1 (Notes 1, 2) X9315WMIT2 (Note 1) X9315WMIZ (Note 2) X9315WMIZT1 (Notes 1, 2) X9315WP X9315WST1 (Note 1) X9315WSZ (Note 2) X9315WSZT1 (Notes 1, 2) X9315WSI X9315WSIT1 (Note 1) X9315WSIZ (Note 2) X9315WSIZT1 (Notes 1, 2) X9315UMZ (Note 2) X9315UMZT1 (Notes 1, 2) X9315UMI X9315UMIT1 (Notes 1, 2) X9315UMIZ (Note 2) X9315UMIZT1 (Notes 1, 2) X9315UST2 (Note 1) X9315USZ (Note 2) X9315USZT1 (Notes 1, 2) X9315USIZ (Note 2) X9315USIZT1 (Notes 1, 2) X9315TMZ (Note 2) X9315TMZT1 (Notes 1, 2) X9315TMIZ (Note 2) X9315TMIZT1 (Notes 1, 2) X9315TSZ (Note 2) X9315TSZT1 (Notes 1, 2) X9315TSIZ (Note 2) X9315TSIZT1 (Notes 1, 2) X9315WMZ-2.7 (Note 2) X9315WMZ-2.7T1 (Notes 1, 2) X9315WMI-2.7T2 (Note 1) X9315WMIZ-2.7 (Note 2) X9315WMIZ-2.7T1 (Notes 1, 2) X9315WS-2.7 PART MARKING DDT DDT AAX AKW AKW X9315WP X9315W X9315W Z X9315W Z X9315W I X9315W I X9315W ZI X9315W ZI DDS DDS AEB AEB DDR DDR X9315U X9315U Z X9315U Z X9315U ZI X9315U ZI DDN DDN DDL DDL X9315T Z X9315T Z X9315T ZI X9315T ZI AOI AOI AAV AKX AKX X9315W F 2.7 to 5.5 10 100 50 VCC LIMITS (V) 5 ±10% RTOTAL (kΩ) 10 TEMP RANGE (°C) 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 PACKAGE PKG. DWG. # 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) MDP0031 M8.15E M8.15 M8.15 M8.15E M8.15E M8.15 M8.15 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP 8 Ld MSOP M8.118 M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) M8.15E M8.15 M8.15 M8.15 M8.15 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) M8.15 M8.15 M8.15 M8.15 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld SOIC M8.15E 2 FN8179.2 December 21, 2009 X9315 Ordering Information (Continued) PART NUMBER X9315WS-2.7T1 (Note 1) X9315WSZ-2.7 (Note 2) X9315WSZ-2.7T1 (Notes 1, 2) X9315WSI-2.7T1 (Note 1) X9315WSIZ-2.7 (Note 2) X9315WSIZ-2.7T1 (Notes 1, 2) X9315UMZ-2.7 (Note 2) X9315UMZ-2.7T1 (Notes 1, 2) X9315UMIZ-2.7 (Note 2) X9315UMIZ-2.7T1 (Notes 1, 2) X9315US-2.7T2 (Note 1) X9315USZ-2.7 (Note 2) X9315USZ-2.7T1 (Notes 1, 2) X9315USI-2.7 X9315USIZ-2.7 (Note 2) X9315USIZ-2.7T1 (Notes 1, 2) X9315TMZ-2.7 (Note 2) X9315TMZ-2.7T1 (Notes 1, 2) X9315TMI-2.7T1 (Note 1) X9315TMIZ-2.7 (Note 2) X9315TMIZ-2.7T1 (Notes 1, 2) X9315TSZ-2.7 (Note 2) X9315TSZ-2.7T1 (Notes 1, 2) X9315TSIZ-2.7 (Note 2) X9315TSIZ-2.7T1 (Notes 1, 2) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. PART MARKING X9315W F X9315W ZF X9315W ZF X9315W G X9315W ZG X9315W ZG AKU AKU AJG AJG X9315U F X9315U ZF X9315U ZF X9315U G X9315U ZG X9315U ZG DDP DDP ADY DDM DDM X9315T ZF X9315T ZF X9315T ZG X9315T ZG 100 50 VCC LIMITS (V) 2.7 to 5.5 RTOTAL (kΩ) 10 TEMP RANGE (°C) 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # M8.15E M8.15 M8.15 M8.15E M8.15 M8.15 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) M8.15E M8.15 M8.15 M8.15E M8.15 M8.15 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld MSOP (Pb-free) M8.118 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) M8.15 M8.15 M8.15 M8.15 3 FN8179.2 December 21, 2009 X9315 Pin Configuration X9315 (8 LD MSOP, SOIC, PDIP) TOP VIEW INC U/D RH/VH VSS 1 2 X9315 3 4 6 5 8 7 VCC CS RL/VL RW/VW Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9315 will be placed in the low power standby mode until the device is selected once again. Principles of Operation There are three sections of the X9315: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. Pin Names SYMBOL RH/VH RW/VW RL/VL VSS VCC U/D INC CS DESCRIPTION High terminal Wiper terminal Low terminal Ground Supply voltage Up/Down control input Increment control input Chip Select control input Pin Description RH/VH and RL/VL The high (RH/VH) and low (RL/VL) terminals of the X9315 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RL/VL and RH/VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input, and not the voltage potential on the terminal. RW/VW RW/Vw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 200Ω at VCC = 5V. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty two wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9315, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until FN8179.2 December 21, 2009 Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 4 X9315 changed by the system or until a power-up/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Power-up and Down Requirements There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is always in effect. Mode Selection CS L L H H X L L L INC U/D H L X X X H L Wiper up Wiper down Store wiper position to nonvolatile memory Standby No store, return to standby Wiper Up (not recommended) Wiper Down (not recommended) MODE 5 FN8179.2 December 21, 2009 X9315 Absolute Maximum Ratings Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on CS, INC, U/D, VH, VL and VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V ΔV = |VH–VL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5mA Thermal Information Thermal Resistance (Typical, Notes 3, 4) θJA (°C/W) θJC (°C/W) 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . 105 68 8 Ld MSOP. . . . . . . . . . . . . . . . . . . . . . 154 58 8 Ld PDIP. . . . . . . . . . . . . . . . . . . . . . . 85 57 Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VCC) (Note 8) Limits X9315. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10% X9315-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Max Wiper Current, IW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.75mA Max Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For θJC, the “case temp” location is taken at the package top center. Potentiometer Characteristics (Over recommended operating conditions unless otherwise stated.) LIMITS SYMBOL PARAMETER End to end resistance tolerance TEST CONDITIONS/NOTES MIN TYP MAX (Note 9) (Note 8) (Note 9) -20 0 0 +20 VCC VCC 200 400 -120 3 400 1000 UNIT % V V Ω Ω dBV % VVH VVL RW RW VH terminal voltage VL terminal voltage Wiper resistance Wiper resistance Noise Resolution Absolute linearity (Note 5) Relative linearity (Note 6) RTOTAL temperature coefficient Ratiometric temperature coefficient Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI] IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 5V IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 2.7V Ref: 1kHz ±1 ±0.2 ±300 ±20 MI (Note 7) MI (Note 7) ppm/°C ppm/°C pF CH/CL/CW NOTES: Potentiometer capacitances See circuit #3 on page 7 10/10/25 5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml Maximum. 6. Relative linearity is a measure of the error in step size between taps = RW(n+1) - [Rw(n) + Ml] = ±0.2 Ml. 7. 1 Ml = Minimum Increment = RTOT/31. 8. Typical values are for TA = +25°C and nominal supply voltage. 9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 6 FN8179.2 December 21, 2009 X9315 DC Electrical Specifications (Over recommended operating conditions unless otherwise specified. LIMITS SYMBOL VCC PARAMETER Supply Voltage X9315 X9315-2.7 ICC1 ICC2 ISB ILI VIH VIL CIN VCC active current (Increment) VCC active current (Store) (EEPROM Store) Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH voltage CS, INC, U/D input LOW voltage CS, INC, U/D input capacitance VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCYC CS = VIH, U/D = VIL or VIH and INC = VIH @ max. tWR CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS to VCC -10 VCC x 0.7 -0.5 10 TEST CONDITIONS MIN (Note 9) 4.5 2.7 TYP (Note 8) MAX (Note 9) 5.5 5.5 80 400 5 +10 VCC + 0.5 VCC x 0.1 UNIT V V µA µA µA µA V V pF Endurance and Data Retention PARAMETER Minimum endurance Data retention MIN 100,000 100 UNIT Data changes per bit Years Test Circuit #1 VH/RH Test Circuit #2 VH/RH Test Point Circuit #3 SPICE Macro Model RTOTAL RH CH CW 25pF 10pF RW CL 10pF RL VS Test Point VW/RW VL/RL V L /RL VL VW VW/RW Force Current AC Conditions of Test Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V (Over recommended operating conditions unless otherwise specified) LIMITS SYMBOL tCl tlD tDI tlL tlH CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period PARAMETER MIN (Note 9) 100 100 2.9 1 1 TYP (Note 8) MAX (Note 9) UNIT ns ns µs µs µs AC Electrical Specifications 7 FN8179.2 December 21, 2009 X9315 AC Electrical Specifications (Over recommended operating conditions unless otherwise specified) (Continued) LIMITS SYMBOL tlC tCPH tCPH tIW tCYC tR, tF (Note 10) tPU (Note 10) tR VCC (Note 10) tWR NOTE: 10. This parameter is not 100% tested. PARAMETER INC Inactive to CS inactive CS Deselect time (NO STORE) CS Deselect time (STORE) INC to Vw change INC cycle time INC input rise and fall time Power-up to wiper stable VCC power-up rate Store cycle 0.2 5 4 500 5 50 10 MIN (Note 9) 1 100 10 1 5 TYP (Note 8) MAX (Note 9) UNIT µs ns ms µs µs µs µs V/ms ms AC Timing CS tCYC tCI INC tID U/D tIW VW NOTE: 11. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position. MI (Note 9) DI tIL tIH tIC (Store) tCPH 90% 90% 10% tF tR 8 FN8179.2 December 21, 2009 X9315 Symbol Table WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance Performance Characteristics (Typical) Typical Noise 0 -10 -20 -30 -40 Noise (dB) -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Frequency (kHz) 9 FN8179.2 December 21, 2009 X9315 Typical Rtotal vs. Temperature 10000 9800 9600 9400 Rtotal 9200 9000 8800 8600 8400 8200 8000 -55 -45 -35 -25 -15 -5 5 15 25 Temperature 35 45 55 65 75 85 95 105 115 125 C° Typical Total Resistance Temperature Coefficient 0 -50 -100 -150 PPM -200 -250 -300 -350 -55 -45 -35 -25 -15 -5 5 15 Temperature 25 35 45 55 65 75 85 95 105 115 125 °C Typical Wiper Resistance 800 700 600 500 Rw (Ω) 400 300 200 100 0 0 2 4 6 8 10 12 14 16 Tap 18 20 22 24 26 28 30 32 VCC = 2.7V 10 FN8179.2 December 21, 2009 X9315 Typical Absolute% Error per Tap Position 40.0% 30.0% Absolute% Error 20.0% 10.0% 0.0% -10.0% -20.0% -30.0% -40.0% 0 3 6 9 12 15 18 21 24 27 30 Tap Typical Relative% Error per Tap Position 20.0% 15.0% Relative% Error 10.0% 5.0% 0.0% -5.0% -10.0% -15.0% -20.0% 0 3 6 9 12 15 18 21 24 27 30 Tap Applications Information Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. 11 FN8179.2 December 21, 2009 X9315 Basic Configurations of Electronic Potentiometers VR VH VW/RW VR VL I Three terminal potentiometer; variable voltage divider Two terminal variable resistor; variable current Basic Circuits Buffered Reference Voltage R1 +V VW + – -5V VOUT = VW/RW (a) (b) +5V VREF OP-07 VOUT +V R1 RW/VW RW/VW X Cascading Techniques +V +V Noninverting Amplifier +5V VS + – -5V R2 LM308A VO VO = (1 + R2/R1)VS Voltage Regulator Comparator with Hysteresis VIN 317 R1 Iadj R2 VO (REG) VS LT311A – + VO VO (REG) = 1.25V (1 + R2/R1) + Iadj R2 VUL = {R1/(R1 + R2)} VO(max) VLL = {R1/(R1 + R2)} VO(min) (for additional circuits see AN115) } R1 } R2 12 FN8179.2 December 21, 2009 X9315 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 -BE INCHES SYMBOL A ABC MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03 MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028 INDEX AREA 12 TOP VIEW 0.20 (0.008) A1 A2 4X θ 0.25 (0.010) GAUGE PLANE SEATING PLANE -C- R1 R b c D E1 A A2 4X θ L L1 e E L L1 N R 0.026 BSC 0.65 BSC A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE 0.037 REF 0.95 REF C a C L E1 C R1 0 SIDE VIEW 15o 6o α -B- 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 13 FN8179.2 December 21, 2009 X9315 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 1.27 0.43 ± 0.076 0.25 M C A B 4° ± 4° SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 0.175 ± 0.075 GAUGE PLANE C SEATING PLANE 0.10 C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012. 2. (5.40) 3. 4. TYPICAL RECOMMENDED LAND PATTERN 14 FN8179.2 December 21, 2009 X9315 Plastic Dual-In-Line Packages (PDIP) D E N PIN #1 INDEX SEATING PLANE L e b A2 A c E1 A1 NOTE 5 eA eB 1 2 b2 N/2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN ±0.005 ±0.002 +0.010/-0.015 +0.004/-0.002 ±0.010 +0.015/-0.010 ±0.005 Basic Basic ±0.025 ±0.010 Reference Rev. B 2/99 2 1 NOTES 15 FN8179.2 December 21, 2009 X9315 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN8179.2 December 21, 2009