DATASHEET
X9400
FN8189
Rev 4.00
September 2, 2015
Low Noise/Low Power/SPI Bus Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
DESCRIPTION
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40 typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
• System VCC: 2.7V to 5.5V operation
• Analog V+/V–: -5V to +5V
• 10k, 2.5k end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
Pot 0
VSS
V+
V-
R0 R1
HOLD
R2 R3
CS
SCK
SO
SI
A0
A1
Interface
and
Control
Circuitry
WP
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW0/RW0
VW2/RW2
VW1/RW1
VW3/RW3
8
Data
R0 R1
R2 R3
FN8189 Rev 4.00
September 2, 2015
VH0/RH0
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RL3
Page 1 of 20
X9400
Ordering Information
PART NUMBER
PART
MARKING
X9400WS24ZT1 (Note) (No longer available,
X9400WS Z
recommended replacement: X9400WS24IZT1)
VCC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(k)
TEMP.
RANGE
(°C)
5 ±10%
10
0 to +70
PACKAGE
PKG.
DWG. #
24 Ld SOIC (300 mil)
M24.3
(Pb-free) Tape and Reel
X9400WS24IZ* (Note)
X9400WS ZI
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
X9400WV24IZ* (Note)
X9400WV ZI
-40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
X9400WV24Z* (Note) (No longer available,
X9400WV Z
recommended replacement: X9400WS24IZT1)
X9400WS24IZ-2.7* (Note)
X9400WS ZG 2.7 to 5.5
X9400WV24IZ-2.7* (Note) (No longer available, X9400WV ZG
recommended replacement: X9400WS24IZT1)
X9400WV24Z-2.7* (Note) (No longer available, X9400WV ZF
recommended replacement: X9400WS24IZT1)
0 to +70
24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
M24.3
-40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
0 to +70
24 Ld TSSOP (4.4mm)
(Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8189 Rev 4.00
September 2, 2015
Page 2 of 20
X9400
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Device Address (A0 - A1)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9400. A maximum of 4 devices may occupy the SPI
serial bus.
Serial Clock (SCK)
Potentiometer Pins
The SCK input is used to clock data into and out of the
X9400.
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3)
Serial Input
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9400, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
The VH/RH and VL/RL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
VW/RW (VW0/RW0 - VW3/RW3)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
SOIC
TSSOP
V+
VCC
1
24
VL0/RL0
2
23
VL3/RL3
VH0/RH0
3
22
VH3/RH3
21
VW3/RW3
VW0/RW0
CS
4
5
WP
6
SI
7
A1
8
X9400
WP
A1
2
23
CS
VL1/RL1
VH1/RH1
3
22
VW0/RW0
4
21
VH0/RH0
5
20
VL0/RL0
6
19
VCC
18
V+
A0
19
SO
VSS
18
HOLD
17
SCK
VH2/RH2
VL2/RL2
SCK
VL1/RL1
9
16
10
15
VH2/RH2
VW1/RW1
11
14
VW2/RW2
12
13
FN8189 Rev 4.00
September 2, 2015
24
20
VH1/RH1
SS
1
VW1/RW1
VL2/RL2
V
SI
V-
X9400
V-
7
VW2/RW2
8
17
VL3/RL3
9
16
VH3/RH3
10
15
VW3/RW3
11
14
A0
12
13
SO
HOLD
Page 3 of 20
X9400
Wiper Counter Register (WCR)
PIN NAMES
Symbol
Description
SCK
Serial Clock
SI, SO
Serial Data
A0 - A1
Device Address
VH0/RH0 - VH3/RH3,
VL0/RL0 - VL3/RL3
Potentiometer Pins (terminal
equivalent)
VW0/RW0 - VW1/RW1
Potentiometer Pins (wiper
equivalent)
WP
Hardware Write Protection
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
DEVICE DESCRIPTION
The X9400 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The X9400 contains four Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent to
a serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register or global XFR data register instructions
(parallel load); it can be modified one step at a time by
the increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9400 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
Array Description
Data Register Detail
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (VH/RH and VL/RL inputs).
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
FN8189 Rev 4.00
September 2, 2015
Page 4 of 20
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
Serial
Bus
Input
From Interface
Circuitry
Register 0
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
If WCR = 00[H] then VW/RW = VL/RL
If WCR = 3F[H] then VW/RW = VH/RH
C
o
u
n
t
e
r
Register 1
8
Register 2
VH/RH
UP/DN
Modified SCL
D
e
c
o
d
e
INC/DEC
Logic
UP/DN
VL/RL
CLK
VW/RW
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
Figure 2. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
INSTRUCTIONS
Identification (ID) Byte
Instruction Byte
The first byte sent to the X9400 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9400 this is fixed as
0101[B] (refer to Figure 2).
The next byte sent to the X9400 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 3.
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A0 - A1 input pins. The X9400
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9400 to successfully continue the
command sequence. The A0 - A1 inputs can be actively
driven by CMOS input signals or tied to VCC or VSS.
The remaining two bits in the slave byte must be set to 0.
FN8189 Rev 4.00
September 2, 2015
Page 5 of 20
X9400
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
Pot Select
The four high order bits of the instruction byte specify the
operation. The next two bits (R1 and R0) select one of
the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P0) selects which one of the four potentiometers
is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register —This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
– Global XFR Data Register to Wiper Counter Register —
This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Register —
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are:
– Read Wiper Counter Register—read the current wiper
position of the selected pot,
– Write Wiper Counter Register—change current wiper
position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the selected
data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle is
in progress.
The sequence of these operations is shown in Figure 5
and Figure 6.
The final command is Increment/Decrement. It is different
from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
capability to the host. For each SCK clock pulse (tHIGH)
while SI is HIGH, the selected wiper will move one
resistor segment towards the VH/RH terminal. Similarly,
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the VL/RL
terminal. A detailed illustration of the sequence and timing
for this operation are shown in Figure 7 and Figure 8.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by tWRL. A transfer from the
WCR (current wiper position), to a data register is a write
to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated registers; or
it may occur globally, where the transfer occurs between
all potentiometers and one associated register.
FN8189 Rev 4.00
September 2, 2015
Page 6 of 20
X9400
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCK
SI
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCK
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
FN8189 Rev 4.00
September 2, 2015
0
1
0
0
A1 A0
I3
I2
I1
I0
0
0
P1
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
Page 7 of 20
X9400
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
Read Wiper Counter Register
I3
1
I2
0
Instruction Set
I1 I0 R1 R0 P1
0
1
0
0
P1
Write Wiper Counter Register
1
0
1
0
Read Data Register
1
0
1
1
R1 R0
P1
Write Data Register
1
1
0
0
R1 R0
P1
XFR Data Register to Wiper
Counter Register
1
1
0
1
R1 R0
P1
XFR Wiper Counter Register
to Data Register
1
1
1
0
R1 R0
P1
Global XFR Data Register to
Wiper Counter Register
0
0
0
1
R1 R0
0
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R1 R0
0
Increment/Decrement Wiper
Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
P1
0
1
0
1
0
0
0
Instruction
FN8189 Rev 4.00
September 2, 2015
0
0
P1
P0
Operation
P0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
P0 Write new value to the Wiper Counter Register
pointed to by P1 - P0
P0 Read the contents of the Data Register pointed to
by P1 - P0 and R1 - R0
P0 Write new value to the Data Register pointed to by
P1 - P0 and R1 - R0
P0 Transfer the contents of the Data Register pointed to
by R1 - R0 to the Wiper Counter Register pointed to by
P1 - P0
P0 Transfer the contents of the Wiper Counter
Register pointed to by P1 - P0 to the Register
pointed to by R1 - R0
0 Transfer the contents of the Data Registers pointed
to by R1 - R0 of all four pots to their respective Wiper
Counter Register
0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1 - R0 of all four pots
P0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P1 - P0
1 Read the status of the internal write cycle, by
checking the WIP bit.
Page 8 of 20
X9400
Instruction Format
Notes: (1)
(2)
(3)
(4)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
device
instruction
identifier
addresses
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1 0 0 1
1 0
WCR
addresses
0
wiper position
(sent by X9400 on SO)
CS
Rising
W W W W W W
P P
0
0 0 P P P P P P Edge
1 0
5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
CS
Falling
Edge 0 1 0 1 0 0 A A 1
1 0
0
1
WCR
addresses
0
0
Data Byte
(sent by Host on SI)
CS
W W W W W W Rising
P P
0
0 0 P P P P P P Edge
1 0
5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P
1 0
1 0 1
Data Byte
(sent by X9400 on SO)
CS
W W W W W W Rising
P
0 0 P P P P P P Edge
0
5 4 3 2 1 0
Write Data Register (DR)
device type
device
identifier
addresses
instruction
opcode
DR and WCR
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A 1 1 0 0 R
1 0
1
R
0
P
1
P
0
Data Byte
(sent by host on SI)
CS
W W W W W W Rising
0 0 P P P P P P Edge
5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge
1 0
1 0 1 0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge
1 0
1 0 1 0
FN8189 Rev 4.00
September 2, 2015
HIGH-VOLTAGE
WRITE CYCLE
Page 9 of 20
X9400
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses (sent by master on SDA)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/ I/ . . . . I/ I/ Edge
1 0
1 0 D D
D D
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
device type
device
instruction
wiper
Data Byte
identifier
addresses
opcode
addresses
(sent by X9400 on SO)
CS
CS
Falling
Rising
W
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
FN8189 Rev 4.00
September 2, 2015
Page 10 of 20
X9400
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65C to +135C
Storage temperature ......................... -65C to +150C
Voltage on SCK, SCL or any address
input with respect to VSS ......................... -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH ....................................................................V+
Any VL ......................................................................VLead temperature (soldering, 10 seconds) ........ 300C
IW (10 seconds)................................................±12mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0C
-40C
Max.
+70C
+85C
Device
X9400
X9400-2.7
Supply Voltage (VCC) Limits
5V 10%
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Max.
Unit
End to end resistance
±20
%
Power rating
50
mW
IW
Wiper current
±6
mA
RW
Wiper resistance
150
250
Wiper Current = 1mA,
VCC = 3V
40
100
Wiper Current = 1mA,
VCC = 5V
V
RTOTAL
Vv+
VvVTERM
Parameter
Voltage on V+ Pin
Voltage on V- Pin
Min.
Typ.
X9400
+4.5
+5.5
X9400-2.7
+2.7
+5.5
X9400
-5.5
-4.5
X9400-2.7
-5.5
-2.7
V-
V+
Voltage on any VH/RH or VL/RL Pin
Noise
Resolution
Absolute linearity (1)
Relative linearity (2)
Temperature coefficient of RTOTAL
V
dBV
1.6
%
-0.2
+1
MI(3)
+0.2
MI(3)
300
Ratiometric temp. coefficient
Potentiometer capacitances
10/10/25
IAL
RH, RL, RW leakage current
0.1
Ref: 1kHz
Rw(n)(actual) - Rw(n)(expected)
Rw(n + 1) - [Rw(n) + MI]
ppm/C
±20
CH/CL/CW
25C, each pot
V
-120
-1
Test Conditions
10
ppm/°C
pF
See Spice Macromodel
µA
VIN = VSS to VCC. Device is in
stand-by mode.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
FN8189 Rev 4.00
September 2, 2015
Page 11 of 20
X9400
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC1
VCC supply current (Active)
ICC2
VCC supply current (Nonvolatile
Write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
1
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
CAPACITANCE
Symbol
COUT
(4)
CIN(4)
Test
Max.
Unit
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, and SCK)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tPUR
(5)
tPUW(5)
tR VCC(4)
Parameter
Max.
Unit
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
50
V/msec
VCC Power-up ramp
POWER-UP REQUIREMENTS (Power-up sequencing
can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First
VCC, then the potentiometer pins, RH, RL, and RW.
Voltage should not be applied to the potentiometer pins
before V+ or V- is applied. The VCC ramp rate specification should be met, and any glitches or slope changes
in the VCC line should be held to > R2
Function Generator
C
R2
–
+
R1
–
} RA
+
} RB
frequency R1, R2, C
amplitude RA, RB
FN8189 Rev 4.00
September 2, 2015
Page 17 of 20
X9400
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
September 2, 2015
FN8189.4
Updated Ordering Information Table on page 2.
Added Revision History and About Intersil sections.
Updated POD M24.3 from rev 1 to rev 2. Changes since rev 1:
Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing.
Added Land Pattern.
Updated POD MDP004 from rev E to rev F. Changes since rev E:
Added dimensions (MILLIMETERS) to table column heading.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
FN8189 Rev 4.00
September 2, 2015
Page 18 of 20
X9400
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291) 10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1
2
3
TOP VIEW
1.27 (0.050)
0.40 (0.016)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
15.60 (0.614)
15.20 (0.598)
0.75 (0.029)
x 45°
0.25 (0.010)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
8°
0°
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “B”
SIDE VIEW “A”
1.981 (0.078)
9.373 (0.369)
1.27 (0.050)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
FN8189 Rev 4.00
September 2, 2015
Page 19 of 20
X9400
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
MILLIMETERS
(N/2)+1
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN8189 Rev 4.00
September 2, 2015
Page 20 of 20
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