IR2010

Data Sheet No. PD60195-D IR2010(S) & (PbF) Features • • • • • • • • HIGH AND LOW SIDE DRIVER Product Summary VOFFSET IO+/VOUT ton/off Delay Matching 200V max. 3.0A / 3.0A typ. 10 - 20V 95 & 65 ns typ. 15 ns max. • Floating channel designed for bootstrap operation Fully operational to 200V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Shut down input turns off both channels Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE Applications • Audio Class D amplifiers • High power DC-DC SMPS converters • Other high frequency applications Packages Description The IR2010 is a high power, high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels, ideal for Audio Class D and DC-DC converter applications. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 200 volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. 14-Lead PDIP 16-Lead SOIC Typical Connection HO VDD HIN SD LIN V SS VCC VDD HIN SD LIN VSS VCC COM LO VB VS 200V TO LOAD (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR2010(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN & SD) Allowable offset supply voltage transient (figure 2) Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (14 lead DIP) (16 lead SOIC) (14 lead DIP) (16 lead SOIC) Min. -0.3 V B - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 — — — — — — -55 — Max. 225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 150 150 300 Units V V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in figures 24 and 25. Symbol VB VS VHO VCC VLO VDD VSS VIN TA Definition High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic supply voltage Logic supply offset voltage Logic input voltage (HIN, LIN & SD) Ambient temperature Min. VS + 10 Note 1 VS 10 0 VSS + 3 -5 (Note 2) VSS -40 Max. VS + 20 200 VB 20 VCC VSS + 20 5 VDD 125 Units V °C Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS. Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD. (Please refer to the Design Tip DT97-3 for more details). 2 www.irf.com IR2010(S) & (PbF) Dynamic Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25°C and VSS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Symbol ton toff tsd tr tf MT Definition Turn-on propagation delay Turn-off propagation delay Shutdown propagation delay Turn-on rise time Turn-off fall time Delay matching, HS & LS turn-on/off Figure Min. Typ. Max. Units Test Conditions 7 8 9 10 11 6 50 30 35 — — — 95 65 70 10 15 — 135 105 105 20 25 15 VS = 0V VS = 200V VS = 200V ns Static Electrical Characteristics VBIAS (VCC, VBS, VDD) = 15V, TA = 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH VIL VIH VIL VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- Definition Logic “1” input voltage Logic “0” input voltage Logic “1” input voltage Logic “0” input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Quiescent VDD supply current Logic “1” input bias current Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current Figure Min. Typ. Max. Units Test Conditions 12 13 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 9.5 — 2 — — — — — — — — — 7.5 7.0 7.5 7.0 2.5 2.5 — — — — — — — 70 100 1 20 — 8.6 8.2 8.6 8.2 3.0 3.0 — 6.0 — 1 1.0 0.1 50 210 230 5 40 1.0 9.7 9.4 9.7 9.4 — — A VO = 0V, VIN = VDD PW ≤ 10 µs VO = 15V, VIN = 0V PW ≤ 10 µs V µA V VDD = 15V VDD = 3.3V IO = 0A IO = 0A VB=VS = 200V VIN = 0V or VDD VIN = 0V or VDD VIN = 0V or VDD VIN = VDD VIN = 0V www.irf.com 3 IR2010(S) & (PbF) Functional Block Diagram VB VDD UV DETECT LEVEL SHIFT CIRCUIT UV Q S R VS HO HIN VSS /COM LEVEL SHIFT SD UV DETECT VCC LIN VSS /COM LEVEL SHIFT LO DELAY VSS COM Lead Definitions Symbol Description VDD HIN SD LIN VSS VB HO VS VCC LO COM Logic supply Logic input for high side gate driver output (HO), in phase Logic input for shutdown Logic input for low side gate driver output (LO), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 14 Lead PDIP 16 Lead SOIC (Wide Body) IR2010 Part Number 4 IR2010S www.irf.com IR2010(S) & (PbF) HV =10 to 200V HIN LIN SD