IR2011SPBF

Data Sheet No.PD60217 Rev A IR2011(S) & (PbF) HIGH AND LOW SIDE DRIVER Features • • • • • • • • • Floating channel designed for bootstrap operation Product Summary VOFFSET IO+/VOUT ton/off Delay Matching 200V max. 1.0A /1.0A typ. 10 - 20V 80 & 60 ns typ. 20 ns max. Fully operational up to +200V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10V to 20V Independent low and high side channels Input logicHIN/LIN active high Undervoltage lockout for both channels 3.3V and 5V input logic compatible CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels 8-Lead SOIC is also available LEAD-FREE (PbF) Applications • Audio Class D amplifiers • High power DC-DC SMPS converters • Other high frequency applications Packages Description The IR2011 is a high power, high speed power MOSFET driver with independent high and low side referenced output channels, ideal for Audio Class D and DC-DC converter applications. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET in the high side configuration which operates up to 200 volts. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. 8-Lead SOIC IR2011S also available LEAD-FREE (PbF) 8-Lead PDIP IR2011 Typical Connection 200V HIN LIN COM 5 HIN LIN COM VS HO VB VCC 4 TO LOAD 8 LO 1 VCC (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR2011(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VIN dVs/dt PD RTHJA TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic input voltage (HIN & LIN) Allowable offset supply voltage transient (figure 2) Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8-lead DIP) (8-lead SOIC) (8-lead DIP) (8-lead SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 COM -0.3 — — — — — — -55 — Max. 250 VB + 0.3 VB + 0.3 25 VCC +0.3 VCC +0.3 50 1.0 0.625 125 200 150 150 300 Units V V/ns W °C/W °C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings are tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VIN TA Definition High side floating supply absolute voltage High side floating supply offset voltage High side floating output voltage Low side fixed supply voltage Low side output voltage Logic input voltage (HIN & LIN) Ambient temperature Min. VS + 10 Note 1 VS 10 0 COM -40 Max. VS + 20 200 VB 20 VCC 5.5 125 Units V °C Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS. 2 www.irf.com IR2011(S) & (PbF) Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000 pF, TA = 25°C unless otherwise specified. Figure 1 shows the timing definitions. Symbol ton toff tr tf DM1 DM2 Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Turn-on delay matching | ton (H) - ton (L) | Turn-off delay matching | toff (H) - toff (L) | Min. Typ. Max. Units Test Conditions — — — — — — 80 75 35 20 5 5 — — 50 35 20 20 VS = 0V VS = 200V ns Static Electrical Characteristics VBIAS (VCC, VBS) = 15V, and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH VIL VOH VOL ILK IQBS IQCC IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- Definition Logic “1” input voltage Logic “0” input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current Logic “0” input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current Min. Typ. Max. Units Test Conditions 2.2 — — — — — — — — 8.2 7.4 8.2 7.4 — — — — — — — 90 140 7.0 — 9.0 8.2 9.0 8.2 1.0 1.0 — 0.7 2.0 0.2 50 210 230 20 1.0 9.8 9.0 V 9.8 9.0 — — A VO = 0V, PW ≤ 10 µs VO = 15V, PW ≤ 10 µs µA V IO = 0A 20mA VB=VS = 200V VIN = 0V or 3.3V VIN = 0V or 3.3V VIN = 3.3V VIN = 0V VCC = 10V - 20V www.irf.com 3 IR2011(S) & (PbF) Functional Block Diagram VB HIGH VOLTAGE LEVEL SHIFT CIRCUIT UV DETECT UV Q S R VS 3V S-TRIGGER HIN LOW VOLTAGE LEVEL SHIFT BUFFER HO VCC 3V S-TRIGGER LIN LOW VOLTAGE LEVEL SHIFT UV DETECT LO DELAY COM Lead Definitions Symbol Description HIN LIN VB HO VS VCC LO COM Logic input for high side gate driver output (HO), in phase Logic input for low side gate driver output (LO), in phase High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 5 HIN 6 LIN 7 COM 8 LO VS 4 HO 3 VB 2 VCC 1 5 HIN 6 LIN 7 COM 8 LO VS 4 HO 3 VB 2 V CC 1 8-Lead PDIP 8-Lead SOIC also available LEAD-FREE (PbF) IR2011 Part Number 4 IR2011S www.irf.com IR2011(S) & (PbF) 50% 50% HIN / LIN trise 90% ton(H) 10% 90% toff(H) 10% tfall HO DM1 90% ton(L) 10% toff(L) DM2 LO Figure 1. Timing Diagram www.irf.com 5 IR2011(S) & (PbF) Turn-on Propagation Delay (ns) 400 300 200 100 Typ. Turn-on Propagation Delay (ns) 500 500 400 300 200 Typ. 100 0 10 12 14 16 18 20 Supply Voltage (V) Figure 2B. Turn-on Propagation Delay vs. Supply Voltage 0 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 2A. Turn-on Propagation Delay vs. Temperature Turn-off Propagation Delay (ns) 400 300 200 100 Typ. Turn-off Propagation Delay (ns) 500 500 400 300 200 100 0 10 12 14 16 18 20 Supply Voltage (V) Figure 3B. Turn-off Propagation Delay vs. Supply Voltage Typ. 0 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 3A. Turn-off Propagation Delay vs. Temperature 6 www.irf.com IR2011(S) & (PbF) 100 Turn-on Rise Time (ns) 80 60 M ax. 100 Turn-on Rise Time (ns) 80 60 40 20 0 M ax. Typ. 40 20 Typ. 0 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Figure 4A. Turn-on Rise Time vs. Temperature Supply Voltage (V) Figure 4B. Turn-on Rise Time vs. Supply Voltage 50 Turn-off Fall Time (ns) Turn-off Fall Time (ns) 50 40 30 Typ. M ax. 40 M ax. 30 20 10 0 -50 Typ. 20 10 0 -25 0 25 50 (oC) 75 100 125 10 12 14 16 18 20 Temperature Supply Voltage (V) Figure 5B. Turn-off Fall Time vs. Supply Voltage Figure 5A. Turn-off Fall Time vs. Temperature www.irf.com 7 IR2011(S) & (PbF) 50 Delay Matching Time (ns) Dealy Matching Time (ns) 50 40 30 M ax. 40 30 M ax. 20 10 Typ. 20 10 0 Typ. 0 -50 -25 0 25 50 o 75 100 125 10 12 14 16 18 20 Temperature ( C) Figure 6A. Turn-on Delay Matching Time vs. Temperature Supply Voltage (V) Figure 6B. Turn-on Delay Matching Time vs. Supply Voltage 50 Delay Matching Time (ns) 40 30 20 10 M ax. 50 Dealy Matching Time (ns) 40 30 M ax. 20 10 0 Typ. Typ. 0 -50 -25 0 25 50 (oC) 75 100 125 10 12 14 16 18 20 Temperature Supply Voltage (V) Figure 7B. Turn-off Delay Matching Time vs. Supply Voltage Figure 7A. Turn-off Delay Matching Time vs. Temperature 8 www.irf.com IR2011(S) & (PbF) 5 Logic "1" Input Voltage (V) Logic "1" Input Voltage (V) 4 3 Mi n. 5 4 3 Mi n. 2 1 0 -50 2 1 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Figure 8A. Logic "1" Input Voltage vs. Temperature Supply Voltage (V) Figure 8B. Logic "1" Input Voltage vs. Supply Voltage 5 Logic "0" Input Voltage (V) Logic "0" Input Voltage (V) 5 4 3 2 M ax. 4 3 2 1 M ax. 1 0 0 -50 -25 0 25 50 (oC) 75 100 125 10 12 14 16 18 20 Temperature Supply Voltage (V) Figure 9B. Logic "0" Input Voltage vs. Supply Voltage Figure 9A. Logic "0" Input Voltage vs. Temperature www.irf.com 9 IR2011(S) & (PbF) 5 High Level Output (V) High Level Output (V) 4 3 M ax. 5 4 3 M ax. 2 1 0 -50 2 1 0 -25 0 25 50 o 75 100 125 10 12 14 16 18 20 Temperature ( C) Figure 10A. High Level Output vs.Temperature Supply Voltage (V) Figure 10B. High Level Output vs. Supply Voltage 0.5 Low Level Output (V) Low Level Output (V) 0.5 0.4 0.3 0.2 M ax. 0.4 0.3 0.2 0.1 0.0 -50 M ax. 0.1 0.0 -25 0 25 50 (oC) 75 100 125 10 12 14 16 18 20 Temperature Supply Voltage (V) Figure 11B. Low Level Output vs. Supply Voltage Figure 11A. Low Level Output vs. Temperature 10 www.irf.com IR2011(S) & (PbF) Offset Supply Leakage Current (µA) Offset Supply Leakage Current (µA) 500 400 300 200 100 M ax. 500 400 300 200 100 0 50 M ax. 0 -50 -25 0 25 50 o 75 100 125 80 110 140 170 200 Temperature ( C) Figure 12A. Offset Supply Leakage Current vs. Temperature V B Boost Voltage (V) 600 V BS Supply Current (µA) 500 400 300 200 100 M ax. 600 V BS Supply Current (µA) 500 400 300 200 100 0 Typ. M ax. 0 -50 Typ. -25 0 25 50 (o 75 100 125 10 12 14 16 18 20 Temperature C) V BS Floating Supply Voltage (V) www.irf.com 11 IR2011(S) & (PbF) 600 V CC Supply Current (µA) 500 400 300 200 100 0 -50 M ax. Typ. 600 V CC Supply Current (µA) 500 400 300 200 100 Typ. M ax. -25 0 25 50 (o 75 100 125 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 14B. V CC Supply Current vs. V CC Supply Voltage Temperature C) Figure 14A. V CC Supply Current vs. Tem perature µ Logic "1" Input Bias Current ( A) 100 80 60 40 20 M ax. Typ. µ Logic "1" Input Bias Current ( A) 100 80 60 40 20 M ax. 0 -50 0 10 Typ. -25 0 25 50 75 100 125 12 14 16 18 20 Temperature (oC) Figure 15A. Logic "1" Input Bias Current vs. Tem perature Supply Voltage (V) 12 www.irf.com IR2011(S) & (PbF) µ Logic "0" Input Bias Current ( A) µ Logic "0" Input Bias Current ( A) -25 0 25 50 75 100 125 5 4 3 2 M ax. 5 4 3 2 M ax. 1 0 -50 1 0 10 12 14 16 18 20 Supply Voltage (V) Figure 16B. Logic "0" Input Bias Current vs. Supply Voltage Temperature (oC) Figure 16A. Logic "0" Input Bias Current vs. Tem perature V CC and V BS UV Threshold (+) (V) 11 10 9 8 7 -50 M ax. Typ. Mi n. V CC and V BS UV Threshold (-) (V) 12 12 11 10 9 8 Mi n. M ax. Typ. -25 0 25 50 75 100 125 7 -50 -25 0 25 50 o 75 100 125 Temperature (oC) Figure 17. VCC and VBS Undervoltage Threshold (+) vs. Temperature Temperature ( C) Figure 18. VCC and VBS Undervoltage Threshold (-) vs. Temperature www.irf.com 13 IR2011(S) & (PbF) 5 Output Source Current (A) 5 Output Source Current (A) -25 0 25 50 75 100 125 4 3 2 Typ. 4 3 2 Typ. 1 0 -50 1 0 10 12 14 16 18 20 Temperature (oC) Figure19A. Output Source Current vs. Temperature Supply Voltage (V) Figure 19B. Output Source Current vs. Supply Voltage 5 Output Sink Current (A) 4 3 2 1 0 -50 Typ. 5 Output Sink Current (A) 0 25 50 75 100 125 4 3 2 1 0 Typ. -25 10 12 14 16 18 20 Temperature (oC) Figure 20A. Output Sink Current vs. Temperature Supply Voltage (V) Figure 20B. Output Sink Current vs. Supply Voltage 14 www.irf.com IR2011(S) & (PbF) Maximum VS Negative Offset (V) 0 -3 -6 -9 -12 -15 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 21. Maximum VS Negative Offset vs. V BS Floating Supply Voltage Typ. www.irf.com 15 IR2011(S) & (PbF) Case outlines 8-Lead PDIP D A 5 B FOOTPRINT 8X 0.72 [.028] 01-6014 01-3003 01 (MS-001AB) INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 DIM A b c D A1 .0040 6 E 8 7 6 5 H 0.25 [.010] A E 6.46 [.255] 1 2 3 4 e e1 H K L 8X 1.78 [.070] .050 BASIC .025 BASIC .2284 .0099 .016 0° .2440 .0196 .050 8° 1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0° 6.20 0.50 1.27 8° 6X e e1 3X 1.27 [.050] y A C 0.10 [.004] y K x 45° 8X b 0.25 [.010] NOTES: A1 CAB 8X L 7 8X c 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE C ONFORMS TO JEDEC OUTLINE MS-012AA. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 8-Lead SOIC 16 01-6027 01-0021 11 (MS-012AA) www.irf.com IR2011(S) & (PbF) LEADFREE PART MARKING INFORMATION Part number IRxxxxxx YWW? ?XXXX Lot Code (Prod mode - 4 digit SPN code) IR logo Date code Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION Basic Part (Non-Lead Free) 8-Lead PDIP IR2011 order IR2011 8-Lead SOIC IR2011S order IR2011S Leadfree Part 8-Lead PDIP IR2011 Not available 8-Lead SOIC IR2011S order IR2011SPbF This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web Site http://www.irf.com/. Data and specifications subject to change without notice WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 5/25/2004 www.irf.com 17