IR2157

ADVANCED INFORMATION Data Sheet No. PD60108B IR2157 FULLY INTEGRATED BALLAST CONTROL IC Features • Programmable preheat time & frequency • Programmable ignition ramp • Protection from failure-to-strike • Lamp filament sensing & protection • Protection from operation below resonance • Protection from low-line condition & automatic restart (mimics a magnetic ballast) • • • • • • • Thermal overload protection Programmable deadtime Integrated 600V level-shifting gate driver Internal 15.6V zener clamp diode on VCC True micropower startup (150uA) Latch immunity protection on all leads ESD protection on all leads Description The IR2157 is a fully integrated, fully protected 600V ballast control IC designed to drive virtually all types of rapid start fluorescent lamp ballasts. Externally programmable features such as preheat time & frequency, ignition ramp characteristics, and running mode operating frequency provide a high degree of flexibility for the ballast design engineer. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, low dc bus conditions, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of this control IC is a variable frequency oscillator with externally programmmable deadtime. Precise control of a 50% duty cycle is accomplished using a T-flip-flop. The IR2157 is available in both 16 pin DIP and 16 pin narrow body SOIC packages. Packages 16 Lead SOIC (narrow body) 16 Lead PDIP Typical Connection + Rectified AC Line + VBUS R2 R1 VDC HO R Supply 1 16 VS Q1 R GHS C BS C SNUBBER N/C C1 C PH C IGN RT C START R START CT R DT R PH R RUN CPH C BLOCK L RES 2 15 IR2157 RPH VB 3 RT 14 13 VCC 4 RUN D BOOT R SNUBBER C RES D2 5 CT 12 COM C VCC D1 6 DT 11 LO 7 SD 10 CS Q2 R GLS R3 R CS R5 R4 8 C2 9 V B U S r eturn IR2157 ADVANCED INFORMATION Power Turned On UVLO Mode 1/ 2 -Bridge Off I Q C C ≅ 1 5 0 µA C PH = 0V Oscillator Off SD > 2.0V (Lamp Removal) or VCC < 9.5V (Power Turned Off) VCC > 11.4V ( U V + ) and VDC > 5.1V ( B u s O K ) and SD < 1.7V ( L a m p O K ) and T J < 1 75C ( T jmax ) VCC < 9.5V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Pow e or SD > 2.0V (Lamp Fault or Lamp Remova FAULT Mode Fault Latch Set 1 / 2 -Bridge Off I Q C C ≅ 1 5 0 µA CPH = 0V VCC = 15.6V Oscillator Off T J > 1 75C (Over-Temperature) PREHEAT Mode 1 / 2-Bridge @ f PH C P H Charging @ I PH = 1 µA RPH = 0V RUN = Open Circuit CS Disabled CPH > 4.0V (End of PREHEAT Mode) CS > 1.0V (Failure to Strike Lamp or Hard Switching) or T J > 1 75C (Over-Temperature) IGNITION RAMP Mode f PH r amps to f MIN C P H Charging @ I PH = 1 µA RPH = Open Circuit RUN = Open Circuit CS 1V Threshold Enabled CS > 1.0V (Over-Current or Hard Switching) or CS < 0.2V (No-Load or Below Resonance) or T J > 1 75C (Over-Temperature) CPH > 5.1V (End of IGNITION RAMP) RUN Mode f MIN R amps to f R UN C P H Charges to 7.6V Clamp RPH = Open Circuit RUN = 0V CS 0.2V Threshold Enabled 2 ADVANCED INFORMATION IR2157 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO IOMAX IRT VCT ICPH VRPH VRUN VDT VCS VSD ICC dV/dt PD RthJA TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Maximum allowable output current due to miller effect RT pin current CT pin voltage CPH pin current RPH pin voltage RUN pin voltage Deadtime pin voltage Current sense pin voltage Shutdown pin voltage Supply current (note 1) Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25°C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (16 lead PDIP) (16 lead SOIC) (16 lead PDIP) (16 lead SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -500 -5 -0.3 -5 -0.3 -0.3 -0.3 -0.3 -0.3 — -50 — — — — -55 -55 — Max. 625 VB + 0.3 VB + 0.3 VCC + 0.3 500 5 VCC + 0.3 5 VCC + 0.3 VCC + 0.3 5.5 5.5 5.5 20 50 1.60 1.25 75 100 150 150 300 Units V mA V mA V mA V/ns °C/W °C Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. 3 IR2157 ADVANCED INFORMATION Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBs VS VCC ICC VDC CT RDT IRT IRPH IRUN ISD ICS TJ Definition High side floating supply voltage Steady state high side floating supply offset voltage Supply voltage Supply current VDC lead voltage CT lead capacitance Deadtime resistance RT lead current (note 3) RPH lead current (note 3) RUN lead current (note 3) Shutdown lead current Current sense lead current Junction temperature Min. V CC - 0.7 -3.0 VCCUV+ note 2 0 220 1.0 -500 0 0 -1 -1 -40 Max. VCLAMP 600 VCLAMP 10 VCC — Units V mA V pF — -50 450 450 1 1 125 kΩ uA uA uA mA mA o C Electrical Characteristics VCC = VBS = VBIAS = 15V +/- 0.25V, RT = 40.0kΩ, CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT = 6.1kΩ, VCS = 0.5V, VSD = 0.0V, CL = 1000pF, TA = 25oC unless otherwise specified. Supply Characteristics Symbol Definition VCCUV+ VCC supply undervoltage positive going threshold VCC supply undervoltage positive going VCCUVthreshold VHYSTUV VCC supply undervoltage lockout hysteresis IQCCUV UVLO mode quiescent current IQCCFLT Fault-mode quiescent current (undervoltage lockout, shutdown, over-current, over-temp) IQCC Quiescent VCC supply current IQCC50K VCLAMP Note 2: Note 3: VCC supply current, f= 50kHz VCC zener clamp voltage Min. — — — — — — — — Typ. 11.4 9.6 1.8 150 200 3.8 4.5 15.6 Max. — — — — — — — — Units Test Conditions VCC rising from 0V V VCC falling from 15V VCC= 10V rising µA RT no connection, CT connected to COM RT =36kΩ, RDT = 5.6kΩ, CT=220pF I CC = 10mA mA V Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead regulating its voltage. Due to the fact that the RT input is a voltage-controlled current source, the total RT pin current is sum of all of the parallel current sources connected to that pin. For optimum oscillator current mirror performance, this total current should be kept between 50mA and 500mA. During the preheat mode, the total current flowing out of the RT pin consists of the RPH pin current plus the current due to the RT resistor. During the run mode, the total RT pin current consists of the RUN pin current plus the the current due to the RT resistor. 4 ADVANCED INFORMATION IR2157 Electrical Characteristics (cont.) Floating Supply Characteristics Symbol Definition IQBS0 Quiescent VBS supply current IQBS1 Quiescent VBS supply current VBSMIN Minimum required VBS voltage for proper HO functionality ILK Offset supply leakage current Min. — — — — Typ. 0 30 4 — Max. — — 5 50 Units Test Conditions µA V µA VB = VS = 600V VHO = VS VHO = VB Oscillator I/O Characteristics Symbol Definition fosc Oscillator frequency Min. — — Typ. 30 100 0.5 0.02 50 4.0 2.0 0 2.0 0 2.0 2.0 0.5 0.02 Max. — — — — — — — — — — — — — — Units Test Conditions kHz RT = 32kΩ, RDT = 6.1kΩ, CT=470pF RT = 6.1kΩ, RDT = 6.1kΩ, CT=470pF VCCUV+ < VCC < 15V -40oC < Tj < 125oC df/dV df/dT d VCT+ VCTVCTFLT VRT VRTFLT tdlo toho dtd/dV dtd/dT Oscillator frequency voltage stability Oscillator frequency temperature stability Oscillator duty cycle Upper CT ramp voltage threshold Lower CT ramp voltage threshold Fault-mode CT pin voltage RT pin voltage Fault-mode RT pin voltage LO output deadtime HO output deadtime Deadtime voltage stability Deadtime temperature stability — — — — — — — — — — — — %/V %/C % V mV V mV µsec %/V %/C SD = 5V, CS = 2V, or Tj > TSD SD = 5V, CS = 2V, or Tj > TSD VCCUV+ < VCC < 15V -40oC < Tj < 125oC Preheat Characteristics Symbol Definition ICPH VCPHIGN VCPHRUN VCPHCLMP VCPHFLT CPH pin charging current CPH pin lgnition mode threshold voltage CPH pin run mode threshold voltage CPH pin clamp voltage Fault-mode CPH pin voltage Min. — — — — — Typ. 1.0 4.0 5.15 7.6 0 Max. — — — — — Units Test Conditions µA V mV ICPH = 1mA SD = 5V, CS = 2V, or Tj > TSD VCPH = 0V 5 IR2157 ADVANCED INFORMATION Electrical Characteristics (cont.) RPH Characteristics Symbol Definition IRPHLK VRPHFLT Open circuit RPH pin leakage current Fault-mode RPH pin voltage Min. — — Typ. 0.1 0 Max. — — Units Test Conditions µA mV VRPH = 5V,VRPH = 5V SD = 5V, CS = 2V, or Tj > TSD RUN Characteristics Symbol Definition IRUNLK VRUNFLT Open circuit RUN pin leakage current Fault-mode RUN pin voltage Min. — — Typ. 0.1 0 Max. — — Units Test Conditions µA mV VRUN = 5V SD = 5V, CS = 2V, or Tj > TSD Protection Circuitry Characteristics Symbol Definition VSDTH+ VSDHYS VCSTH+ VCSTHTCS VDC+ VDCTSD Rising shutdown pin threshold voltage Shutdown pin threshold hysteresis Over-current sense threshold voltage Under-current sense threshold voltage Over-current sense propogation delay Low VBUS /rectified line input upper threshold Low VBUS /rectified line input lower threshold Thermal shutdown junction temperature Min. — — — — — — — — Typ. 2.0 150 1.0 0.2 160 5.15 3.0 175 Max. — — — — — — — — Units Test Conditions V mV V nsec Delay from CS to LO or HO V o C Gate Driver Output Characteristics Symbol Definition VOL VOH tr tf Low-level output voltage High level output voltage Turn-on rise time Turn-off fall time Min. — — — — Typ. 0 0 85 45 Max. 100 100 150 100 Units Test Conditions mV nsec Io = 0 VBIAS - VO, Io = 0 Note 4: When the IC senses an overtemperature condition (Tj > 175ºC), the IC is latched off. In order to reset this Fault Latch, the SD pin must be cycled high and then low, or the VCC supply to the IC must be cycled below the falling undervoltage lockout threshold (VCCUV-). 6 ADVANCED INFORMATION IR2157 Lead Assignments & Definitions Lead # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol Description VDC CPH RPH RT RUN CT DT SD CS LO COM VCC N/C VB VS HO DC bus sensing input Preheat timing capacitor Preheat frequency resistor & ignition capacitor Oscillator timing resistor Run frequency resistor Oscillator timing capacitor Deadtime programming Shutdown input Current sensing input Low-side gate driver output IC Power & signal ground Logic & low-side gate driver supply Unused High-side gate driver floating supply High voltage floating return High-side gate driver output VDC CPH RPH RT RUN CT DT SD 1 2 16 15 HO VS VB N/C VCC COM LO CS IR2157 3 4 5 6 7 8 14 13 12 11 10 9 Functional Block Diagram 3.0V VDC 1 S R 5.1V 14 VB Q Q LEVEL SHIFT PULSE FILTER & LATCH 16 HO 15 VS 1.0uA CPH 2 7.6V 5.1V S 4.0V 4.0V Q T R Q Q R1 2.0V 12 VCC 10 LO 15.6V RPH 3 I RT R2 Q RT 4 2.0V 11 COM RUN 5 I CT = I RT Q Q Q S R Q D CLK R 0.2V CT 6 DT 7 9 CS 1.0V SD 8 2.0V UNDERVOLTAGE DETECT OVERTEMP DETECT 7 IR2157 ADVANCED INFORMATION 16 Lead SOIC (narrow body) 01-3064 00 16 Lead PDIP 8 01-3065 00 ADVANCED INFORMATION IR2157 Description of Operation & Component Selection Tips Supply Bypassing and PC Board Layout Rules Component selection and placement on the pc board is extremely important when using power control ICs VCC should be bypassed to COM as close to the IC terminals as possible with a low ESR/ESL capacitor, as shown in Figure 1 below. Connecting the IC Ground (COM) to the Power Ground Both the low power control circuitry and low side gate driver output stage grounds return to this pin within the IC. The COM pin should be connected to the bottom terminal of the current sense resistor in the source of the low side power MOSFET using an individual pc board trace, as shown in Figure 2. In addition, the ground return path of the timing components and VCC decoupling capacitor should be connected directly to the IC COM pin, and not via separate traces or jumpers to other ground traces on the board. pin 1 C B O O T ( surface mount) IR2157 D Boot ( surface mount) C VCC ( through hole) C VCC ( surface mount) IR2157 p in 1 C VCC ( surface mount ) Figure 1: Supply bypassing PCB layout example timin g components C VCC ( throu g h hole ) R C S ( throu g h hole ) A rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (Ciss) of the power transistors being driven. This decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electrolytic (e.g., 10mF) placed immediately adjacent to the VCC and COM terminals will work well. In a typical application circuit, the supply voltage to the IC is normally derived by means of a high value startup resistor (1/4W) from the rectified line voltage, in combination with a charge pump from the output of the half-bridge. With this type of supply arrangement, the internal 15.6V zener clamp diode from VCC to COM will determine the steady state IC supply voltage. V B U S r eturn Figure 2: COM pin connection PCB layout example These connection technique prevents high current ground loops from interfering with sensitive timing component operation, and allows the entire control circuit to reject common-mode noise due to output switching. 9 IR2157 ADVANCED INFORMATION The Control Sequence & Timing Component Selection The IR2157 uses the following control sequence (Figure 3) to drive rapid start fluorescent lamps. f Start frequency fP H fR u n f min t 5V The heart of this controller is an oscillator which resembles those found in many popular PWM voltage regulator ICs. In its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. The voltage across the timing capacitor CT is a sawtooth, where the rising portion of the ramp is determined by the current in the RT pin, and the falling portion of the ramp is determined by an external deadtime resistor RDT. The oscillograph in Figure 4 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. V CPH 2V V RPH 2V V RUN Ignition R u n m o d e Ramp mode Preheat mode Figure 3: IR2157 control sequence Figure 4 The control sequence used in the IR2157 allows the Run Mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). This control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant LC component tolerances (please note that it is possible to use the IR2157 in systems where fstart > fph > fign > frun, simply by leaving the RUN pin open). Six pins in the IC are used to control the Startup, Preheat, Ignition Ramp, and R un m odes of operation, and to allow ballast and lamp engineers the flexibility to optimize their designs for virtually any lamp type. The deadtime can be programmed by means of the external RDT resistor, given a certain range of CT capacitor values, using the graph shown in Figure 5. The RT input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0V. In order to maintain proper linearity between the RT pin current and the CT capacitor charging current, the value of the RT pin current should be kept between 50µA and 500µA. The RT pin can also be used as a feedback point for closed loop control. 10 ADVANCED INFORMATION IR2157 10 tDEAD (usec) CT = 220 pF CT = 470 pF CT = 1 nF 1 During the Startup Mode, the operating frequency is determined by the parallel combination of RPH, RSTART , and RT , combined with the values of CSTART, CT and RDT , as shown in Figure 6. This frequency is normally chosen to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp. As the voltage across CSTART charges up to the RT pin voltage, the output frequency exponentially decays to the preheat frequency. During the Preheat Mode, the operating frequency is determined by the parallel combination of RPH and RT , combined with the value of CT and RDT . This frequency, along with the Preheat Time, is normally chosen to ensure that adequate heating of the lamp filaments occurs. Typically, a 4.5:1 ratio of 0.1 1 10 100 RDT (Kohms) Figure 5: Deadtime versus RDT CPH 2 C PH 7.6V 5.1V 1.0uA S 4.0V Q RPH 3 C IGN RT C START R START R PH 4.0V 2.0V R1 R2 Q RT 4 RUN 5 CT 6 IRT 2.0V R RUN ICT = IRT CT R DT DT 7 UNDERVOLTAGE DETECT Figure 6: Oscillator section block diagram with external component connection 11 IR2157 ADVANCED INFORMATION the hot filament-to-cold filament resistance is desired for maximum lamp life, as shown in Figure 7 The following graphs, Figures 8 and 9, illustrate the relationship between the effective RT resistance (i.e., the parallel combination of resistors which programs the CT capacitor charging current) and the operating frequency. 150 FREQ (KHz) CT=220pF, RDT=11K CT=470pF, RDT=6.2K CT=1nF, RDT=3K 100 50 Figure 7: Lamp filament voltage during the preheat, ignition ramp and run modes. 0 0 5 10 15 20 RT (K ohms) 25 30 35 40 The Preheat Time is programmed by means of the preheat capacitor, CPH, an internal 1mA current source, and an internal threshold on the CPH pin of 4.0V, according to the following formula: Figure 8: fosc versus effective RT (tDEAD = 2.0 usec) tPH = 4E6 ⋅ CPH, or CPH = 250E- 9 ⋅ tPH At the end of the Preheat Time, the internal, opendrain transistor holding the RPH pin to ground turns off, and the voltage on this pin charges exponentially up to the RT pin potential. During this Ignition Ramp Mode, the output frequency exponentially decays to a minimum value. The rate of decay of this frequency is a function of the RPH * CPH time constant. Because the Ignition Ramp Mode ends when the voltage on the CPH pin reaches 5.15V, the ignition ramp is always 1/4th as long as the preheat time. When the CPH pin reaches 5.15V, an open-drain transistor on the RUN pin turns on, and the external RRUN resistor is then in parallel with the RT resistor. The Run Mode operating frequency is therefore a function of the parallel combination of RRUN and RT , and this means that the operating power of the lamp can be programmed by means of RRUN . 250 200 CT=220pF , RDT=5.6K CT=470pF , RDT=2.7K CT=1nF, RDT=1.2K 150 FREQ (KHz) 100 50 0 0 5 10 15 20 RT (K ohms ) 25 30 35 40 Figure 9: fosc versus effective RT (tDEAD = 1.0 usec) 12 ADVANCED INFORMATION IR2157 Lamp Protection & Automatic Restart Circuitry Operation Three pins on the IR2157 are used for protection, as shown in Figure 10 below. These are VDC (dc bus monitor), SD (unlatched shutdown), and CS (latched shutdown). + V BUS R2 VDC 1 3.0V S R 5.1V Q Q R1 C1 from oscillator section CPH 2 7.6V 1.0uA T R Q Q 5.1V Q2 4.0V R4 Q D CLK 0.2V CS 9 R3 R CS from lamp lower cathode R5 DT 7 Q Q S R Q R SD 8 2.0V 1.0V C2 UNDERVOLTAGE DETECT OVERTEMP DETECT Figure 10: Lamp protection & automatic restart circuitry block diagram with external component connection. Sensing the DC Bus Voltage The first of these protection pins senses the voltage on the DC bus by means of an external resistor divider and an internal comparator with hysteresis. When power is first supplied to the IC at system startup, 3 conditions are required before oscillation is initiated: 1.) the voltage on the VCC pin must exceed the rising undervoltage lockout threshold (11.5V), 2.) the voltage at the VDC pin must exceed 5.1V, and 3.) the voltage on the SD pin must be below approximately 1.85V. If a low dc bus condition occurs during normal operation, or if power to the ballast is shut off, the dc bus will collapse prior to the VCC of the chip (assuming the VCC is derived from a charge pump off of the output of the half-bridge). In this case, the voltage on the VDC pin will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switching. Approximately 2V of hysteresis has been designed into the internal comparator sensing the VDC pin, in order to account for variations in the dc bus voltage under varying load conditions. When the dc bus recovers, the chip restarts from the beginning of the control sequence, as shown in timing diagram 11 below. 13 IR2157 ADVANCED INFORMATION rectified AC line + VB U S VDC HO 1 16 VS Q1 RGHS CBLOCK VB 5 VDC 3 CPH 2 15 LRES IR2157 RPH 3 RT 14 N/C C BOOT D BOOT R SUPPLY RSNUBBER CS N U B B E R CRES D2 Q2 4 RUN 13 VCC D1 5 12 COM 4 CT 6 11 LO CVCC CT DT 7 SD 10 CS R GLS R3 R4 R5 8 9 RCS 8 C2 CPH V B U S r eturn 15 LO Figure 12: Lamp presence detection circuit connection (shaded area) 15 HO-VS 2 SD RUN mode Low VDC Restart 4 Figure 11: VDC pin fault and auto restart CT 8 Lamp Presence Detection and Automatic Restart The second protection pin, SD, is used for both unlatched shutdown and automatic restart functions. The SD pin would normally be connected to an external circuit which senses the presence of the lamp (or lamps), as shown in Figure 12. When the SD pin exceeds 2.0V (approximately 150mV of hysteresis is included to increase noise immunity), signaling either a lamp fault or lamp removal, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. Since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted into the fixture, the SD pin would be pulled back to near the ground potential. Under these CPH 15 LO 15 HO-VS RUN mode SD mode Restart Figure 13: SD pin fault and auto restart conditions a reset signal would restart the chip from the beginning of the control sequence, as shown in the timing diagram in Figure 13. 14 ADVANCED INFORMATION IR2157 Thus, for a lamp removal and replacement, the ballast automatically restarts the lamp in the proper manner, maximizing lamp life and minimizing stress on the power MOSFETs or IGBTs. The SD pin contains an internal 7.5V zener diode clamp, thereby reducing the number of external components required. and under-resonance conditions, there is a negativegoing threshold of 0.2V which is enabled at the onset of the run mode. The sensing of this 0.2V threshold is synchronized with the falling edge of the LO output. Figures 15, 16 and 17 are oscillographs of fault conditions. Figure 15 shows a failure of the lamp to strike, Figure 16 shows a hard switching condition and Figure 17 shows an under-current condition. Half-Bridge Current Sensing and Protection The third pin used for protection is the CS pin, which is normally connected to a resistor in the source of the lower power MOSFET, as shown in Figure 14. The CS pin is used to sense fault conditions such a failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. If any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. The CS pin performs its sensing functions on a cycle-by-cycle basis in order to maximize ballast reliability. failure-to-strike, and For the over-current, hard switching fault conditions, the 1V, positive-going CS threshold is enabled at the end of the preheat time. For the under-current Figure 15: Lamp failure to strike rectified AC line +V B U S VDC HO 1 CPH 16 VS Q1 R GHS 1 2 15 IR2157 RPH VB / 2 B ridge output 3 RT 14 N/C CBOOT DBOOT VCC R SUPPLY R SNUBBER C SNUBBER 4 RUN 13 12 COM D1 5 CT 6 DT 11 LO C VCC Q2 D2 7 SD 10 CS R GLS R3 8 9 R CS V B U S r eturn Figure 14: Half-bridge current sensing circuit connection (shaded area) Figure 16: Hard switching condition 15 IR2157 ADVANCED INFORMATION Recovery from such a fault condition is accomplished by cycling either SD pin or the VCC pin. When a lamp is removed, the SD pin goes high, the fault latch is reset, and the chip is held off in an unlatched state. Lamp replacement causes the SD pin to go low again, reinitiating the startup sequence. The fault latch can also be reset by the undervoltage lockout signal, if VCC falls below the lower undervoltage threshold. Bootstrap Supply Considerations Power is normally supplied to the high-side circuitry by means of a simple charge pump from VCC, as shown in Figure 19 below. rectified AC line +V B U S VDC HO Figure 17: Operation below resonance CPH RPH 1 2 16 VS Q1 R GHS 1 15 IR2157 VB / 2 B ridge output 3 RT 14 N/C CBOOT DBOOT VCC R SUPPLY RSNUBBER CSNUBBER 4 RUN 13 12 COM D1 5 CT 6 DT 11 LO C VCC Q2 D2 7 SD 10 CS R GLS R3 8 9 R CS V B U S r eturn Figure 19: Typical bootstrap supply connection with VCC charge pump from half-bridge output (shaded area) Figure 18: Auto restart for lamp replacement A high voltage, fast recovery diode DBOOT (the socalled bootstrap diode) is connected between VCC (anode) and VB (cathode), and a capacitor CBOOT (the so-called bootstrap capacitor) is connected between the VB and VS pins. During half-bridge switching, when MOSFET Q2 is on and Q1 is off, the bootstrap capacitor CBOOT is charged from the VCC decoupling capacitor, through the bootstrap diode DBOOT, and through Q2. Alternately, when Q2 is off and Q1 is on, the bootstrap diode is reverse-biased, 16 ADVANCED INFORMATION IR2157 and the bootstrap capacitor (which ‘floats’ on the source of the upper power MOSFET) serves as the power supply to the upper gate driver CMOS circuitry. Since the quiescent current in this CMOS circuitry is very low (typically 45mA in the on-state), the majority of the drop in the VBS voltage when Q1 is on occurs due to the transfer of charge from the bootstrap capacitor to the gate of the power MOSFET. VB should be bypassed to VS as close as possible to the pins of the IC with a low ESR/ESL capacitor. A PCB layout example is shown in figure 20. A rule of thumb for the value of this capacitor is to keep its minimum value at least 50 times the value of the total input capacitance (Ciss) of the MOSFET or IGBT being driven. In addition, the VS pin should be connected directly to the high side power MOSFET source. pin 1 C B O O T ( surface mount) IR2157 D Boot ( surface mount) C VCC ( through hole) C VCC ( surface mount) Figure 20: Supply bypassing PCB layout example Characteristic Curves 100 0.15 0.125 T = -25 T = 25C T = 75C I qcc (mA) 0.1 T = 125C 10 1 Iqcc (mA) 0.1 0.075 0.05 0.01 0.025 0 0.001 0 2 4 6 8 VCC (volts) 10 12 14 16 0 2 4 6 VCC (volts) 8 10 12 Figure 21: IQCC versus VCC 4 Figure 22: I QCC versus V CC and temperature (VCC < VCC+) 30 25 T = -25 3.5 I qcc (mA) 15 20 T = 25C T = 75C T = 125C I qcc (mA) 3 T = -25 T = 25C T = 75C T = 125C 10 5 2.5 11.5 12.5 VCC (volts) 13.5 14.5 0 14.5 15 15.5 VCC (volts) 16 16.5 Figure 23: IQCC versus VCC and temperature (VCC > VCC+) Figure 24: VCLAMP versus I QCC and temperature 17 IR2157 12 ADVANCED INFORMATION 80 70 T = -25C T = 25C T = 75C T = 125C 11.5 Vccuv+ 11 Vccuv (V) 10.5 60 50 I qbs1 40 (uA) 30 10 Vccuv9.5 20 10 9 -25 0 0 25 50 Temperature (C) 75 100 125 0 2 4 6 8 10 VBS ( volts) 12 14 16 18 20 Figure 25: VCCUV+ and VCCUV- versus temperature Figure 26: IQBS1 versus VBS 54 53.75 53.5 53.25 fOSC (KHz) 53 52.75 52.5 52.25 52 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 fOSC (KHz) T = -25C T = 25C T = 75C T = 125C 210 207.5 205 202.5 200 197.5 195 192.5 190 11 11.5 12 12.5 13 VCC (volts ) 13.5 14 14.5 15 T = -25C T = 25C T = 75C T = 125C Figure 27: fOSC versus VCC and temperature (RT=330kΩ, CT=300pF) Figure 28: fOSC versus VCC and temperature (RT=6.2kΩ, CT=300pF) 1000 990 980 970 T = -25C T = 25C T = 75C T = 125C 80 T = -25C 70 T = 25C T = 75C T = 125C 60 960 tDEAD 950 (nsec) 940 930 920 910 900 11 11.5 12 12.5 13 VCC (volts ) 13.5 14 14.5 15 20 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 50 tfall (nsec) 40 30 Figure 29: tDEAD versus VCC and temperature Figure 30: tfall versus VCC and temperature 18 ADVANCED INFORMATION IR2157 160 T = -25C T = 25C 140 T = 75C T = 125C 120 1.1 T = -25C 1.08 T = 25C T = 75C T = 125C 1.06 trise 100 (nsec) CS+ (volts) 1.04 80 1.02 60 40 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 1 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 Figure 31: trise versus VCC and temperature Figure 32: CS+ threshold versus VCC and temperature 0.235 T = -25C T = 25C T = 75C 0.225 T = 125C 2.15 T = -25C 2.125 T = 25C T = 75C T = 125C 2.1 SD+ (volts) 2.075 0.23 0.22 CS(volts) 0.215 2.05 0.21 2.025 0.205 0.2 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 2 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 Figure 33: CS- threshold versus VCC and temperature Figure 34: SD+ threshold versus VCC and temperature 0.25 T = -25C T = 25C 0.225 T = 75C T = 125C SD hysterisis (volts) 0.175 0.2 5.4 T = -25C 5.35 T = 25C T = 75C 5.3 T = 125C VDC+ (volts) 5.25 5.2 0.15 5.15 5.1 0.125 5.05 0.1 11 11.5 12 12.5 13 VCC (volts) 13.5 14 14.5 15 5 11 11.5 12 12.5 13 VCC ( volts) 13.5 14 14.5 15 Figure 35: SD hysterisis versus VCC and temperature Figure 36: VDC+ threshold versus VCC and temperature 19 IR2157 3.3 ADVANCED INFORMATION 4.15 3.25 T = -25C T = 25C T = 75C T = 125C 4.1 T = -25C T = 25C T = 75C T = 125C 3.2 4.05 VDC3.15 (volts) 3.1 VCPHIGN (volts) 4 3.95 3.05 3.9 11 3 11 11.5 12 12.5 13 13.5 VCC (volts) 14 14.5 15 11.5 12 12.5 13 13.5 VCC (volts) 14 14.5 15 Figure 37: VDC- threshold versus VCC and temperature Figure 38: VCPHIGN threshold versus VCC and temperature 5.25 1.2 T= T= T= T= -25C 25C 75C 125C 1.15 1.1 1.05 ICPH (uA) 1 5.2 5.15 VCPHRUN (volts) 5.1 0.95 5.05 0.9 0.85 T = -25C T = 25C T = 75C T = 125C 11.5 12 12.5 13 13.5 VCC ( volts) 14 14.5 15 5 11 11.5 12 12.5 13 13.5 VCC (volts) 14 14.5 15 0.8 11 Figure 39: VCPHRUN threshold versus VCC and temperature Figure 40: ICPH versus V CC and temperature WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 322 3331 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2 Tel: (905) 453-2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: 65 838 4630 IR TAIWAN: 16 Fl. Suite D..207, Sec.2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936 http://www.irf.com/ Data and specifications subject to change without notice. 3/1/99 20