IR21571

Data Sheet PD No. 60179-I IR21571(S) FULLY INTEGRATED BALLAST CONTROL IC Features • Programmable preheat time & frequency • Programmable ignition ramp • Protection from failure-to-strike • Lamp filament sensing & protection • Protection from operation below resonance • Protection from low-line condition • Automatic restart for lamp exchange • Thermal overload protection • Programmable deadtime • Integrated 600V level-shifting gate driver • Internal 15.6V zener clamp diode on VCC • Micropower startup (150uA) • Latch immunity protection on all leads • ESD protection on all leads 0.2V CS threshold sync’d to falling edge on LO Description The IR21571 is a fully integrated, fully protected 600V ballast control IC designed to drive virtually all types of rapid start fluorescent lamp ballasts. Externally programmable features such as preheat time & frequency, ignition ramp characteristics, and running mode operating frequency provide a high degree of flexibility for the ballast design engineer. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, low dc bus conditions, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of this control IC is a variable frequency oscillator with externally programmable deadtime. Precise control of a 50% duty cycle is accomplished using a T-flip-flop. The IR21571 is available in both 16 pin DIP and 16 pin narrow body SOIC packages. Packages 16 Lead SOIC (narrow body) 16 Lead PDIP Typical Connection + Rectified AC Line + VBUS R2 R1 VDC HO RSupply 1 16 VS C1 CPH CRAMP RT CSTART RSTART CT ROC RDT RPH RRUN CPH RGHS CBS DBOOT CVCC D1 CBLOCK LRES 2 RPH 15 VB IR21571 3 RT 14 VCC CSNUBBER 4 RUN 13 COM 5 CT 12 D2 LO CRES 6 DT 11 CS R3 RGLS R5 R4 7 OC 10 SD 8 9 C2 RCS VBUS return www.irf.com 1 IR21571(S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO IOMAX IRT VCT VDC ICPH IRPH IRUN IDT VCS ICS IOC ISD ICC dV/dt PD RthJA TJ TS TL Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Maximum allowable output current (either output) due to external power transistor miller effect RT pin current CT pin voltage VDC pin voltage CPH pin current RPH pin current RUN pin current Deadtime pin current Current sense pin voltage Current sense pin current Over-current threshold pin current Shutdown pin current Supply current (note 1) Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25°C PD = (TJMAX-TA)/RthJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (16 lead PDIP) (16 lead SOIC) (16 lead PDIP) (16 lead SOIC) Min. -0.3 V B - 25 VS - 0.3 -0.3 -500 -5 -0.3 -0.3 -5 -5 -5 -5 -0.3 -5 -5 -5 -20 -50 — — — — -55 -55 — Max. 625 VB + 0.3 VB + 0.3 VCC + 0.3 500 Units V mA 5 5.5 VCC + 0.3 5 5 5 5 5.5 5 5 5 20 50 1.60 1.00 75 115 150 150 300 °C °C/W W V/ns mA V mA V Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. 2 www.irf.com IR21571(S) Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBS VS VCC ICC VDC CT RDT ROC IRT IRPH IRUN ISD ICS TJ VBSMIN Definition High side floating supply voltage Steady state high side floating supply offset voltage Supply voltage Supply current VDC lead voltage CT lead capacitance Deadtime resistance Over-current (CS+) threshold programming resistance RT lead current (Note 3) RPH lead current (Note 3) RUN lead current (Note 3) Shutdown lead current Current sense lead current Junction temperature Minimum required VBS voltage for proper HO functionality Min. VCC - 0.7 -3.0 VCCUV+ Note 2 0 220 1.0 Max. VCLAMP 600 VCLAMP 10 VCC — Units V mA V pF — 50 -50 450 450 1 1 125 5 — -500 0 0 -1 -1 -40 — kΩ uA mA o C V Electrical Characteristics VCC = V BS = VBIAS = 14V +/- 0.25V, R T = 40.0k Ω, CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT = 6.1k Ω, R OC = 20.0k Ω, V CS = 0.5V, VSD = 0.0V, CL = 1000pF, TA = 25 oC unless otherwise specified. Supply Characteristics Symbol Definition VCC supply undervoltage positive going threshold VUVHYS VCC supply undervoltage lockout hysteresis IQCCUV UVLO mode quiescent current IQCCFLT Fault-mode quiescent current IQCC ICC50K V CLAMP Note 2: Note 3: Quiescent VCC supply current VCC supply current, f= 50kHz VCC zener clamp voltage VCCUV+ Min. 10.5 1.5 50 75 2.9 4.0 14.5 Typ. 11.4 1.8 150 200 3.8 5.5 15.6 Max. 12.4 Units V Test Conditions VCC rising from 0V 2.2 300 300 4.3 7.0 16.5 µA mA V VCC < VCCUVSD=5V, CS = 2V or Tj > TSD RT no connection, CT connected to COM RT =36kΩ, RDT = 5.6kΩ, CT=220pF ICC = 10mA Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead regulating its voltage. Due to the fact that the RT input is a voltage-controlled current source, the total RT lead current is the sum of all the parallel current sources connected to that lead. For optimum oscillator current mirror performance, this total current should be kept between 50µA and 500µA. During the preheat mode, the total current flowing out of the RT lead consists of the RPH lead current plus the current due to the RT resistor. During the run mode, the total RT lead current consists of the RUN lead current plus the current due to the RT resistor. www.irf.com 3 IR21571(S) Electrical Characteristics (cont.) V CC = V BS = VBIAS = 14V +/- 0.25V, R T = 40.0k Ω , CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT = 6.1kΩ , ROC = 20.0kΩ, VCS = 0.5V, VSD = 0.0V, C L = 1000pF, TA = 25 oC unless otherwise specified. Floating Supply Characteristics Symbol Definition IQBS0 Quiescent VBS supply current IQBS1 Quiescent VBS supply current ILK Offset supply leakage current Min. 0 5 — Typ. 0 35 50 Max. 15 65 µA Units µA Test Conditions — VHO = VS VHO = VB VB = VS = 600V Oscillator I/O Characteristics Symbol Definition fosc d VCT+ VCTVCTFLT VRT VRTFLT tdlo tdho Oscillator frequency Oscillator duty cycle Upper CT ramp voltage threshold Lower CT ramp voltage threshold Fault-mode CT lead voltage RT lead voltage Fault-mode RT lead voltage LO output deadtime HO output deadtime Min. 45.5 49.5 3.7 1.85 — 1.85 — 2 2 Typ. 48 50 4.0 2.0 0 2.0 0 2.3 2.3 Max. 50.5 50.5 4.3 2.15 50 2.15 50 2.5 2.5 Units Test Conditions kHz % V mV V mV µ sec SD = 5V, CS = 2V, or Tj > TSD SD = 5V, CS = 2V, or Tj > TSD RT = 16.9kΩ, RDT = 6.1kΩ, CT=470pF Preheat Characteristics Symbol Definition ICPH VCPHIGN V CPHRUN VCPHCLMP VCPHFLT CPH lead charging current CPH lead lgnition mode threshold voltage CPH lead run mode threshold voltage CPH lead clamp voltage Fault-mode CPH lead voltage Min. 0.72 3.7 4.7 9.0 — Typ. 0.85 4.0 5.15 9.5 0 Max. 0.98 4.3 5.45 10.5 300 Units Test Conditions µA V mV ICPH = 1mA SD = 5V, CS = 2V, or Tj > TSD VCPH = 5.3V RPH Characteristics Symbol Definition IRPHLK Open circuit RPH lead leakage current VRPHFLT Fault-mode RPH lead voltage Min. — — Typ. 0.01 0 Max. 0.1 50 Units µA mV Test Conditions VRPH= 5V,VRPH= 6V SD = 5V, CS = 2V, or Tj > TSD 4 www.irf.com IR21571(S) Electrical Characteristics (cont.) VCC = VBS = VBIAS = 14V +/- 0.25V, R T = 40.0k Ω, CT = 470 pF, RPH and RUN leads no connection, VCPH = 0.0V, RDT = 6.1k Ω, ROC = 20.0kΩ, VCS = 0.5V, VSD = 0.0V, CL = 1000pF, TA = 25 oC unless otherwise specified. RUN Characteristics Symbol Definition IRUNLK Open circuit RUN lead leakage current VRUNFLT Fault-mode RUN lead voltage Min. — — Typ. 0.01 0 Max. 0.1 50 Units µA mV Test Conditions VRUN = 5V SD = 5V, CS = 2V, or Tj > TSD Protection Circuitry Characteristics Symbol Definition VSD+ VSDHYS VCS+ VCSTCS VDC+ VDCTSD Rising shutdown lead threshold voltage Shutdown pin threshold hysteresis Over-current sense threshold voltage Under-current sense threshold voltage Over-current sense propogation delay Low VBUS/rectified line input upper threshold Low VBUS/rectified line input lower threshold Thermal shutdown junction temperature Min. 1.9 100 0.99 0.15 100 5.0 2.85 150 Typ. 2.1 150 1.10 0.2 250 5.20 3.3 160 Max. 2.3 200 1.21 0.35 400 5.6 3.3 170 Units V mV V nsec V oC Test Conditions Delay from CS to LO Note 4 Gate Driver Output Characteristics Symbol Definition VOL VOH tr tf Note 4: Low-level output voltage High level output voltage Turn-on rise time Turn-off fall time Min. — — 55 35 Typ. 0 0 85 45 Max. 100 100 150 100 Units mV nsec Test Conditions Io = 0 VBIAS - VO, Io = 0 When the IC senses an overtemperature condition (Tj > 160ºC), the IC is latched off. In order to reset this Fault Latch, the SD lead must be cycled high and then low, or the VCC supply to the IC must be cycled below the falling undervoltage lockout threshold (VCCUV-). www.irf.com 5 IR21571(S) Functional Block Diagram 3.0V VDC 1 S R 5.1V 14 Q Q VB HO VS LEVEL SHIFT PULSE FILTER & LATCH 16 1.0uA CPH 2 10V 5.1V 15 S 4.0V 4.0V Q T R Q Q R1 2.0V 13 11 15.6V VCC LO COM RPH 3 IR R2 Q RT 4 RUN 5 T 2.0V 12 IC = IR T T Q Q Q S R Q D CLK R 0.2V CT DT 6 7 10 CS 7.6V 50uA OC 8 7.6V UNDERVOLTAGE DETECT OVERTEMP DETECT 9 2.0V 7.6V SD Lead Assignments & Definitions Pin # Symbol VDC CPH RPH RT RUN CT DT OC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Description DC Bus Sensing Input Preheat Timing Capacitor Preheat Frequency Resistor & Ignition Capacitor Oscillator Timing Resistor Run Frequency Resistor Oscillator Timing Capacitor Deadtime Programming Over-current (CS+) Threshold Programming Shutdown Input Current Sensing Input Low-Side Gate Driver Output IC Power & Signal Ground Logic & Low-Side Gate Driver Supply High-Side Gate Driver Floating Supply High Voltage Floating Return High-Side Gate Driver Output HO VS VB VCC COM LO CS SD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDC CPH RPH RT RUN CT DT OC SD CS LO COM VCC VB VS HO IR21571 6 www.irf.com IR21571(S) IR21571 State Diagram Power Turned On UVLO Mode 1/ -Bridge 2 Off IQCC ≅ 150 A µ CPH = 0V Oscillator Off VCC > 11.4V(UV+) and VDC > 5.1VBus OK) ( and SD < 1.7V(Lamp OK) and TJ < 160C (Tjmax) VCC < 9.5V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Power Down) or SD > 2.0V (Lamp Fault or Lamp Removal) SD > 2.0V (Lamp Removal) or VCC < 9.5V (Power Turned Off) FAULT Mode Fault Latch Set 1/ -Bridge Off 2 IQCC ≅ 150 A µ CPH = 0V VCC = 15.6V Oscillator Off TJ > 160C (Over-Temperature) PREHEAT Mode 1/ -Bridge @ f 2 PH CPH Charging @PH = 1µA I RPH = 0V RUN = Open Circuit CS Disabled CS > CS+ Threshold (Failure to Strike Lamp or Hard Switching) or TJ > 160C (Over-Temperature) CPH > 4.0V (End of PREHEAT Mode) IGNITION RAMP Mode fPH ramps to MIN f CPH Charging @PH = 1µA I RPH = Open Circuit RUN = Open Circuit CS+ Threshold Enabled CS > CS+ Threshold (Over-Current or Hard Switching) or CS < 0.2V (No-Load or Below Resonance) or TJ > 160C (Over-Temperature) CPH > 5.1V (End of IGNITION RAMP) RUN Mode fMIN Ramps toRUN f CPH Charges to 7.6V Clamp RPH = Open Circuit RUN = 0V CS- Threshold Enabled www.irf.com 7 IR21571(S) Description of Operation & Component Selection Tips Supply Bypassing and PC Board Layout Rules Component selection and placement on the pc board is extremely important when using power control ICs. VCC should be bypassed to COM as close to the IC terminals as possible with a low ESR/ESL capacitor, as shown in Figure 1 below. Connecting the IC Ground (COM) to the Power Ground Both the low power control circuitry and low side gate driver output stage grounds return to this lead within the IC. The COM lead should be connected to the bottom terminal of the current sense resistor in the source of the low side power MOSFET using an individual pc board trace, as shown in Figure 2. In addition, the ground return path of the timing components and VCC decoupling capacitor should be connected directly to the IC COM lead, and not via separate traces or jumpers to other ground traces on the board. CVCC (surface mount) IR21571 pin 1 CBOOT (surface mount) DBoot (surface mount) CVCC (through hole) IR21571 pin 1 CVCC (surface mount) Figure 1: Supply bypassing PCB layout example timing components CVCC (through hole) A rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (Ciss) of the power transistors being driven. This decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electrolytic (e.g., 10µF) placed immediately adjacent to the VCC and COM terminals will work well. In a typical application circuit, the supply voltage to the IC is normally derived by means of a high value startup resistor (1/4W) from the rectified line voltage, in combination with a charge pump from the output of the half-bridge. With this type of supply arrangement, the internal 15.6V zener clamp diode from VCC to COM will determine the steady state IC supply voltage. RCS (through hole) VBUS return Figure 2: COM lead connection PCB layout example This connection technique prevents high current ground loops from interfering with the sensitive timing component operation, and allows the entire control circuit to reject common-mode noise due to output switching. 8 www.irf.com IR21571(S) The Control Sequence & Timing Component Selection The IR21571 uses the following control sequence (Figure 3) to drive rapid start fluorescent lamps. The heart of this controller is an oscillator which resembles those found in many popular PWM voltage regulator ICs. In its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. The voltage across the timing capacitor CT is a sawtooth, where the rising portion of the ramp is determined by the current in the RT lead, and the falling portion of the ramp is determined by an external deadtime resistor RDT. The oscillograph in Figure 4 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. fStart frequency fPH fRun fmin t 5V VCPH 2V VRPH 2V VRUN Ignition Run mode Ramp mode Preheat mode Figure 3: IR21571 control sequence Figure 4 The control sequence used in the IR21571 allows the Run Mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). This control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant LC component tolerances (please note that it is possible to use the IR21571 in systems where fstart > fph > fign > frun, simply by leaving the RUN lead open). Six leads in the IC are used to control the Startup, Preheat, Ignition Ramp, a nd Run m odes of operation, and to allow ballast and lamp engineers the flexibility to optimize their designs for virtually any lamp type. The deadtime can be programmed by means of the external RDT resistor, given a certain range of CT capacitor values, using the graph shown in Figure 5. The RT input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0V. In order to maintain proper linearity between the RT lead current and the CT capacitor charging current, the value of the RT lead current should be kept between 50µA and 500µA. The RT lead can also be used as a feedback point for closed loop control. www.irf.com 9 IR21571(S) 10 tDEAD (usec) CT = 220 pF 1 CT = 470 pF CT = 1 nF During the Startup Mode, the operating frequency is determined by the parallel combination of RPH, RSTART, and RT, combined with the values of CSTART, CT and RDT , as shown in Figure 6. This frequency is normally chosen to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp. As the voltage across CSTART charges up to the RT lead voltage, the output frequency exponentially decays to the preheat frequency. During the Preheat Mode, the operating frequency is determined by the parallel combination of RPH and RT, combined with the value of CT and RDT. This frequency, along with the Preheat Time, is normally chosen to ensure that adequate heating of the lamp filaments occur. Typically, a 4.5:1 ratio of the hot filament-to-cold filament resistance is desired for maximum lamp life, as shown in Figure 7. 0.1 1 10 100 RDT (Kohms) Figure 5: Deadtime versus RDT CPH 2 CPH 7.6V 5.1V 1.0uA 4.0V S R1 Q RPH 3 CIGN RT CSTART RSTART RPH 4.0V 2.0V IRT R2 Q RT 4 RUN 5 CT 6 RRUN 2.0V ICT = I RT CT RDT DT 7 UNDERVOLTAGE DETECT Figure 6: Oscillator section block diagram with external component connection 10 www.irf.com IR21571(S) Preheat Ignition Ramp Run The following graphs, Figures 8 and 9, illustrate the relationship between the effective RT resistance (i.e., the parallel combination of resistors which programs the CT capacitor charging current) and the operating frequency. 150 FREQ (KHz) CT=220pF,RDT=11K CT=470pF,RDT=6.2K CT=1nF,RDT=3K 100 Figure 7: Lamp filament voltage during the preheat, ignition ramp and run modes. 50 The Preheat Time is programmed by means of the preheat capacitor, CPH, an internal 1 µA current source, and an internal threshold on the CPH lead of 4.0V, according to the following formula: 0 0 5 10 15 20 RT (K ohms) 25 30 35 40 Figure 8: fosc versus effective RT (tDEAD = 2.0 usec) tPH = 4.7E6 ⋅ CPH, CPH = 213E - 9 ⋅ tPH or 250 At the end of the Preheat Time, the internal, opendrain transistor holding the RPH lead to ground turns off, and the voltage on this lead charges exponentially up to the RT lead potential. During this Ignition Ramp Mode, the output frequency exponentially decays to a minimum value. The rate of decay of this frequency is a function of the RPH * CPH time constant. Because the Ignition Ramp Mode ends when the voltage on the CPH lead reaches 5.15V, the Ignition Ramp Mode is always 1/4th as long as the preheat time. When the CPH lead reaches 5.15V, an open-drain transistor on the RUN lead turns on, and the external RRUN resistor is then in parallel with the RT resistor. The Run Mode operating frequency is therefore a function of the parallel combination of RRUN and RT, and this means that the operating power of the lamp can be programmed by means of RRUN. 200 CT=220pF, RDT=5.6K CT=470pF, RDT=2.7K CT=1nF, RDT=1.2K 150 FREQ (KHz) 100 50 0 0 5 10 15 20 25 RT (K ohms) 30 35 40 Figure 9: fosc versus effective RT (tDEAD = 1.0 usec) www.irf.com 11 IR21571(S) Lamp Protection & Automatic Restart Circuitry Operation Three leads on the IR21571 are used for protection, as shown in Figure 10 below. These are VDC (dc bus monitor), SD (unlatched shutdown), CS (latched shutdown) and OC (CS+ threshold programming). +VBUS R2 VDC 1 3.0V S R 5.1V Q Q R1 C1 from oscillator section CPH 2 7.6V 1.0uA T R Q Q Q2 5.1V R3 4.0V Q D CLK R 0.2V CS 10 DT 7 RCS Q Q S R Q VCC 7.6V OC 8 ROC 7.6V 50uA UNDERVOLTAGE DETECT OVERTEMP DETECT SD 9 2.0V 7.6V R4 R5 C2 from lower lamp cathode Figure 10: Lamp protection & automatic restart circuitry block diagram with external component connection. Sensing the DC Bus Voltage The first of these protection leads senses the voltage on the DC bus by means of an external resistor divider and an internal comparator with hysteresis. When power is first supplied to the IC at system startup, 3 conditions are required before oscillation is initiated: 1.) the voltage on the VCC lead must exceed the rising undervoltage lockout threshold (11.5V), 2.) the voltage at the VDC lead must exceed 5.1V, and 3.) the voltage on the SD lead must be below approximately 1.85V. If a low dc bus condition occurs during normal operation, or if power to the ballast is shut off, the dc bus will collapse prior to the VCC of the chip (assuming the VCC is derived from a charge pump off of the output of the half-bridge). In this case, the voltage on the VDC lead will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switching. Approximately 2V of hysteresis has been designed into the internal comparator sensing the VDC lead, in order to account for variations in the dc bus voltage under varying load conditions. When the dc bus recovers, the chip restarts from the beginning of the control sequence, as shown in timing diagram Figure 11. 12 www.irf.com IR21571(S) + rectified AC Line 5 + VBUS VDC 3 VDC HO 1 CPH 16 VS RGHS CBS RSupply DBOOT CVCC D1 CBLOCK LRES 2 RPH 15 VB IR21571 3 RT 14 VCC CSNUBBER 4 RUN 4 5 CT 13 COM CT DT 12 D2 LO CRES 6 7 OC 11 CS R3 RGLS R5 R4 8 10 SD CPH 8 9 C2 RCS 15 VBUS return LO Figure 12: Lamp presence detection circuit connection (shaded area) 15 HO-VS SD Restart 2 RUN mode Low VDC 4 Figure 11: VDC lead fault and auto restart CT 8 Lamp Presence Detection and Automatic Restart The second protection lead, SD, is used for both unlatched shutdown and automatic restart functions. The SD lead would normally be connected to an external circuit which senses the presence of the lamp (or lamps), as shown in Figure 12. When the SD lead exceeds 2.0V (approximately 150mV of hysteresis is included to increase noise immunity), signaling either a lamp fault or lamp removal, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. Since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted into the fixture, the SD lead would be pulled back to near the ground potential. Under these CPH 15 LO 15 HO-VS RUN mode SD mode Restart Figure 13: SD lead fault and auto restart conditions a reset signal would restart the chip from the beginning of the control sequence, as shown in the timing diagram in Figure 13. www.irf.com 13 IR21571(S) Thus, for a lamp removal and replacement, the ballast automatically restarts the lamp in the proper manner, maximizing lamp life and minimizing stress on the power MOSFETs or IGBTs. The SD lead contains an internal 7.5V zener diode clamp, thereby reducing the number of external components required. enabled at the end of the preheat time. The level of this positive-going threshold is determined by the value of the resistor ROC. The value of the resistor ROC is determined by the following formula: ROC = VCS+ = Half-Bridge Current Sensing and Protection The third lead used for protection is the CS lead, which is normally connected to a resistor in the source of the lower power MOSFET, as shown in Figure 14. The CS lead is used to sense fault conditions such as failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. If any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. The CS lead performs its sensing functions on a cycle-by-cycle basis in order to maximize ballast reliability. For the over-current, failure-to-strike, and hard switching fault conditions, an externally programmable, positive-going CS+ threshold is rectifie d AC line VDC HO VCS+ or 50E - 6 50E -6 - ROC For the under-current and under-resonance conditions, there is a negative-going CS- threshold of 0.2V which is enabled at the onset of the run mode. The sensing of this CS- threshold is synchronized with the falling edge of the LO output. Figures 15, 16 and 17 are oscillographs of fault conditions. Figure 15 shows a failure of the lamp to strike, Figure 16 shows a hard switching condition and Figure 17 shows an under-current condition. +VBUS 1 CPH 16 VS Q1 RGHS 1 2 RPH 15 VB /2 CBOOT DBOOT Bridge output IR21571 3 RT 14 VCC RSUPPLY D1 CSNUBBER 4 RUN 13 COM 5 CT 12 LO CVCC Q2 6 DT 11 CS RGLS R3 D2 7 OC 10 SD 8 ROC 9 RCS VBUS return Figure 15: Lamp failure to strike Figure 14: Half-bridge current sensing circuit connection (shaded area) 14 www.irf.com IR21571(S) Figure 16: Hard switching condition Figure 18: Auto restart for lamp replacement Recovery from such a fault condition is accomplished by cycling either the SD lead or the VCC lead. When a lamp is removed, the SD lead goes high, the fault latch is reset, and the chip is held off in an unlatched state. Lamp replacement causes the SD lead to go low again, reinitiating the startup sequence. The fault latch can also be reset by the undervoltage lockout signal, if VCC falls below the lower undervoltage threshold. Bootstrap Supply Considerations Power is normally supplied to the high-side circuitry by means of a simple charge pump from VCC, as shown in Figure 19. Figure 17: Operation below resonance www.irf.com 15 IR21571(S) power supply to the upper gate driver CMOS circuitry. Since the quiescent current in this CMOS circuitry is very low (typically 45µA in the on-state), the majority of the drop in the VBS voltage when Q1 is on occurs due to the transfer of charge from the bootstrap capacitor to the gate of the power MOSFET. VB should be bypassed to VS as close as possible to the leads of the IC with a low ESR/ESL capacitor. A PCB layout example is shown in figure 20. A rule of thumb for the value of this capacitor is to keep its minimum value at least 50 times the value of the total input capacitance (Ciss) of the MOSFET or IGBT being driven. In addition, the VS lead should be connected directly to the high side power MOSFET source. rectifie d AC line VDC HO +VBUS 1 CPH 16 VS Q1 RGHS 1 2 RPH 15 VB /2 CBOOT DBOOT Bridge output IR21571 3 RT 14 VCC RSUPPLY D1 CSNUBBER 4 RUN 13 COM 5 CT 12 LO CVCC Q2 6 DT 11 CS RGLS R3 D2 7 OC 10 SD 8 9 RCS VBUS return CVCC (surface mount) IR21571 pin 1 CBOOT (surface mount) DBoot (surface mount) Figure 19: Typical bootstrap supply connection with VCC charge pump from half-bridge output (shaded area) A high voltage, fast recovery diode DBOOT (the socalled bootstrap diode) is connected between VCC (anode) and VB (cathode), and a capacitor CBOOT (the so-called bootstrap capacitor) is connected between the VB and VS leads. During half-bridge switching, when MOSFET Q2 is on and Q1 is off, the bootstrap capacitor CBOOT is charged from the VCC decoupling capacitor, through the bootstrap diode DBOOT, and through Q2. Alternately, when Q2 is off and Q1 is on, the bootstrap diode is reverse-biased, and the bootstrap capacitor (which ‘floats’ on the source of the upper power MOSFET) serves as the CVCC (through hole) Figure 20: Supply bypassing PCB layout example 16 www.irf.com IR21571(S) Case outlines 16-Lead PDIP 01-6015 01-3065 00 (MS-001A) 16-Lead SOIC (narrow body) 01-6018 01-3064 00 (MS-012AC) Data and specifications subject to change without notice 6/28//2003 www.irf.com 17