IR2159S

Preliminary Data Sheet No. PD60169-D IR2159(S) IR21591(S) Features • • • • • • • • • • • • DIMMING BALLAST CONTROL IC • • • • • • Brown-out protection Automatic restart Micro-power startup Zener clamped Vcc Over-temperature protection 16-pin DIP and SOIC package types Ballast control and half-bridge driver in one IC Transformer-less lamp power sensing Closed-loop lamp power control Closed-loop preheat current control Programmable preheat time Programmable preheat current Programmable ignition-to-dim time 0.5 to 5VDC dimming control input Min and max lamp power adjustments Programmable minimum frequency Internal current sense blanking Full lamp fault protection Parameter Deadtime Frequency Range IR2159 1.8us See Graph 3 IR21591 1.0us See Graph 4 Description Description: The IR2159/IR21591 are complete dimming ballast controllers and 600V half-bridge drivers all in one IC. The architecture includes phase control for transformer-less lamp power sensing and regulation which minimizes changes needed to adapt non-dimming ballasts for dimming. Externally programmable features such as preheat time and current, ignition-to-dim time, and a complete dimming interface with minimum and maximum settings provide a high degree of flexibility for the ballast design engineer. Protection from failure of a lamp to strike, filament failures, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of this control IC is a voltagecontrolled oscillator with externally programmable minimum frequency. The IR2159/ IR21591 are available in both 16 pin DIP and 16 pin narrow body SOIC packages. Packages 16 Lead SOIC (narrow body) 16 Lead PDIP Typical Connection + Rectified AC Line + DC Bus RVDC CVDC CVCO CPH RDIM 0.5 to 5VDC RMAX RMIN RFMIN RIPH RVAC RPULL-UP 1 16 Single Lamp Dimmable VDC HO 2 VCO VS 15 3 CPH VB 14 4 DIM VCC 13 5 MAX COM 12 6 MIN LO 11 7 FMIN CS 10 8 IPH SD 9 RCS - DC Bus www.irf.com 1 IR2159/IR21591 (S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO IOMAX VVCO I CPH VIPH VDIM VMAX VMIN VCS ISD ICC dV/dt PD RthJA TJ TS TL Note 1: Definition High side floating supply voltage High side floating supply offset voltage High side floating output voltage Low side output voltage Maximum allowable output current (either output) due to external power transistor miller effect Voltage controlled oscillator input voltage CPH current IPH voltage Dimming control pin input voltage Maximum lamp power setting pin input voltage Minimum lamp power setting pin input voltage Current sense input voltage Shutdown pin current Supply current (note 1) Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25°C PD = (TJMAX-TA)/RthJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (16 pin DIP) (16 pin SOIC) (16 pin DIP) (16 pin SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -500 -0.3 -5 -0.3 -0.3 -0.3 -0.3 -0.3 -5 — -50 — — — — -55 -55 — Max. 625 VB + 25 VB + 0.3 VCC + 0.3 500 6.0 5 5.5 5.5 5.5 5.5 5.5 5 25 50 1.60 1.25 75 115 150 150 300 Units V mA V mA V mA V/ns W o C/W o C This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V (VCLAMP). Please note that this supply pin should not be driven by a DC, low impedance power source greater than the diode clamp voltage (VCLAMP) as specified in the Electrical Characteristics section. 2 www.irf.com IR2159/IR21591 (S) Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBs VS VCC ICC VVCO VDIM VMAX VMIN RFMIN I SD I CS TJ Note 2: Note 3: Definition High side floating supply voltage Steady state high side floating supply offset voltage Supply voltage Supply current VCO pin voltage DIM pin voltage MAX pin current (note 3) MIN pin voltage Minimum frequency setting resistance Shutdown pin current Current sensing pin current Junction temperature Min. VCC - 0.7 -1 VCCUV+ note 2 0 0 -750 1 10 -1 -1 -40 Max. VCLAMP 600 VCLAMP (15.6) 10 5 5 0 3 100 1 1 125 Units V mA V µA V kΩ mA o C Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead regulating its voltage, VCLAMP. The MAX lead is a voltage-controlled current source. For optimum dim interface current mirror performance, this current should be kept between 0 and 750µA. Electrical Characteristics VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, C VCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VCPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Supply Characteristics VCCUV+ VCCHYS IQCCUV IQCCFLT IQCCFMIN IQCCFMAX IQCCFMIN IQCCFMAX VCLAMP VCC supply undervoltage positive going threshold VCC supply undervoltage lockout hysteresis UVLO mode quiescent current Fault-mode quiescent current VCC supply current @ FMIN (IR2159) VCC supply current @ FMAX (IR2159) VCC supply current @ FMIN (IR21591) VCC supply current @ FMAX (IR21591) VCC zener shunt clamp voltage 12.0 1.5 — — — — — — 14.5 12.5 1.6 200 240 5.6 6.6 5.4 6.8 15.6 13.0 V 1.7 — — — — — — 16.5 VCC = 10V SD=5V, CS=2V, or Tj > TSD VVCO = 0V VVCO = 5V VVCO = 0V VVCO = 5V ICC = 10mA µA mA V www.irf.com 3 IR2159/IR21591 (S) Electrical Characteristics (cont.) VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, C VCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Floating Supply Characteristics IQBS0 IQBS1 VBSMIN ILK Quiescent VBS supply current Quiescent VBS supply current Minimum required VBS voltage for proper HO functionality Offset supply leakage current — — — — 0 30 4 — — — 5 50 µA V µA VB = VS = 600V VHO = VS VHO = VB Oscillator I/O Characteristics fvco VCO frequency range (IR2159) (See graph 3) fvco VCO frequency range (IR21591) (See graph 4) d Gate drive outputs duty cycle VVCOFLT Fault-mode VCO pin voltage (UVLO, shutdown, over-current/temp.) IVCOPH Preheat mode VCO pin discharge current IVCODIM Dim mode VCO pin discharge current IVCOPK tDTLO tDTHO tDTLO tDTHO Amplitude control VCO pin charging current LO output deadtime (IR2159) HO output deadtime (IR2159) LO output deadtime (IR21591) HO output deadtime (IR21591) — — — — — — — — — — — — — 25 95 30 230 50 5 1.0 16.0 60.0 1.8 1.8 1.0 1.0 — — — — — kHz % V µA VVCO=0V, RFMIN=39KΩ VVCO=5V, RFMIN=10KΩ VVCO=0V, RFMIN=68KΩ VVCO=5V, RFMIN=10KΩ VVCO = 0V — — — — — — — VCPH < 5V µA µs VCPH < 5V, VCS >VIPH Gate Driver Output Characteristics VOL VOH tr tf Low-level output voltage High-level output voltage Turn-on rise time Turn-off fall time — — — — — — — — 100 100 150 100 mV ns VBIAS - Vo 4 www.irf.com IR2159/IR21591 (S) Electrical Characteristics (cont.) VCC = VBS = VBIAS = 14V +/- 0.25V, VCS = 0.5V, VSD = 0.0V, RFMIN = 40k, C VCO = 10 nF, VDIM = 0.0V, RMAX = 33k, RMIN = 56k, VTPH = 0.0V, CLO,HO = 1000pF, TA = 25oC unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions Preheat Characteristics ICPH VCPHIGN VCPHCLMP IIPH VCSTH VCPHFLT CPH pin charging current CPH pin ignition mode threshold voltage CPH pin clamp voltage IPH pin DC source current Peak preheat current regulation threshold CPH pin voltage during UVLO or fault — — — — — — 1.3 5.0 10 25.0 0.7 0.0 — — — — — — µA V µA V V IIPH = 1/RFMIN VCSTH =(IIPH) x (RIPH) SD = 5V, or CS = 2V, or Tj > TSD Ignition Characteristics VCSTH Peak over current threshold — 1.6 — V VCPH < 5V Protection Characteristics VSDTH+ VVDCTH+ VSDHYS VVDCHYS VSDCLMP VCSTH TSD Rising shutdown pin threshold voltage Rising VDC pin threshold voltage SD threshold hysteresis VDC threshold hysteresis SD pin clamp voltage Peak over-current latch threshold voltage Thermal shutdown junction temperature — — — — — — — 2.0 5.1 150 2.1 7.6 1.6 165 — — — — — — — V mV V oC ISD = 100mA VCPH > 5.1V Phase Control VCSTHZX RFB tBlank Zero-crossing threshold voltage Phase control FB resistor (Internal) Zero-crossing internal blank time — — — 0.0 5.7 400 — — — V kΩ ns Dimming Interface VDIMOFF VDIM VMINMIN VMINMAX VDIMTH VDIMTH DIM pin offset voltage DIM pin input voltage range DIM minimum reference voltage (MIN pin) DIM maximum reference voltage (MIN pin) DIM mode VCO Threshold (IR2159) DIM mode VCO Threshold (IR21591) — 0.0 — — — — 0.5 — 1.0 3.0 0.5 1.1 — 5.0 — — 3.0 3.0 V VDIM= 5V VDIM= 0V Minimum Frequency Setting VFMIN VFMINFLT FMIN pin voltage during normal operation FMIN pin voltage during fault mode — — 5.1 0.0 — — V V SD = 5V, or CS = 2V, or Tj > TSD www.irf.com 5 IR2159/IR21591 (S) Block Diagram 60uA VCC VCO 2 1uA RFB 15uA ICT VDIMTH 14 LEVEL SHIFT PULSE FILTER & LATCH VB HO VS 16 VDC 1 1.3uA 10 CYCLES IGNITION COUNTER S R Q Q ERR 15 CPH 3 REF CT 13 5.1V S R1 R2 Q Q T R Q Q 15.6V VCC LO COM 10V 11 ICT S R Q Q 1.0V 12 IDT+I CT CT DIM 4 5.1V 400ns DELAY IDIM FB MAX 5 4/RFMIN Q Q S R 10 CS MIN 6 IDIM /5 IFMIN 3V S R 5.1V Q Q FMIN 7 5.1V 1/RFMIN 1.6V 1 UNDERVOLTAGE DETECT OVERTEMP DETECT 2.0V 9 7.6V SD IPH 8 0 Lead Assignments & Definitions Pin Assignments VDC VCO CPH DIM MAX MIN FMIN IPH 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Pin # Symbol HO VS VB VCC COM LO CS SD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDC VCO CPH DIM MAX MIN FMIN IPH SD CS LO COM VCC VB VS HO Description Line input voltage detection Voltage controlled oscillator Input Preheat timing input 0.5 to 5VDC dimming control input Maximum lamp power setting Minimum lamp power setting Minimum frequency setting Peak preheat current reference Shutdown input Current sensing input Low-side gate driver output IC power & signal ground Logic & low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output 6 www.irf.com IR2159/IR21591 (S) State Diagram Power Turned On UVLO Mode 1 /2-Bridge Off IQCC ≅ 200µA CPH = 0V Oscillator Off VCC > 12.5V (UV+) and VDC > 5.1V (Bus OK) and SD < 1.7V (Lamp OK) and TJ < 175C (Tjmax ) VCC < 10.9V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Power Down) or SD > 2.0V (Lamp Fault or Lamp Removal) SD > 2.0V (Lamp Removal) or VCC < 10.9V (Power Turned Off) FAULT Mode Fault Latch Set 1 /2-Bridge Off IQCC ≅ 240µA CPH = 0V VCC = 15.6V Oscillator Off TJ > 175C (OverTemperature) PREHEAT Mode 1 /2-Bridge Oscillator On VCSPK =VIPH (Peak Current Control) CPH Charging @ I PH = 1µA DIM = Open Circuit Over-Current Disabled CS > VCSTH (1.6V) (Failure to Strike Lamp or Hard Switching) or TJ > 175C (Over-Temperature) CPH > 5.1V (End of PREHEAT Mode) IGNITION Mode fPH ramps to f MIN CPH Charging @ I PH = 1µA DIM = Open Circuit Over-Current Enabled CS > VCSTH (1.6V) (Over-Current or Hard Switching) or TJ > 175C (Over-Temperature) VCO < V DIMTH (End of IGNITION Mode) DIM Mode Phase CS = Phase REF DIM = CPH Over-Current Enabled www.irf.com 7 IR2159/IR21591 (S) Timing Diagram Non-strike fault condition with lamp exchange VCC 15.6V UVLO+ UVLO- VDC VDCTH+ VDCTH- CPH 5.1V VDIM VCO 5V f SD 5V HO LO CS 1.6V VIPH IGN IGN UVLO PH FLT SD PH DIM UVLO 8 www.irf.com IR2159/IR21591 (S) External Components Selection Procedure (Note: Please refer to "Typical Connection" diagram, page 1) BEGIN Calculate R PULL-UP RPULL −UP = VACTURN −ON I QCCUV Calculate R VDC Set RVAC and RVDC such that the voltage on pin VDC will exceed 5.1 volts at the desired line turn-on voltage. RVDC 5.1    VAC TURN − ON  = 5.1 1− VACTURN −ON   RVAC   RVDC VAC TURN-ON The minimun operating frequency must be lower than f100% of fIGN (whichever is lower). RFMIN also programs IMIN and IIPH, so RFMIN must be set first. RCS sets the maximum ignition current which corresponds to the maximum ignition voltage across the lamp. Select R FMIN Use Graph 5 or Graph 6 Calculate R CS RCS = 1. 6 I IGN PK RFMIN fMIN RCS IIGN VIGN Select & Calculate R IPH The voltage at pin IPH is the reference for amplitude current control during preheat mode. RIPH must be set after RFMIN . Use Graph 8 to find I IPH, then calculate R IPH: RIPH = I PH PK ⋅ RCS I IPH RIPH IPH VPH During preheat, an internal 1.3 µA current source at pin CPH charges external capacitor CCPH. Preheat mode ends when VCPH exceeds 5.1 volts. Calculate C CPH CCPH = (2.6e − 7 ) t PH CCPH tPH Calculate R MIN RMIN sets the lower phase boundary corresponding to minimum lamp power when VDIM = 0 volts. RMIN must be set after RFMIN . Find I MIN (Graph 7) Calculate ϕMIN (Equations 8 & 9) Find V MIN (Graph 9) RMIN = VMIN I MIN RMIN ϕMIN PLAMP RMAX sets the upper phase boundary corresponding to maximum lamp power when VDIM = 5 volts. RMAX must be set after RFMIN and RMIN. Calculate R MAX Use Equation 15 RMAX ϕMAX PLAMP www.irf.com 9 IR2159/IR21591 (S) Characteristic Curves 125 230 105 Frequency (KHz) Frequency (KHz) IN= 10 K 190 RF MI N= 10 K 85 RF M 150 RF N MI =1 6K 65 RF MI N= K 16 0K M RF 45 7K =2 9K RF =3 IN M RF N MI IN =2 110 70 0K =2 IN 7K M RF N=2 I M 9K RF =3 IN 8K M6 RF IN= M RF 25 0 1 2 3 V VCO (V) 4 5 30 0 1 2 3 4 5 Graph 1. Frequency vs VVCO (IR2159) Graph 2. Frequency vs VVCO (IR21591) 125 230 VVCO=5V 105 Frequency (KHz) 190 Frequency (KHz) VVCO=5V 85 150 65 110 VVCO=0.5V 45 VVCO=1.1V 70 VVCO=0V VVCO=0V 30 34 38 25 10 14 18 22 26 30 10 20 30 40 50 60 70 R F MIN K Ω R F MIN K Ω Graph 3. Frequency vs RFMIN (IR2159) Graph 4. Frequency vs RFMIN (IR21591) 10 www.irf.com IR2159/IR21591 (S) 90 85 80 170 160 150 Frequency (KHz) 140 130 120 110 100 90 80 10 14 18 22 26 30 34 38 VVCO=1.1V 75 Frequency (KHz) 70 65 60 55 50 45 40 35 VVCO=0.5V 10 14 18 22 26 30 34 38 RFMIN K Ω Graph 5. Frequency vs RFMIN (IR2159) RFMIN KΩ Graph 6. Frequency vs RFMIN (IR21591) 450 400 350 300 IMIN ( A) 250 200 150 100 50 10 20 30 40 RFMIN (KΩ) 50 60 70 110 100 90 80 IIPH ( A) 70 60 50 40 30 20 10 10 20 30 40 RFMIN (KΩ) 50 60 70 Graph 7. IMIN vs RFMIN (IR2159/IR21591) Graph 8. I IPH vs RFMIN (IR2159/IR21591) www.irf.com 11 IR2159/IR21591 (S) 0 30 -15 25 39K IN= RFM 3K IN=3 RFM -30 IIVSI/VVSI RMIN (KΩ) 20 -45 K IN=27 RFM 15 -60 =20K RFMIN 16K RFMIN= -75 10 RFMIN=10K 5 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 -90 2 2.2 2.4 2.6 2.8 3 V MIN (V) VMIN (V) Graph 9. ϕ IIVS/VVSI vs VMIN (IR2159/IR21591) Graph 10. R MIN vs VMIN 3 2.5 2 ICPH µA IMIN µA 1.5 1 0.5 0 -25 0 25 50 75 100 125 150 140 130 120 110 100 90 -25 0 25 50 75 100 125 Temperature °C Graph 11. ICPH vs Temperature (IR2159/IR21591) Temperature °C Graph 12. IMIN vs Temperature (IR2159/IR21591) 12 www.irf.com IR2159/IR21591 (S) 40 6 36 5.6 IIPH (µA) 28 VFMIN (V) -25 0 25 50 75 100 125 32 5.2 4.8 24 4.4 20 4 -25 0 25 50 75 100 125 Temperature °C Temperature °C Graph 13. IIPH vs Temperature (IR2159/IR21591) Graph 14. VFMIN vs Temperature (IR2159/IR21591) 55 110 105 IR21591 50 IR21591 Frequency (KHz) Frequency (KHz) 45 100 95 90 85 80 75 70 40 35 30 65 IR2159 60 55 100 125 -25 0 25 IR2159 25 -25 0 25 50 75 50 75 100 125 Temperature °C Temperature °C Graph 15. Frequency vs Temperature VVCO= 0V (IR2159/IR21591) Graph 16. Frequency vs Temperature VVCO= 2V (IR2159/IR21591) www.irf.com 13 IR2159/IR21591 (S) 3 2.5 Dead Time Sec 2 1.5 IR2159 IR21591 1 0.5 0 -25 0 25 50 75 100 125 Temperature °C Graph 17. Dead Time vs Temperature (IR2159/IR21591) 14 www.irf.com IR2159/IR21591 (S) Functional Description PH/IGN 400 20 350 Phase Control To understand phase control, a simplified model for the ballast output stage is used (Figure 1). The lamp and filaments are replaced with resistors, with the lamp inserted between the filament resistors (R1, R2, R3 and R4). R1 R2 10% 10 300 250 200 50% Magnitude [dB] 0 100% 150 100 -10 PH/IGN 10% 50 0 -50 -100 5 10 15 20 25 30 35 40 45 50 Fr equency [kHz] -20 50% 100% -30 L Vin Rlamp C Figure 2, Typical output stage transfer function for different lamp power levels. R3 R4 Figure 1, Dimming ballast output stage. During preheat and ignition (Figure 2), the circuit is a high-Q series LC with a strong input current to input voltage phase inversion from +90 to -90 degrees at the resonance frequency. For operating frequencies slightly above resonance and higher, the phase is fixed at -90 degrees for the duration of preheat and ignition. During dimming, the circuit is an L in series with a parallel R and C, with a weak phase inversion at high lamp power and a strong phase inversion at low lamp power. In the time domain (Figure 3), the input current is shifted -90 degrees from the input half-bridge voltage during preheat and ignition, and somewhere between 0 and -90 degrees after ignition during running. Zero phase-shift corresponds to maximum power Vin Iin ph/ign Iin run 0 t nrun nph/ign Figure 3, Typical ballast output stage waveforms. When the phase is calculated and plotted versus lamp power (Figure 4), the result is a linear dimming curve, even down to ultra-low light levels where the resistance of the lamp can change by orders of magnitude. www.irf.com Phase [deg] 15 IR2159/IR21591 (S) -60.0 -65.0 -70.0 Phase [degrees] -75.0 -80.0 -85.0 The start-up capacitor (C1) is charged by current through resistor (R1) minus the start-up current drawn by the IC. This resistor is typically chosen to provide 2X the maximum start-up current at low line to guarantee start-up under the worst case condition. Once the capacitor voltage reaches the start-up threshold, and, the voltage on pin VDC is above 5.1V (see Brown-out Protection), the IC turns on and HO and LO begin to oscillate. The capacitor begins to discharge due to the increase in IC operating current (Figure 6). V C1 0 5 10 15 Lamp Pow er [Watts] 20 25 30 -90.0 C1 DISCHARGE V UVLO+ INTERNAL CLAMP VOLTAGE Figure 4, Lamp power vs. phase of output stage. VHYST V UVLO- Under-voltage Lock-Out (UVLO) The IR2159 undervoltage lock-out is designed to maintain an ultra low quiescent current of less than 200uA, while guaranteeing the IC is fully functional before the high and low side output drivers are activated. Figure 5 shows an efficient supply voltage using the start-up current of the IR2159 together with a charge pump from the ballast output stage (R1, C1, C2, D1 and D2). VBUS(+) Rectified AC Line R3 VDC 1 16 HO R1 Q1 Half-Bridge Output C2 D3 C1 D1 DISCHARGE TIME CHARGE PUMP OUTPUT R1 & C1 TIME CONSTANT t Figure 6, Start-up capacitor (C1) voltage. 15 VS 14 VB C3 13 VCC 12 CVDC RVDC COM 11 LO Q2 D2 RCS V BUS(-) Figure 5, Typical application of start-up circuitry. During the discharge cycle, the rectified current from the charge pump charges the capacitor above the minimum operating voltage of the device and the charge pump and internal 15.6V zener clamp of the IC take over as the supply voltage. The start-up capacitor and snubber capacitor must be selected such that worst case IC conditions are satisfied. A bootstrap diode (D3) and supply capacitor (C3) comprise the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During UVLO, the high and low side driver outputs are low, pin VCO is pulled-up internally to 5V resetting the starting frequency to the maximum, and pin CPH is short-circuited internally to COM resetting the preheat time. www.irf.com 16 IR2159/IR21591 (S) Brown-out Protection VBUS(+) In addition to the voltage on VCC being above the start-up threshold, pin VDC must also be above 5.1V for HO and LO to begin oscillating. A voltage divider (R3,RVDC) from the rectified AC line connected to pin VDC measures the rectified AC line input voltage to the ballast and programs the turn-on and turn-off line voltages. A filter capacitor (CVDC) is also connected to pin VDC that must be chosen such that the ripple is low enough and the lower turn-off threshold of 3V is not crossed during normal line conditions. This detection is necessary due to the possibility of the lamp extinguishing during low-line conditions before the IC is properly reset. Should a brownout occur, the DC bus can drop to a level below the minimum required for the tank circuit to maintain the necessary lamp voltage. This detection will insure a clean turn-off before the DC bus drops too low and properly resets the IC to the preheat mode when the line returns. Preheat (PH) The IR2159 enters preheat mode when VCC exceeds the UVLO+ threshold and VDC exceeds 5.1V. HO and LO begin to oscillate at the maximum operating frequency with 50% duty cycle and at the internally set dead-time of 2us. Pin CPH is disconnected from COM and an internal 1uA current source (Figure 7) charges the external timing capacitor on CPH linearly. 60uA VCO 2 CVCO 1uA HO VCO 16 Q2 Half Bridge Driver 1uA VS 15 Half Bridge Output ILOAD CPH 3 CCPH 7.6V PH LOGIC IFMIN LO 11 Q2 FMIN RFMIN 7 5.1V CS 10 RCS 1/RFMIN COM 12 IPH 8 RIPH IR2159 Load Return VBUS(-) Figure 7, IR2159 preheat circuitry. An internal 1uA current source slowly discharges the external capacitor on pin VCO and the voltage on pin VCO begins to decrease. This decreases the frequency, which, for operating frequencies above resonance, increases the load current. When the peak voltage measured on pin CS, produced by a portion of the load current flowing through an external sense resistor (RCS), exceeds the voltage level on pin IPH, a 60uA internal current source is connected to pin VCO and the capacitor charges (Figure 8). This forces the frequency to increase and the load current to decrease. When the voltage on pin CS decreases below IPH, the 60uA current source is disconnected and the frequency decreases again. www.irf.com 17 IR2159/IR21591 (S) HO LO VS VBUS(+) VCO 2 CVCO 1uA HO VCO 16 Q2 VR C S V IPH t 1uA CPH 3 CCPH 7.6V PH LOGIC Half Bridge Driver VS 15 Half Bridge Output ILOAD LO 11 DIM INTERFACE Q2 t 0.5 to 5V RDIM DIM 4 FAULT LOGIC 1.6V CS 10 RCS I CVCO 60uA PHASE CONTROL COM 12 IR2159 Load Return VBUS(-) -1uA t Figure 9, IR2159 ignition circuitry. VCVCO t Figure 8, Peak load current regulation timing diagram. This feedback keeps the peak preheat current regulated to the user-programmable setting on pin IPH for the duration of the preheat time. An internal current source connected to an external resistor on pin IPH sets a voltage reference for the peak pre-heat current. The pre-heat time continues until the voltage on pin CPH exceeds 5V. Ignition (IGN) The IR2159 enters ignition mode when the voltage on pin CPH exceeds 5V. The peak current regulation reference voltage is disconnected from the user-programmable setting on pin IPH and is connected to a higher internal threshold of 1.6V (Figure 9). 18 The ignition ramp is then initiated as the capacitor on pin VCO discharges linearly through an internal 1uA current source. The frequency decreases linearly towards the resonance frequency of the high-Q ballast output stage, causing the lamp voltage and load current to increase (Figure 10). The frequency continues to decrease until the lamp ignites or the current limit of the IR2159 is reached. If the current limit is reached, the IR2159 enters FAULT mode. The 1.6V threshold together with the external current sensing resistor on pin CS determine the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs or IGBTs, and, the resonant inductor must not saturate at any time. Should the lamp ignite, the frequency continues to decrease until the voltage on pin VCO reaches VDIMTH, corresponding to the minimum operating frequency set by the external resistor on pin FMIN, www.irf.com IR2159/IR21591 (S) and the IR2159 enters DIM mode and the phase control loop is closed. down smoothly to the user setting. Should the ignition-to-dim time be too fast, however, the loop can respond faster than the ionization constant of the lamp (milliseconds) causing the VCO to over-shoot. This can result in a frequency that is higher than the minimum brightness frequency and can extinguish the lamp. The capacitor on pin CPH serves multiple functions by setting the preheat time, the travel rate just after ignition (together with resistor RDIM), and, serving as a filter capacitor on pin DIM during dimming to increase high-frequency noise immunity and minimize component count. Dimming (DIM) t V CPH 5.1V R DIM & CTPH TIME CONSTANT VDIM t VVCO IGN-TO-DIM TIME PH IGN DIM Figure 10, IR2159 ignition timing diagram. For a reliable ignition with minimal start-up flash, the resistor on FMIN should be set to 5kHz lower than the ignition frequency or the 100% brightness dimming frequency, whichever is lower. Ignition-to-Dim (IGN-to-DIM) When the VCO decreases below VDIMTH, the IR2159 enters dim mode. The phase control loop is closed and the phase of the load current is regulated against the user control input on pin DIM. To control the rate at which the dim setting changes from maximum brightness to the user setting (IGN-TO-DIM time, Figure 10), pin DIM is connected internally to pin CPH when the IR2159 enters DIM mode. The resistor on pin DIM (RDIM) discharges the capacitor on pin CPH down to the user dim setting. The resistor can be selected for a fast time constant to minimize the amount of flash visible over the lamp just after ignition, or, a long time constant such that the brightness ramps www.irf.com To regulate lamp power, the error between the reference phase and the phase of the output stage current forces the VCO to steer the frequency in the proper direction, as determined by the transfer function of the output stage, such that the error is forced to zero. An internal 15uA current source is connected to pin VCO during dimming mode (Figure 11) to discharge the VCO capacitor and decrease the frequency towards lock. VBUS(+) IR2159 VCC VCO 2 RFB HO VCO 16 Q2 16uA CVCO Half Bridge Driver CPH 3 VS 15 Half Bridge Output ILOAD LO 7.6V DIM INTERFACE CCPH 0.5 to 5V RDIM RMAX RMIN 11 Q2 DIM 4 MAX 5 FAULT LOGIC 1.6V CS 10 RCS MIN 6 PHASE CONTROL COM 12 Load Return VBUS(-) Figure 11, IR2159 dimming circuitry. 19 IR2159/IR21591 (S) Once lock is achieved, the phase detector (PDET) outputs short pulses to an open-drain PMOS that charges the VCO capacitor through an internal resistor (RFB) each time an error pulse occurs (Figure 12). This action "nudges" the integrator at the input of the VCO to keep the phase of the output stage current exactly locked in phase with the reference. VCS V MIN 5V V CT R MAX R MIN 3V 1V DIM RANGE 0 0.5V V DIM USER SETTING 5V LO nREF t 0-90-180- n LO Figure 13, Dimming interface nREF nFB nERR VVCO t Figure 12, Phase control timing diagram. The charging time of CT from 1V to 5.1V determines the on-time of output gate drivers HO and LO and corresponds to -180 degrees of possible phase shift in load current (minus deadtime). For the 0 to -90 degree dim range, the voltage on pin MIN is bounded between 1V and 3V using pins MIN and MAX. An external resistor on pin MAX programs the minimum phase shift reference (maximum lamp power) corresponding to 5V on pin DIM, and an external resistor on pin MIN sets the maximum phase shift (minimum lamp power) corresponding to 0.5V on pin DIM. Current Sensing During dimming, the current sensing circuitry (Figure 14) detects over-current which can occur during hard-switching (see Fault section), and zero-crossing to measure the phase of the total load current. To reject any switching noise which can occur at the turn-on of the low-side MOSFET or IGBT, a digital current sense blanking circuit blanks out the signal from the zero-crossing www.irf.com The IR2159 includes a dimming interface for analog lamp power control. The DIM pin input requires a voltage in the range of 0.5 to 5VDC, with 5V corresponding to minimum phase shift (maximum lamp power). The output of the dim interface is the voltage on pin MIN, which is compared with the internal timing capacitor (CT) voltage to produce a frequency-independent digital reference phase (Figure 13). 20 IR2159/IR21591 (S) detection comparator for 400ns after LO goes 'high' (Figure 15). V CS Switching Noise VBUS (+) t IR2159 HO 16 Q2 LO Half Bridge Output ILOAD Half Bridge Driver VS 15 JB L A N K Dimming Range LO 11 Q2 FAULT LOGIC 1.6V CS 10 Figure 15, Current sense timing diagram. R1 RCS PHASE CONTROL 400ns BLANK 12 COM Load Return Fault Mode (FAULT) During dimming, the peak current regulation circuit active during preheat and ignition is disabled. Should non-zero voltage switching at the output of the half-bridge occur (Figure 18), high current spikes will result. A lamp filament failure, lamp end-of-life, lamp removal, or a deadtime shorter than what is required for commutation, can all cause hard-switching. LOAD REMOVAL VBUS (-) Figure 14, Current sensing circuitry. The internal blank time reduces the dimming range slightly (Figure 15) when operating at minimum phase shift (maximum lamp power). The external programming resistor on pin MAX must be selected such that the minimum phase shift is set a safe margin away from the blank time. A series resistor (R1) is required to limit the amount of current flowing out of pin CS when the voltage across RCS goes below -0.7V. A filter capacitor at pin CS may be required due to other possible asynchronous noise sources present in the ballast system. HO LO VS t VCS 1.6V t NORMAL OPERATION HARD SWITCHING FAULT Figure 18, hard-switching with latch off www.irf.com 21 IR2159/IR21591 (S) Should the peak voltage on pin CS exceed 1.6V at any time during dimming, the IR2159 enters FAULT mode and the high and low-side driver outputs, HO and LO, are both turned off . Cycling the supply voltage on VCC below or the voltage on pin SD will reset the IR2159 to preheat (PH) mode (see STATE DIAGRAM). Ballast Output Stage The components comprising the output stage are selected using a set of equations. Different ballast operating frequencies and their respective voltages and currents are calculated. The inductor and capacitor values are obtained using equations (2) through (7). The results of these equations reveal the location of each operating frequency and the corresponding voltages and currents. For a given L, C, DC bus voltage, and pre-heat current, the resulting voltage over the lamp during pre-heat is given as: 1 Ballast Design Lamp Requirements Before selecting component values for the ballast output stage and the programmable inputs of the IR2159, the following lamp requirements must first be defined: Variable V ph  2VDC  2 8 L 2  2 2VDC (2) =  I ph  − + π C π     I ph t ph V phmax Description Filament pre-heat current Filament pre-heat time Maximum lamp pre-heat voltage Lamp ignition voltage Lamp power at 100% brightness Lamp voltage at 100% brightness Lamp power at 1% brightness Lamp voltage at 1% brightness Minimum cathode heating current Units Arms s Vpp Vpp W Vpp W Vpp Arms The resulting operating frequency during pre-heat is given as: f ph = 2I ph Vign P% 100 πCVph [Hz] (3) V100% P% 1 The resulting operating frequency during ignition is given as: 4 V 1 + π DC Vign V1% I Cathmin Table I, Typical lamp requirements f ign = 1 2π LC [Hz] (4) The total load current during ignition is given as: Iign = f ign CVign 2π [App] (5) 22 www.irf.com IR2159/IR21591 (S) The operating frequency [Hz] at maximum lamp power is given as:  1 32P2  1 1 32P2 % − 2 100 +  − 2 100%  − f100% = 4 4 2π LC C V100%  LC C V100%  2  4V  1 −  DC  V π   100%  L2C2 2  4V  1−  DC  V π  2 22  1 32P  1 1 32P − 2 % +  − 2 %  −  2 %2  f% = 4 4 LC 2π LC C V%  LC C V%  2 (8) (6) ϕ% = 2 180 −1 V% 2P V2 3 % tan [( C − 2 L)2πf% − 4 % LC2π3 f%] 2P π V% P % % (9) The cathode heating current at minimum lamp power is given as: I Cath1% = V1% f1%πC 2 (7) With the lamp requirements defined, the L and C of the ballast output stage selected, and the minimum and maximum phase calculated, the component values for setting the programmable inputs of the IR2159 are obtained with the following equations: Design Constraints The inductor and capacitor values should be iterated until the following design constraints have been fulfilled (Table II). Design Constraint Reason RFMIN = ( 25e − 6) − ( f MIN − 10000) ⋅ (1e − 10) ( f MIN − 10000) ⋅ (2e − 14) [Ohms] (10) [Ohms] V ph < V phmax f ph − f ign > 5kHz I ign < I ignmax RCS = Ignition during preheat Production tolerances Inductor saturation Lamp extinguishing during dimming 2 ⋅ (1.6) I ign (11) (12) RIPH = RFMIN RCS I ph 2 C CPH = ( 2.6 E − 7)(t PH ) RFMIN  ϕ1%  1 −  4 45  [Ohms] I Cath1% ≥ I Cathmin [Farads] (13) Table II, Ballast design constraints IR2159 Programmable Inputs In order to program the MIN and MAX settings of the dimming interface, the phase of the output stage current at minimum and maximum lamp power must be calculated. This is obtained using the following equations: RMIN = [Ohms] (14) RMAX = 4 ⋅ RMIN RFMIN ⋅ RMIN ϕ  − R FMIN ⋅ 1 − 100 %  45   [Ohms] (15) 23 www.irf.com IR2159/IR21591 (S) This ballast design procedure has been summarized into the following 3 steps: Define Lamp Requirements Iterate L and C to fulfill constraints Calculate IR2159 Programmable Inputs Figure 19, Simplified Ballast Design Procedure Case outline 16 Lead PDIP 24 01-6015 01-3065 00 (MS-001A) www.irf.com IR2159/IR21591 (S) 16 -Lead SOIC (narrow body) 01-6018 01-3064 00 (MS-012AC) IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/27/2001 www.irf.com 25