IR21814PBF

Preliminary Data Sheet No. PD60030 rev.O IR2213(S) & (PbF) HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation • • • • • • • • Fully operational to +1200V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 12 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Outputs in phase with inputs Also available LEAD-FREE (PbF) Product Summary VOFFSET IO+/VOUT ton/off (typ.) Delay Matching 1200V max. 1.7A / 2A 12 - 20V 280 & 225 ns 30 ns Packages Description The IR2213(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary 16-Lead SOIC HVIC and latch immune CMOS technologies enable (wide body) ruggedized monolithic construction. Logic inputs are 14-Lead PDIP compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 1200 volts. Typical Connection HO V DD HIN SD LIN V SS V CC V DD HIN SD LIN V SS V CC COM LO VB VS up to 1200V TO LOAD (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR2213(S) & (PbF) Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA TJ TS TL Definition High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation @ TA ≤ +25°C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) (14 Lead PDIP) (16 Lead SOIC) (14 Lead PDIP) (16 Lead SOIC) Min. -0.3 V B - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 — — — — — — -55 — Max. 1225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 125 150 300 Units V V/ns W °C/W °C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VDD VSS VIN Definition High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Min. VS + 12 Note 1 VS 12 0 VSS + 3 -5 (Note 2) VSS Max. VS + 20 1200 VB 20 VCC VSS + 20 5 VDD Units V Note 1: Logic operational for VS of -5 to +1200V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD