IR2214SSPBF

Data Sheet No. PD60213 revG IR2114SSPbF/IR21141SSPbF IR2214SSPbF/IR22141SSPbF HALF-BRIDGE GATE DRIVER IC Features • • • • • • • • • Floating channel up to +600 V or +1200 V Soft over-current shutdown Synchronization signal to synchronize shutdown with the other phases Integrated desaturation detection circuit Two stage turn on output for di/dt control Separate pull-up/pull-down output drive pins Matched delay outputs Undervoltage lockout with hysteresis band LEAD-FREE Product Summary VOFFSET IO+/- (min) VOUT Deadtime matching (max) Deadtime (typ) Desat blanking time (typ) DSH, DSL input voltage threshold (typ) Soft shutdown time (typ) 600 V or 1200 V max. 1.0 A / 1.5 A 10.4 V – 20 V 75 ns 330 ns 3 µs 8.0 V 9.25 µs Description The IR211(4,41)/IR221(4,41) gate driver family is suited to drive a single half bridge in power switching applications. These drivers provide high gate driving capability (2 A source, 3 A sink) and require low quiescent current, which allows the use of bootstrap power supply techniques in medium power systems. These drivers feature full short circuit protection by means of power transistor desaturation detection and manage all half-bridge faults by smoothly turning off the desaturated transistor through the dedicated soft shutdown pin, therefore preventing over-voltages and reducing EM emissions. In multi-phase systems, the IR211(4,41)/ IR221(4,41) drivers communicate using a dedicated local network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase short circuits. The system controller may force shutdown or read device fault state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the control and power ground use dedicated pins enabling low-side emitter current sensing as well. Undervoltage conditions in floating and low voltage circuits are managed independently. Package 24-Lead SSOP Typical connection DC+ 15 V VCC VB HOP HON SSDH LIN IR2x14 DC BUS (Up to 1200 V) HIN uP, Control FAULT/SD FLT_CLR SY_FLT DSH VS Motor LOP LON SSDL DSL VSS COM DC- www.irf.com 1 IR211(4,41)/IR221(4,41)SSPbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units VS VB VHO VCC COM VLO VIN VFLT VDSH VDSL dVs/dt PD RthJA TJ TS TL High side offset voltage (IR2114 or IR21141) High side floating supply voltage (IR2214 or IR22141) High side floating output voltage (HOP, HON and SSDH) Low side and logic fixed supply voltage Power ground Low side output voltage (LOP, LON and SSDL) Logic input voltage (HIN, LIN and FLT_CLR) FAULT input/output voltage (FAULT/SD and SY_FLT) High side DS input voltage Low side DS input voltage Allowable offset voltage slew rate Package power dissipation @ TA ≤ 25 °C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) V B - 25 -0.3 -0.3 VS - 0.3 -0.3 VCC - 25 VCOM -0.3 VSS -0.3 VSS -0.3 VS -3 VCOM -3 — — — — -55 — VB + 0.3 625 1225 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VB + 0.3 VCC + 0.3 50 1.5 65 150 150 300 °C V/ns W °C/W V Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at a 15 V differential. Symbol VB VS VHO VLO VCC COM VIN VFLT VDSH VDSL TA Definition High side floating supply voltage (Note 1) High side floating supply offset voltage High side output voltage (HOP, HON and SSDH) Low side output voltage (LOP, LON and SSDL) Low side and logic fixed supply voltage (Note 1) Power ground Logic input voltage (HIN, LIN and FLT_CLR) Fault input/output voltage (FAULT/SD and SY_FLT) High side DS pin input voltage Low side DS pin input voltage Ambient temperature (IR2114 or IR21141) (IR2214 or IR22141) Min. VS + 11.5 Note 2 Note 2 VS VCOM 11.5 -5 VSS VSS VS - 2.0 VCOM - 2.0 -40 Max. VS + 20 600 1200 VS + 20 VCC 20 5 VCC VCC VB VCC 125 °C V Units Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached. Note 2: Logic operational for VS from VSS-5 V to VSS +600 V or 1200 V. Logic state held for VS from VSS -5 V to VSS-VBS. (Please refer to the Design Tip DT97-3 for more details). www.irf.com 2 IR211(4,41)/IR221(4,41)SSPbF Static Electrical Characteristics VCC = 15 V, VSS = COM = 0 V, VS = 600 V or 1200 V and TA = 25 °C unless otherwise specified. Pins: VCC, VSS, VB, VS Symbol VCCUV+ VCCUVVCCUVH VBSUV+ VBSUVVBSUVH ILK IQBS Definition VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis (VB-VS) supply undervoltage positive going threshold (VB-VS) supply undervoltage negative going threshold (VB-VS) supply undervoltage lockout hysteresis Offset supply leakage current Quiescent VBS supply current Min 9.3 8.7 — 9.3 8.7 — — — — Typ 10.2 9.3 0.9 10.2 9.3 0.9 — 400 0.7 Max Units 11.4 10.3 — 11.4 10.3 — 50 800 2.5 mA µA VB = VS = 600 V or 1200 V VIN = 0 V or 3.3 V (No load) V VS = 0 V, VS = 600 V or 1200 V Test Conditions IQCC Quiescent VCC supply current Note 1: Refer to Fig. 1 Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT Symbol VIH VIL VIHSS IIN+ IINLogic "1" input voltage Logic "0" input voltage Logic input hysteresis Logic “1” input bias current (HIN, LIN, FLTCLR) Logic “0” input bias current (FAULT/SD, SY_FLT) Logic “0” input bias current Logic “1” input bias current (FAULT/SD, SY_FLT) Definition Min 2.0 — 0.2 — 0 -1 -1 — — Typ — — 0.4 330 — — — 60 60 Max — 0.8 — — 1 0 0 — — µA VIN = 0 V Ω V Units Test Conditions VCC = VCCUVto 20 V VIN = 3.3 V RON,FLT FAULT/SD open drain resistance SY_FLT open drain resistance RON,SY Note 1: Refer to Figs. 2 & 3 PW≤ 7 µs Pins: DSL, DSH The active bias is present only the IR21141and IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS respectively for DSL and DSH. Symbol Definition Min Typ Max Units Test Conditions VDESAT+ VDESATVDSTH IDS+ IDSHigh desat input threshold voltage Low desat input threshold voltage Desat input voltage hysteresis High DSH or DSL input bias current 7.2 8.0 6.3 7.0 — — — 1.0 21 -20 8.8 7.7 — — — µA mA VDESAT = VCC or VBS VDESAT = 0 V VDESAT = (VCC or VBS) – 2 V V See Figs. 4,16 Low DSH or DSL input bias current DSH or DSL input bias current IDSB (IR21141 and IR22141 only) Note 1: Refer to Fig. 4 — -160 — www.irf.com 3 IR211(4,41)/IR221(4,41)SSPbF Pins: HOP, LOP Symbol VOH Definition High level output voltage, VB – VHOP or VCC –VLOP Min — Typ 40 Max Units Test Conditions 300 mV IO= 20 mA VHOP/LOP= 0 V, HIN or LIN = 1, PW≤ 200 ns, resistive load, see Fig. 8 A Output high second stage short circuit pulsed current VHOP/LOP= 0 V, HIN or LIN= 1, 400 ns ≤PW≤ 10 µs, resistive load, see Fig. 8 IO1+ Output high first stage short circuit pulsed current 1 2 — IO2+ 0.5 1 — Note 1: Refer to Fig. 5 Pins: HON, LON, SSDH, SSDL Symbol VOL RON,SSD IODefinition Low level output voltage, VHON or VLON Soft Shutdown on resistance (Note 1) Output low short circuit pulsed current Min — — 1.5 Typ 45 90 3 Max Units Test Conditions 300 — — mV Ω A IO= 20 mA PW≤ 7 µs VHOP/LOP = 15 V, HIN or LIN = 0, PW≤ 10 µs Note 1: SSD operation only Note 2: Refer to Fig. 6 www.irf.com 4 IR211(4,41)/IR221(4,41)SSPbF AC Electrical Characteristics VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified. Symbol ton toff tr tf ton1 tDESAT1 tDESAT2 tDESAT3 tDESAT4 tDS tSS tSY_FLT, DESAT1 Definition Turn on propagation delay Turn off propagation delay Turn on rise time (CLOAD=1 nF) Turn off fall time (CLOAD=1 nF) Turn on first stage duration time Min. 220 220 — — 120 Typ. 440 440 24 7 200 3300 — 3300 — — Max. Units 660 660 — — 280 4600 — 4600 — — ns Test Conditions VIN = 0 & 1, VS = 0 V to 600 V or 1200 V, HOP shorted to HON, LOP shorted to LON, Fig. 7 Fig. 8 VHIN= 1 V VDESAT = 15 V, Fig. 10 VLIN = 1 V VDESAT = 15 V, Fig. 10 Fig. 9 VDS=15 V, Fig. 9 VHIN = 1 V VDS = 15 V, Fig. 10 VLIN = 1 V VDESAT=15 V, Fig. 10 VHIN = VLIN = 1 V, VDESAT=15 V, Fig. 10 DSH to HO soft shutdown propagation delay at HO 2000 turn on DSH to HO soft shutdown propagation delay after blanking DSL to LO soft shutdown propagation delay at LO turn on DSL to LO soft shutdown propagation delay after blanking Soft shutdown minimum pulse width of desat Soft shutdown duration period DSH to SY_FLT propagation delay at HO turn on DSH to SY_FLT propagation delay after blanking DSL to SY_FLT propagation delay at LO turn on DSL to SY_FLT propagation delay after blanking DS blanking time at turn on 1050 2000 1050 1000 5700 — 1300 — 1050 — 9250 13500 3600 — 3050 — 3000 — — — — — tSY_FLT, DESAT2 tSY_FLT, DESAT3 tSY_FLT, DESAT4 tBL Deadtime/Delay Matching Characteristics DT MDT PDM Deadtime Deadtime matching, MDT=DTH-DTL Propagation delay matching, Max (ton, toff) – Min (ton, toff) — — — 330 — — — 75 75 Fig. 11 External DT = 0 s, Fig. 11 External DT > 500 ns, Fig. 7 www.irf.com 5 IR211(4,41)/IR221(4,41)SSPbF comparator VCC/VB UV internal signal HIN/LIN/ FLTCLR 10k schmitt trigger internal signal VCCUV/VBSUV VSS/VS VSS Figure 1: Undervoltage Diagram Figure 2: HIN, LIN and FLTCLR Diagram VCC/VBS FAULT/SD SY_FLT fault/hold internal signal 100k active bias comparator schmitt trigger RON hard/soft shutdown internal signal DSL/DSH VDESAT SSD 700k internal signal VSS COM/VS Figure 3: FAULT/SD and SY_FLT Diagram Figure 4: DSH and DSL Diagram 200ns oneshot VCC/VB LON/HON VOH on/off internal signal on/off internal signal SSDL/SSDH VOL RON,SSD LOP/HOP desat internal signal COM/VS Figure 5: HOP and LOP Diagram Figure 6: HON, LON, SSDH and SSDL Diagram www.irf.com 6 IR211(4,41)/IR221(4,41)SSPbF 3.3V HIN LIN t on 50% tr PW out HO (HOP=HON) LO (LOP=LON) 90% 10% Figure 7: Switching Time Waveforms PW in 50% t off tf 90% 10% Ton1 Io1+ Io2+ Figure 8: Output Source Current 3.3V HIN/LIN t DS DSH/DSL 8V 8V SSD Driver Enable t DESAT t SS HO/LO Figure 9: Soft Shutdown Timing Waveform www.irf.com 7 IR211(4,41)/IR221(4,41)SSPbF HIN 50% 50% LIN 50% DSH 8V 8V DSL 8V 8V SY_FLT t 50% SY_FLT,DESAT1 50% t 50% SY_FLT,DESAT3 50% tSY_FLT,DESAT2 tSY_FLT,DESAT4 FAULT/SD FLTCLR tDESAT1 10% tDESAT2 90% SoftShutdown Turn_Off propagation Delay 50% 50% 90% SoftShutdown 90% HON tBL Turn-On Propagation Delay tBL 10% tDESAT3 50% 90% SoftShutdown tDESAT4 50% 90% SoftShutdown 90% LON tBL Turn-On Propagation Delay tBL Figure 10: Desat Timing LIN HIN 50% 50% HO (HOP=HON) LO (LOP=LON) 50% DTH 50% DTL 50% MDT=DTH-DTL Figure 11: Internal Deadtime Timing 50% www.irf.com 8 IR211(4,41)/IR221(4,41)SSPbF Lead Assignments HIN LIN FLT_CLR SY_FLT FAULT/SD 1 24 DSH VB N.C. HOP HON 24-Lead SSOP VSS SSDL COM LON LOP VCC DSL 12 SSOP24 VS SSDH N.C. N.C. N.C. N.C. 13 N.C. Lead Definitions Symbol Description VCC VSS HIN LIN FAULT/SD SY_FLT FLT_CLR LOP LON DSL SSDL COM VB HOP HON DSH SSDH VS Low side gate driver supply Logic ground Logic input for high side gate driver outputs (HOP/HON) Logic input for low side gate driver outputs (LOP/LON) Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status. Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence is occurring. As an input, an active low signal freezes both output status. Fault clear active high input. Clears latched fault condition (see Fig. 17) Low side driver sourcing output Low side driver sinking output Low side IGBT desaturation protection input Low side soft shutdown Low side driver return High side gate driver floating supply High side driver sourcing output High side driver sinking output High side IGBT desaturation protection input High side soft shutdown High side floating supply return www.irf.com 9 IR211(4,41)/IR221(4,41)SSPbF VCC SCHMITT TRIGGER INPUT SHOOT THROUGH PREVENTION (DT) Deadtime INPUT HOLD LOGIC OUTPUT SHUTDOWN LOGIC VB on/off on/off (HS) LEVEL SHIFTERS HIN LIN on/off LATCH LOCAL DESAT PROTECTION soft shutdown di/dt control Driver HOP HON SSDH DSH on/off (LS) desat SOFT SHUTDOWN UV_VBS DETECT Hard ShutDown internal Hold VS UV_VCC DETECT UV_VCC DesatHS on/off SY_FLT FAULT/SD FLT_CLR SSD FAULT HOLD SD FAULT LOGIC managemend (See figure 14) DesatLS LOCAL DESAT PROTECTION SOFTSHUTDOWN soft shutdown di/dt control Driver LOP LON SSDL DSL VSS COM FUNCTIONAL BLOCK DIAGRAM Start-Up Sequence SY _F LT FAULT /SD HO=LO=0 IN FA U LT/S D ShutDown FL T_ CL R HI N/ L VCC UV_ FA D /S LT U VB V_ U S FAULT DESAT EVENT /LIN HIN UnderVoltage VCC HO=LO=0 UnderVoltage VBS HO=0, LO=LIN UV_VCC L _F SY HO/LO=1 Soft ShutDown L H/ DS C _ VC UV T FAU Freeze DS H/ L STATE DIAGRAM Stable State − FAULT − HO=LO=0 (Normal operation) − HO/LO=1 (Normal operation) − UNDERVOLTAGE VCC − SHUTDOWN (SD) − UNDERVOLTAGE VBS − FREEZE Temporary State − SOFT SHUTDOWN − START UP SEQUENCE System Variable − FLT_CLR − HIN/LIN − UV_VCC − UV_VBS − DSH/L − SY_FLT − FAULT/SD NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE 2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event happens in HIN. www.irf.com FA LT/S D UL T/ SD UV_VBS FLT SY_ 10 IR211(4,41)/IR221(4,41)SSPbF HO/LO Status 0 1 SSD LO/HO LOn-1/HOn-1 HOP/LOP HON/LON SSDH/SSDL HiZ 0 HiZ 1 HiZ HiZ HiZ HiZ 0 Output follows inputs (in=1->out=1, in=0->out=0) Output keeps previous status IR2214 Logic Table: Output Drivers Status Description INPUTS INPUT/OUTPUT ______ SY_FLT SSD: desat (out) HOLD: freezing (in) _________ FAULT/SD SD: shutdown (in) FAULT: diagnostic (out) Undervoltage Yes: V< UV threshold No : V> UV threshold X: don’t care VCC VBS OUTPUTS Operation Hin Lin FLT_CLR HO LO Shutdown Fault Clear Normal Operation Anti Shoot Through Soft Shutdown (entering) Soft Shutdown (finishing) Freeze Undervoltage X HIN 1 0 0 1 1 0 X X X X X X LIN 0 1 0 1 0 1 X X X LIN X X X NOTE1 0 (SD) (FAULT) 1 1 1 1 (SSD) (SSD) (SSD) (SSD) 1 1 (FAULT) (FAULT) 1 1 0 (FAULT) X No No No No No No No No No No No Yes X No No No No No No No No No No Yes X 0 HO 1 0 0 0 SSD 0 0 0 HOn-1 0 0 0 LO 0 1 0 0 0 SSD 0 0 LOn-1 LO 0 0 0 0 0 0 0 0 0 X X X 1 1 1 1 0 (HOLD) 1 1 NOTE 1: SY_FLT automatically resets after the SSD event is over and FLT_CLR is not required. In order to avoid the FLT_CLR conflicting with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active. www.irf.com 11 IR211(4,41)/IR221(4,41)SSPbF 1 Features Description 1.1 Start-Up Sequence At power supply start-up, it is recommended to keep the FLT_CLR pin active until the supply voltages are properly established. This prevents spurious diagnostic signals being generated. All protection functions are operating independently from the FLT_CLR status and the output driver status reflects the input commands. When the bootstrap supply topology is used for supplying the floating high side stage, the following startup sequence is recommended (see also Fig. 12): 1. 2. 3. 4. 5. Set VCC, Set FLT_CLR pin to HIGH level, Set LIN pin to HIGH level and charge the bootstrap capacitor, Release LIN pin to LOW level, Release FLT_CLR pin to LOW level. VCC FLT_CLR LIN 1.4 Fault Management The IR211(4,41)/ IR221(4,41) is able to manage supply failure (undervoltage lockout) and transistor desaturation (on both the low and high side switches). 1.4.1 Undervoltage (UV) The undervoltage protection function disables the driver’s output stage which prevents the power device from being driven when the input voltage is less than the undervoltage threshold. Both the low side (VCC supplied) and the floating side (VBS supplied) are controlled by a dedicate undervoltage function. An undervoltage event on the VCC pin (when VCC < UVVCC-) generates a diagnostic signal by forcing the FAULT/SD pin low (see FAULT/SD section and Fig. 14). This event disables both the low side and floating drivers and the diagnostic signal holds until the undervoltage condition is over. The fault condition is not latched and the FAULT/SD pin is released once VCC becomes higher than UVVCC+. The VBS undervoltage protection works by disabling only the floating driver. Undervoltage on VBS does not prevent the low side driver from activating its output nor does it generate diagnostic signals. The VBS undervoltage condition (VBS < UVVBS-) latches the high side output stage in the low state. VBS must exceed the UVVBS+ threshold to return the device to its normal operating mode. To turn on the floating driver, HIN must be reasserted high (rising edge event on HIN is required). LO Figure 12 Start-Up Sequence A minimum 15 µs LIN and FLT-CLR pulse is required. 1.4.2 Power Devices Desaturation Different causes can generate a power inverter failure (phase and/or rail supply short-circuit, overload conditions induced by the load, etc.). In all of these fault conditions, a large increase in current results in the IGBT. The IR211(4,41)/ IR221(4,41) fault detection circuit monitors the IGBT emitter to collector voltage (VCE) (an external high voltage diode is connected between the IGBT’s collector and the ICs DSH or DSL pins). A high current in the IGBT may cause the transistor to desaturate; this condition results in an increase of VCE. Once in desaturation, the current in the power transistor can be as high as 10 times the nominal current. Whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltage). The gate driver is able to control the transient condition by smoothly turning off the desaturated transistor with its integrated soft shutdown (SSD) protection. 1.2 Normal Operation Mode After the start-up sequence has completed, the device becomes fully operative (see grey blocks in the State Diagram). HIN and LIN produce driver outputs to switch accordingly, while the input logic monitors the input signals and deadtime (DT) prevent shoot-through events from occurring. 1.3 Shutdown The system controller can asynchronously command the Hard Shutdown (HSD) through the 3.3 V compatible CMOS I/O FAULT/SD pin. This event is not latched. In a multi-phase system, FAULT/SD signals are or-ed so the controller or one of the gate drivers can force the simultaneous shutdown of the other gate drivers through the same pin. 1.4.3 Desaturation Detection: DSH/L Function Figure 13 shows the structure of the desaturation sensing and soft shutdown block. This configuration is the same for both the high and low side output stages. www.irf.com 12 IR211(4,41)/IR221(4,41)SSPbF VB/Vcc PreDriver on/off sensing diode HOPH/L ONE SHOT (ton1) HONH/L tBL Blanking DesatHS/LS RDSH/L tss One Shot Ron,ss SSDH/L tDS filter desat comparator DSH/L VDESAT VS/COM Figure 13: High and Low Side Output Stage internal HOLD internal FAULT (hard shutdown) SY_FLT (external hold) FAULT/SD (external hard shutdown) Q Q SET S R DesatHS DesatLS UVCC CLR FLTCLR Figure 14: Fault Management Diagram The external sensing diode should have BV > 600 V or 1200 V and low stray capacitance (in order to minimize noise coupling and switching delays). The diode is biased by an internal pull-up resistor RDSH/L (equal to VCC/IDS- or VBS/IDS- for IR2114 or IR2214) or by a dedicated circuit (see the active-bias section for IR21141 and IR22141). When VCE increases, the voltage at the DSH or DSL pin increases too. Being internally biased to the local supply, the DSH/DSL voltage is automatically clamped. When DSH/DSL exceeds the VDESAT+ threshold, the comparator triggers (see Fig. 13). The comparator’s output is filtered in order to avoid false desaturation detection by externally induced noise; pulses shorter than tDS are filtered out. To avoid detecting a false desaturation event during IGBT turn on, the desaturation circuit is disabled by a blanking signal (TBL, see blanking block in Fig. 13). This time is the estimated maximum IGBT turn on time and must be not exceeded by proper gate resistance sizing. When the IGBT is not completely saturated after TBL, desaturation is detected and the driver will turn off. Eligible desaturation signals initiate the SSD sequence. While in SSD, the driver’s output goes to a high impedance state and the SSD pull-down is activated to turn off the IGBT through the SSDH/SSDL pin. The SY_FLT output pin (active low, see Fig. 14) reports the gate driver status during the SSD sequence (tSS). Once the SSD has finished, SY_FLT releases, and the gate driver generates a FAULT signal (see the FAULT/SD section) by activating the FAULT/SD pin. This generates a hard shutdown for both the high and low output stages (HO=LO=low). Each driver is latched low until the fault is cleared (see FLT_CLR). Figure 14 shows the fault management circuit. In this diagram DesatHS and DesatLS are two internal signals that come from the output stages (see Fig. 13). It must be noted that while in SSD, both the undervoltage fault and external SD are masked until the end of SSD. Desaturation protection is working independently by the other control pin and it is disabled only when the output status is off. www.irf.com 13 IR211(4,41)/IR221(4,41)SSPbF In the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see Fig. 19). In fact, a pull up resistor with a low resistance may result in a high current the significantly discharges the bootstrap capacitor. For that reason, the typical pull up resistor value is on the order of 100 kΩ. This is the value of the internal pull up. While the impedance of the DSH/DSL pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. In that case, relevant dV/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (DSH/DSL). This coupled noise may be easily reduced be using an active bias structure for the sensing diode. An active bias structure is available only for the IR21141 or IR22141 versions. The DSH/DSL pins present an active pull-up respectively to VB/VCC, and a pull-down respectively to VS/COM. The dedicated biasing circuit reduces the impedance on the DSH/DSL pin when the voltage exceeds the VDESAT threshold (see Fig. 16). This low impedance helps in rejecting the noise provided by the current injected by the parasitic capacitance. When the power transistor is fully on, the sensing diode is forward biased and the voltage at the DSH/DSL pin decreases. At this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in Fig. 16. RDSH/L FAULT VCC LIN HIN FLT_CLR VB HOP HON SSH VCC LIN HIN FLT_CLR VB HOP HON SSH VCC LIN HIN FLT_CLR SY_FLT VB HOP HON SSH IR2214 IR2214 SY_FLT SY_FLT VS VS IR2214 VSS DSH DSH DSH VS FAULT/SD LOP LON SSL DSL FAULT/SD LOP LON SSL DSL FAULT/SD LOP LON SSL DSL COM VSS COM VSS COM phase U phase V phase W Figure 15: IR2214 Used in a 3 Phase Application 1.4.4 Fault Management in Multi-Phase Systems In a system with two or more gate drivers the IR2214/1 devices must be connected as shown in Fig. 15. SY_FLT: The bi-directional SY_FLT pins communicate each other through a local network. The logic signal is active low. The device that detects the IGBT desaturation activates the SY_FLT, which is then read by the other gate drivers. When SY_FLT is active all the drivers hold their output state regardless of the input signals (HIN, LIN) they receive from the controller (freeze state). This feature is particularly important in phase-tophase short circuit where two IGBTs are involved; in fact, while one is softly shutting-down, the other must be prevented from hard shutdown to avoid exiting SSD. In the freeze state, the frozen drivers are not completely inactive because desaturation detection still takes the highest priority. SY_FLT communication has been designed for creating a local network between the drivers. There is no need to wire SY_FLT to the controller. The bi-directional FAULT/SD pins FAULT/SD: communicate with each other and with the system controller. The logic signal is active low. When low, the FAULT/SD signal commands the outputs to go off by hard shutdown. There are three events that can force FAULT/SD low: 1. 2. 3. Desaturation detection event: the FAULT/SD pin is latched low when SSD is over, and only a FLT_CLR signal can reset it, Undervoltage on VCC: the FAULT/SD pin is forced low and held until the undervoltage is active (not latched), FAULT/SD is externally driven low either from the controller or from another IR2x14/1 device. This event is not latched; therefore the FLT_CLR cannot disable it. Only when FAULT/SD becomes high the device returns to its normal operating mode. 100K ohm 100 ohm VDSH/L VDESAT+ VDESAT- Figure 16: RDSH/L Active Biasing 1.6 Output Stage The structure is shown in Fig. 13 and consists of two turn on stages and one turn off stage. When the driver turns on the IGBT (see Fig. 8), a first stage is activated while an additional stage is maintained in the active state for a limited time (ton1). This feature boosts the total driving capability in order to accommodate both a fast gate charge to the plateau voltage and dV/dt control in switching. At turn off, a single n-channel sinks up to 3 A (IO-) and offers a low impedance path to prevent the self-turn on due to the parasitic Miller capacitance in the power switch. 1.7 Timing and Logic State Diagrams Description The following figures show the input/output logic diagram. Figure 17 shows the SY_FLT and FAULT/SD signals as outputs, whereas Fig. 18 shows them as inputs. 1.5 Active Bias For the purpose of sensing the power transistor desaturation, the collector voltage is monitored (an external high voltage diode is connected between the IGBT’s collector and the IC’s DSH or DSL pin). The diode is normally biased by an internal pull up resistor connected to the local supply line (VB or VCC). When the transistor is “on” the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. www.irf.com 14 IR211(4,41)/IR221(4,41)SSPbF A B C D E F G H IN LIN DSH DSL SY_FLT FAULT/SD FLT_CLR HO(HOP/HON) LO(LOP/LON) Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output AB C D E F HIN LIN SY_FLT FAULT/SD FLT_CLR HO (HOP/HON) LO (LOP/LON) Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input Referred to the timing diagram of Fig. 17: A. When the input signals are on together the outputs go off (anti-shoot through), B. The HO signal is on and the high side IGBT desaturates, the HO turn off softly while the SY_FLT stays low. When SY_FLT goes high the FAULT/SD goes low. While in SSD, if LIN goes up, LO does not change (freeze), C. When FAULT/SD is latched low (see FAULT/SD section) FLT_CLR can disable it and the outputs go back to follow the inputs, D. The DSH goes high but this is not read because HO is off, E. The LO signal is on and the low side IGBT desaturates, the low side behaviour is the same as described in point B, F. The DSL goes high but this is not read as LO is off, G. As point A (anti-shoot through). Referred to the timing diagram Fig. 18: A. The device is in the hold state, regardless of input variations. The hold state results as SY_FLT is forced low externally, B. The device outputs go off by hard shutdown, externally commanded. A through B is the same sequence adopted by another IR2x14x device in SSD procedure. C. Externally driven low FAULT/SD (shutdown state) cannot be disabled by forcing FLT_CLR (see FAULT/SD section), D. The FAULT/SD is released and the outputs go back to follow the inputs, E. Externally driven low FAULT/SD: outputs go off by hard shutdown (like point B), F. As point A and B but for the low side output. www.irf.com 15 IR211(4,41)/IR221(4,41)SSPbF 2 Sizing Tips 2.1 Bootstrap Supply The VBS voltage provides the supply to the high side driver circuitry of the gate driver. This supply sits on top of the VS voltage and so it must be floating. The bootstrap method is used to generate the VBS supply and can be used with any of the IR211(4,41)/ IR221(4,41) drivers. The bootstrap supply is formed by a diode and a capacitor as connected in Fig. 19. bootstrap resistor Rboot bootstrap diode DC+ − − Charge required by the internal level shifters (QLS); typical 20 nC, − Bootstrap capacitor leakage current (ILK_CAP), − High side on time (THON). ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution). Then we have: VF VCC VCC VB QTOT = QG + Q LS + ( I LK _ GE + I QBS + VBS bootstrap capacitor VGE ILOAD HOP HON VS SSDH VCEon VFP + I LK + I LK _ DIODE + I LK _ CAP + I DS − ) ⋅ THON motor IR2214 The minimum size of bootstrap capacitor is: C BOOT min = QTOT ∆VBS COM An example follows using IR2214SS or IR22141SS: Figure 19: Bootstrap Supply Schematic This method has the advantage of being simple and low cost but may force some limitations on duty-cycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. a) using a 25 A @ 125 °C 1200 V IGBT (IRGP30B120KD): • • • • • • • • • IQBS = 800 µA (datasheet IR2214); ILK = 50 µA (see Static Electrical Characteristics); QLS = 20 nC (datasheet IRGP30B120KD); QG = 160 nC (datasheet IRGP30B120KD); ILK_GE = 100 nA (reverse recovery VBSUV − where VCC is the IC voltage supply, VF is bootstrap diode forward voltage, VCEon is emitter-collector voltage of low side IGBT, and VBSUV- is the high-side supply undervoltage negative going threshold. Now we must consider the contributing VBS to decrease: − − − − − − − the maximum voltage drop ∆VBS becomes ∆VBS ≤ VCC − VF − VGEmin − VCEon = = 15 V−1 V − 10.5 V − 3.1 V = 0.4 V And the bootstrap capacitor is: influencing factors IGBT turn on required gate charge (QG), IGBT gate-source leakage current (ILK_GE), Floating section quiescent current (IQBS), Floating section leakage current (ILK), Bootstrap diode leakage current (ILK_DIODE), Desat diode bias when on (IDS- ), CBOOT ≥ 290 nC = 725 nF 0.4 V NOTICE: VCC has been chosen to be 15 V. Some IGBTs may require a higher supply to work correctly with the bootstrap technique. Also VCC variations must be accounted in the above formulas. www.irf.com 16 IR211(4,41)/IR221(4,41)SSPbF 2.3 Some Important Considerations Voltage Ripple: There are three different cases to consider (refer to Fig. 19). ILOAD < 0 A; the load current flows in the low side IGBT (resulting in VCEon). minimize the amount of charge fed back from the bootstrap capacitor to VCC supply. 2.4 Gate Resistances The switching speed of the output transistor can be controlled by properly sizing the resistors controlling the turn-on and turn-off gate currents. The following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver (RDRp and RDRn). The example shown uses IGBT power transistors and Figure 20 shows the nomenclature used in the following paragraphs. In addition, Vge* indicates the plateau voltage, Qgc and Qge indicate the gate to collector and gate to emitter charge respectively. CRES IC VBS = VCC − VF − VCEon In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off, the Vs node is pushed up by the load current until the high side freewheeling diode is forwarded biased. ILOAD = 0 A; the IGBT is not loaded while being on and VCE can be neglected VBS = VCC − V F ILOAD > 0 A; the load current flows through the freewheeling diode VGE VBS = VCC − V F + VFP In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. To minimize the risk of undervoltage, the bootstrap capacitor should be sized according to the ILOAD< 0 A case. Bootstrap Resistor: A resistor (Rboot) is placed in series with the bootstrap diode (see Fig. 19) in order to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding 10 Ω to avoid increasing the VBS time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. Bootstrap Capacitor: For high THON designs where an electrolytic capacitor is used, its ESR must be considered. This parasitic resistance forms a voltage divider with Rboot, which generats a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint. t1,QGE VCE t2,QGC dV/dt IC 90% CRES VGE CRESon Vge* CRESoff 10% 10% t,Q tSW tDon tR Figure 20: Nomenclature 2.5 Sizing The Turn-On Gate Resistor Switching-Time: For the matters of the calculation included hereafter, the switching time tsw is defined as the time spent to reach the end of the plateau voltage (a total Qgc+Qge has been provided to the IGBT gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and Qgc, Vcc, Vge* (see Fig. 21): ESR ⋅ V ≤ 3V ESR + RBOOT CC A parallel combination of a small ceramic capacitor and a large electrolytic capacitor is normally the best compromise, the first capacitor posses a fast time constant and limits the dVBS/dt by reducing the equivalent resistance. The second capacitor provides a large capacitance to maintain the VBS voltage drop within the desired ∆VBS. Bootstrap Diode: The diode must have a BV > 600 V or 1200 V and a fast recovery time (trr < 100 ns) to I avg = and Qgc + Qge t sw RTOT = * Vcc − V ge I avg www.irf.com 17 IR211(4,41)/IR221(4,41)SSPbF Vcc/Vb RDRp HS Turning ON dV/dt Iavg CRES IGBT, the device may self turn on, causing large oscillation and relevant cross conduction. RGon COM/Vs RGoff CRESoff OFF Figure 21: RGon Sizing ON RDRn C IES where RTOT = RDRp + RGon Figure 22: RGoff Sizing: Current Path When Low Side is Off and High Side Turns On RGon = gate on-resistor RDRp = driver equivalent on-resistance When RGon > 7 Ω, RDRp is defined by The transfer function between the IGBT collector and the IGBT gate then becomes: RDRp Vcc Vcc  t SW   +   t − 1 when t SW > t on1 I I o 2+  on1   =  o1+ Vcc  when t SW ≤ t on1  I o1+  (IO1+ ,IO2+ and ton1 from “Static Electrical Characteristics”). Vge Vde = s ⋅ ( RGoff + RDRn ) ⋅ CRESoff 1 + s ⋅ ( RGoff + RDRn ) ⋅ (CRESoff + CIES ) 1 + RDRn ) ⋅ (CRESoff + CIES ) Which yields to a high pass filter with a pole at: 1/τ = ( RGoff Table 1 reports the gate resistance size for two commonly used IGBTs (calculation made using typical datasheet values and assuming VCC= 15 V). Output Voltage Slope: The turn-on gate resistor RGon can be sized to control the output slope (dVOUT/dt). While the output voltage has a nonlinear behaviour, the maximum output slope can be approximated by: As a result, when τ is faster than the collector rise time (to be verified after calculation) the transfer function can be approximated by: Vge Vde = s ⋅ ( RGoff + RDRn ) ⋅ CRESoff Vge = ( RGoff + RDRn ) ⋅ CRESoff ⋅ dVde dt in the I avg dVout = dt C RESoff inserting the expression yielding Iavg and rearranging: So that time domain. Then the condition: RTOT Vcc − Vge = dV C RESoff ⋅ out dt * Vth > Vge = (RGoff + RDRn ) ⋅ CRESoff Rearranging the equation yields: dVout dt must be verified to avoid spurious turn on. As an example, table 2 shows the sizing of gate resistance to get dVout/dt= 5 V/ns when using two popular IGBTs (typical datasheet values are used and VCC= 15 V is assumed). NOTICE: Turn on time must be lower than TBL to avoid improper desaturation detection and SSD triggering. RGoff < Vth CRESoff ⋅ dV dt − RDRn In any case, the worst condition for unwanted turn on is with very fast steps on the IGBT collector. In that case, the collector to gate transfer function can be approximated with the capacitor divider: 2.6 Sizing the Turn-Off Gate Resistor The worst case in sizing the turn-off resistor RGoff is when the collector of the IGBT in the off state is forced to commutate by an external event (e.g., the turn-on of the companion IGBT). In this case the dV/dt of the output node induces a parasitic current through CRESoff flowing in RGoff and RDRn (see Fig. 22). If the voltage drop at the gate exceeds the threshold voltage of the Vge = Vde ⋅ CRESoff (CRESoff + CIES ) which is driven only by IGBT characteristics. www.irf.com 18 IR211(4,41)/IR221(4,41)SSPbF As an example, table 3 reports RGoff (calculated with the above mentioned disequation) for two popular IGBTs to withstand dVout/dt = 5 V/ns. NOTICE: The above-described equations are intended to approximate a way to size the gate resistance. A more accurate sizing may provide more precise device and PCB (parasitic) modelling. IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19 nC 10 nC Qgc 82 nC 20 nC Vge* tsw Iavg Rtot RGon → std commercial value Tsw →420 ns →202 ns 9V 400 ns 0.25 A 24 Ω RTOT - RDRp = 12.7 Ω → 10 Ω 9V 200 ns 0.15 A 40 Ω RTOT - RDRp = 32.5 Ω → 33 Ω Table 1: tsw Driven RGon Sizing Vge* CRESoff Rtot RGon → std commercial value IGBT IRGP30B120K(D) IRG4PH30K(D) Qge 19 nC 10 nc Qgc dVout/dt →4.5 V/ns →5 V/ns 82 nC 9V 85 pF 14 Ω RTOT - RDRp = 6.5 Ω → 8.2 Ω 20 nC 9V 14 pF RTOT - RDRp = 78 Ω → 82 Ω 85 Ω Table 2: dVOUT/dt Driven RGon Sizing Vth(min) 4 CRESoff 85 pF RGoff RGoff ≤ 4 Ω RGoff ≤ 35 Ω IGBT IRGP30B120K(D) IRG4PH30K(D) 3 14 pF Table 3: RGoff Sizing www.irf.com 19 IR211(4,41)/IR221(4,41)SSPbF 3 PCB Layout Tips 3.1 Distance from High to Low Voltage The IR2x14/1 pin out maximizes the distance between floating (from DC- to DC+) and low voltage pins. It’s strongly recommended to place components tied to floating voltage on the high voltage side of device (VB, VS side) while the other components are placed on the opposite side. 3.5 Routing and Placement Example Figure 24 shows one of the possible layout solutions using a 3 layer PCB. This example takes into account all the previous considerations. Placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize the supply path loop and the gate drive loop. The bootstrap diode is placed under the device to have the cathode as close as possible to the bootstrap capacitor and the anode far from high voltage and close to VCC. 3.2 Ground Plane To minimize noise coupling, the ground plane must not be placed under or near the high voltage floating side. 3.3 Gate Drive Loops Current loops behave like antennas and are able to receive and transmit EM noise. In order to reduce the EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 23 shows the high and low side gate loops. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, increasing the possibility of self turn-on. For this reason, it is strongly recommended to place the three gate resistances close together and to minimize the loop area (see Fig. 23). VGH R2 R3 R4 IR2214 R5 R6 R7 C2 D2 DC+ D3 VGL Phase a) Top Layer C1 VEH D1 VCC VEL R1 IGC VB/ VCC H/LOP H/LON SSDH/L Gate Drive Loop gate resistance CGC b) Bottom Layer VGE VS/COM Figure 23: gate drive loop 3.4 Supply Capacitors The IR2x14x output stages are able to quickly turn on an IGBT, with up to 2 A of output current. The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance. c) Ground Plane Figure 24: layout example Information below refers to Fig. 24: Bootstrap section: R1, C1, D1 High side gate: R2, R3, R4 High side Desat: D2 Low side supply: C2 Low side gate: R5, R6, R7 Low side Desat: D3 www.irf.com 20 IR211(4,41)/IR221(4,41)SSPbF Figures 25-83 provide information on the experimental performance of the IR211(4,41)/ IR221(4,41)SSPbF HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). VCCUV+ Threshold (V) 10.30 10.25 10.20 10.15 10.10 10.05 10.00 9.95 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 25. VCCUV+ Threshold vs. Temperature Exp. VCCUV- Threshold (V) 9.60 9.55 9.50 9.45 9.40 9.35 9.30 9.25 9.20 9.15 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 26. VCCUV- Threshold vs. Temperature Exp. VBSUV+ Threshold Threshold (V) 10.45 10.40 10.35 10.30 10.25 10.20 10.15 10.10 10.05 10.00 -50 -25 0 25 50 o V BSUV- ThresholdThreshold (V) 9.70 9.65 9.60 9.55 9.50 9.45 9.40 9.35 9.30 9.25 Exp. Exp. 75 100 125 -50 -25 0 25 50 75 100 125 Temperature ( C) Figure 27. V BSUV+ Threshold vs. Temperature Temperature (oC) Figure 28. VBSUV- Threshold vs. Temperature 500 400 300 200 100 0 -50 -25 0 25 50 o Exp. VCC Quiescent Current (mA) VBS Quiescent Current (uA) 600 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 Exp. 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 29. VBS Quiescent Current vs. Temperature Temperature ( C) Figure 30. V CC Quiescent Current vs. Temperature www.irf.com 21 IR211(4,41)/IR221(4,41)SSPbF VIH Logic Input Voltage (V) 2.30 1.90 Exp. VIL Logic Input Voltage (V) 2.70 2.10 1.80 1.50 1.20 0.90 Exp. 1.50 1.10 -50 -25 0 25 50 o 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 31. VIH Logic Input Voltage vs. Temperature Temperature ( C) Figure 32. VIL Logic Input Voltage vs. Temperature VIHSS HIN Logic Input Hysteresis (V) 0.60 0.50 0.40 0.30 0.20 0.10 0.00 -50 -25 0 25 50 o Exp. LIN Logic "1" Input Voltage (V) 2.20 1.90 Exp. 1.60 1.30 1.00 -50 -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Figure 33. VIHSS HIN Logic Input Hysteresis vs. Temperature Temperature ( C) Figure 34. LIN Logic "1" Input Voltage vs. Temperature LIN Logic "0" Input Voltage (V) 1.60 1.30 Exp. VIHSS LIN Logic Input Hysteresis (V) 1.90 0.90 0.70 0.50 0.30 0.10 -50 -25 0 25 50 o Exp. 1.00 0.70 -50 -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Figure 35. LIN Logic "0" Input Voltage vs. Temperature Temperature ( C) Figure 36. VIHSS LIN Logic Input Hysteresis vs. Temperature www.irf.com 22 IR211(4,41)/IR221(4,41)SSPbF VIL FLTCLR Logic Input Hysteresis (V) VIH FLTCLR Logic Input Voltage (V) 2.30 2.00 1.70 1.40 1.10 -50 -25 0 25 50 o Exp. 1.70 1.40 Exp. 1.10 0.80 -50 -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Figure 37. VIH FLTCLR Logic Input Voltage vs. Temperature Temperature ( C) Figure 38. VIL FLTCLR Logic Input Voltage vs. Temperature VIHSS FLTCLR Logic Input Hysteresis (V) 0.60 0.50 0.40 0.30 0.20 -50 -25 0 25 50 o VIH SD Logic Input Voltage (V) 2.10 1.70 1.30 0.90 0.50 -50 -25 0 25 50 75 100 125 Temperature (oC) Exp. Exp. 75 100 125 Temperature ( C) Figure 39. VIHSS FLTCLR Logic Input Hysteresis vs. Temperature Figure 40. VIH SD Logic Input Voltage vs. Temperature VIHSS SD Logic Input Hysteresis (V) VIL SD Logic Input Voltage (V) 2.10 1.70 1.30 0.90 0.50 -50 -25 0 25 50 75 100 125 Temperature (oC) 0.60 0.50 0.40 0.30 0.20 -50 -25 0 25 50 o Exp. Exp. 75 100 125 Temperature ( C) Figure 42. VIHSS SD Logic Input Hysteresis vs. Temperature Figure 41. VIL SD Logic Input Voltage vs. Temperature www.irf.com 23 IR211(4,41)/IR221(4,41)SSPbF VIH SYFLT Logic Input Voltage (V) VIL SYFLT Logic Input Voltage (V) 2.40 2.00 Exp. 2.40 2.00 1.60 1.20 0.80 -50 -25 0 25 50 o Exp. 1.60 1.20 0.80 -50 -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Figure 43. VIH SYFLT Logic Input Voltage vs. Temperature Temperature ( C) Figure 44. VIL SYFLT Logic Input Voltage vs. Temperature VIHSS SYFLT Logic Input Hysteresis (V) 0.60 0.50 0.40 0.30 0.20 -50 -25 0 25 50 o 60 50 VOL LO (mV) Exp. 40 30 20 Exp. 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 45. VIHSS SYFLT Logic Input Hysteresis vs. Temperature Temperature ( C) Figure 46. VOL LO vs. Temperature 900 725 VOH LO (mV) VOL HO (mV) 550 375 200 -50 -25 0 25 50 o Exp. 65 55 45 35 25 75 100 125 -50 -25 0 25 50 o Exp. 75 100 125 Temperature ( C) Figure 47. VOH LO vs. Temperature Temperature ( C) Figure 48. VOL HO vs. Temperature www.irf.com 24 IR211(4,41)/IR221(4,41)SSPbF VDSH+ DSH Input Voltage (V) 900 725 VOH HO (mV) 9 8 7 6 5 -50 Exp. 550 375 200 -50 -25 0 25 50 o Exp. 75 100 125 -25 0 25 50 75 100 125 Temperature ( C) Figure 49. VOH HO vs. Temperature Temperature (oC) Figure 50. VDSH+ DSH Input Voltage vs. Temperature VDSH- DSH Input Voltage (V) VDSL+ DSL Input Voltage (V) 9 9 8 Exp. 8.30 7.60 Exp. 6.90 6.20 5.50 -50 8 7 -50 -25 0 25 50 o 75 100 125 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 51. VDSL+ DSL Input Voltage vs. Temperature Temperature ( C) Figure 52. VDSH- DSH Input Voltage vs. Temperature VDSL- DSL Input Voltage (V) 8.00 7.50 7.00 6.50 6.00 -50 -25 0 25 50 o Exp. FAULT/SD Open Drain Resistance (Ω) 90 75 60 45 Exp. 75 100 125 30 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 53. VDSL- DSL Input Voltage vs. Temperature Temperature ( C) Figure 54. FAULT/SD Open Drain Resistance vs. Temperature www.irf.com 25 IR211(4,41)/IR221(4,41)SSPbF SY_FLT Open Drain Resistance (Ω) DTL Off Deadtime (ns ) 130 105 80 55 30 -50 -25 0 25 50 o 490 430 370 Exp. Exp. 310 250 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 55. SY_FLT Open Drain Resistance vs. Temperature Temperature ( C) Figure 56. DTL Off Deadtime vs. Temperature TonH Propagation Delay (ns) DTH Off Deadtime (ns ) 490 430 Exp. 780 660 540 Exp. 370 310 250 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 57. DTH Off Deadtime vs. Temperature 420 300 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 58. TonH Propagation Delay vs. Temperature ToffH Propagation Delay (ns ) 780 TrH Turn On Rise Time (ns) 32 28 24 20 Exp. 660 540 420 300 -50 -25 0 25 50 o Exp. 16 12 75 100 125 -50 -25 0 25 50 75 100 125 Temperature ( C) Figure 59. ToffH Propagation Delay vs. Temperature Temperature (oC) Figure 60. TrH Turn On Rise Time vs. Temperature www.irf.com 26 IR211(4,41)/IR221(4,41)SSPbF TonL Propagation Delay (ns) TfH Turn Off Fall Time (ns) 18 15 12 9 6 -50 -25 0 25 50 o 780 660 540 Exp. Exp. 420 300 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 61. TfH Turn Off Fall Time vs. Temperature Temperature ( C) Figure 62. TonL Propagation Delay vs. Temperature ToffL Propagation Delay (ns ) 660 540 Exp. TrL Turn On Rise Time (ns ) 780 40 33 26 19 12 -50 Exp. 420 300 -50 -25 0 25 50 o 75 100 125 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 63. ToffL Propagation Delay vs. Temperature Temperature ( C) Figure 64. TrL Turn On Rise Time vs. Temperature TfL Turn Off Fall Time (ns) 20 16 6 5 tDSAT1 (us) -25 0 25 50 o Exp. 12 8 4 4 3 2 Exp. -50 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 65. TfL Turn Off Fall Time vs. Temperature Temperature ( C) Figure 66. tDSAT1 vs. Temperature www.irf.com 27 IR211(4,41)/IR221(4,41)SSPbF 3 3 t DSAT2 (us) 6 5 tDSAT3 (us) -25 0 25 50 o 2 Exp. 4 3 Exp. 2 1 -50 75 100 125 Temperature ( C) Figure 67. tDSAT2 vs. Temperature 2 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 68. tDSAT3 vs. Temperature 4.50 3.50 t DSAT4 (us) 17 14 t SSH (us) -25 0 25 50 o 2.50 Exp. 11 8 5 Exp. 1.50 0.50 -50 75 100 125 Temperature ( C) Figure 69. tDSAT4 vs. Temperature -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 70. tSSH vs. Temperature IO2+H SC Pulsed Current (A) 17 14 tSSL (us) Exp. 1.80 1.45 1.10 Exp. 11 8 5 -50 -25 0 25 50 o 0.75 0.40 75 100 125 -50 -25 0 25 50 75 100 125 Temperature ( C) Figure 71. tSSL vs. Temperature Temperature (oC) Figure 72. IO2+H SC Pulsed Current vs. Temperature www.irf.com 28 IR211(4,41)/IR221(4,41)SSPbF IO2+L SC Pulsed Current (A) IO-H SC Pulsed Current (A) 1.80 1.45 1.10 0.75 0.40 -50 -25 0 25 50 o Exp. 3.25 2.80 Exp. 2.35 1.90 1.45 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 73. IO2+L SC Pulsed Current vs. Temperature Temperature ( C) Figure 74. IO-H SC Pulsed Current vs. Temperature IO-L SC Pulsed Current (A) 3.50 3.05 2.60 2.15 1.70 1.25 -50 -25 0 25 50 o 900 700 t ON1H (ns) Exp. Exp. 500 300 100 75 100 125 -50 -25 0 25 50 75 100 125 Temperature ( C) Figure 75. IO-L SC Pulsed Current vs. Temperature Temperature (oC) Figure 76. tON1H vs. Temperature 500 400 tON1L (ns) 300 200 100 -50 -25 0 25 50 o Exp. IO1+H SC Pulsed Current (A) 3.00 2.50 2.00 Exp. 1.50 1.00 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Figure 77. tON1L vs. Temperature Temperature ( C) Figure 78. IO1+H SC Pulsed Current vs. Temperature www.irf.com 29 IR211(4,41)/IR221(4,41)SSPbF IO1+L SC Pulsed Current (ns) IHIN+ Logic "1" Input Bias Current (uA) 4 3 2 1 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Figure 79. IO1+L SC Pulsed Current vs. Temperature Exp. 900 700 500 300 100 -50 -25 0 25 50 o Exp. 75 100 125 Temperature ( C) Figure 80. IHIN+ Logic "1" Input Bias Current vs. Temperature IHIN- Logic "0" Input Bias Current (uA) -0.03 -0.08 -0.13 -0.18 -0.23 -0.28 -50 Exp. ILIN+ Logic "1" Input Bias Current (uA) 0.02 900 700 500 300 100 -50 -25 0 25 50 o Exp. -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Figure 81. IHIN- Logic "0" Input Bias Currentvs. Temperature Temperature ( C) Figure 82. ILIN+ Logic "1" Input Bias Current vs. Temperature ILIN- Logic "0" Input Bias Current (uA) 0.02 -0.03 -0.08 -0.13 -0.18 -0.23 -0.28 -50 -25 0 25 50 o Exp. 75 100 125 Temperature ( C) Figure 83. ILIN- Logic "0" Input Bias Current vs. Temperature www.irf.com 30 IR211(4,41)/IR221(4,41)SSPbF Case Outline www.irf.com 31 IR211(4,41)/IR221(4,41)SSPbF LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR 24SSOP:2000 units per reel Code A B C D E F G H Metric Min Max 11.90 12.10 3.90 4.10 15.70 16.30 7.40 7.60 8.30 8.50 8.50 8.70 1.50 n/a 1.50 1.60 Imperial Min Max 0.468 0.476 0.153 0.161 0.618 0.641 0.291 0.299 0.326 0.334 0.334 0.342 0.059 n/a 0.059 0.062 F D C E B A G H REEL DIMENSIONS FOR 24SSOP Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 22.40 G 18.50 21.10 H 16.40 18.40 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.881 0.728 0.830 0.645 0.724 www.irf.com 32 IR211(4,41)/IR221(4,41)SSPbF LEAD-FREE PART MARKING INFORMATION Part number Date code IRSxxxxx YWW? IR logo Pin 1 Identifier ? P ?XXXX Lot Code (Prod mode – 4 digit SPN code) MARKING CODE Lead Free Released Non-Lead Free Relased Assembly site code Per SCOP 200-002 ORDER INFORMATION 24-Lead SSOP IR2114SSPbF 24-Lead SSOP IR21141SSPbF 24-Lead SSOP IR2214SSPbF 24-Lead SSOP IR22141SSPbF 24-Lead SSOP Tape & Reel IR2114SSPbF 24-Lead SSOP Tape & Reel IR21141SSPbF 24-Lead SSOP Tape & Reel IR2214SSPbF 24-Lead SSOP Tape & Reel IR22141SSPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105 This part has been qualified per industrial level http://www.irf.com Data and specifications subject to change without notice. 5/18/2006 www.irf.com 33