IR3081A

IR3081A DATA SHEET XPHASETM VR 10 CONTROL IC DESCRIPTION The IR3081A Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to implement a complete VR 10 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3081A is intended for VRD 10 or VRM/EVRD 10 applications that use external VCCVID/VTT circuits. The IR3081A is functionally equivalent to the IR3081, but incorporates the following modifications: • Under Voltage Lockout start threshold increased from 9.1V to 9.7V (typical) and hysteresis increased from 200mV to 800mV (typical). • Hysteresis (52mV typical) added to the SS/DEL comparator to prevent Power Good output chatter. • Over current discharge current increased from 6uA to 40uA (typical) to reduce the over current delay time. • IIN pin precondition circuit added to disable current sharing in the phase ICs during soft start. FEATURES • • • • • • • • • • • • • • 6 bit VR 10 compatible VID with 0.5% overall system accuracy 1 to X phases operation with matching phase ICs Programmable Dynamic VID Slew Rate No Discharge of output capacitors during Dynamic VID step-down (can be disabled) +/-300mV Differential Remote Sense Programmable 150kHz to 1MHz oscillator Programmable VID Offset and Load Line output impedance Programmable Softstart Programmable Hiccup Over-Current Protection with Delay to prevent false triggering Simplified Powergood provides indication of proper operation and avoids false triggering Operates from 12V input with 9.1V Under-Voltage Lockout 6.8V/5mA Bias Regulator provides System Reference Voltage Enable Input Small thermally enhanced 28L MLPQ package Page 1 of 39 1/31/05 IR3081A APPLICATION CIRCUIT 12V RVCC 10 ohm CVCC 0. 1uF 25 27 23 28 26 24 22 POWERGOOD ENABLE CSS/ DEL EN ABLE SS/ D EL RM POUT PW R GD N/C LGN D VC C RMPOUT VBIAS VBI AS BBF B 21 20 19 18 17 16 15 RDRP1 CDRP RDRP RCP CCP 0. 1uF 1 OSCDS VI D 5 VI D 0 VI D 1 VI D 2 VI D 3 VID5 VID0 VID1 VID2 VID3 VID4 2 3 4 5 6 7 IR3081A CONTROL IC VOSN SROSC TR M 1 TR M 2 TR M 3 TR M 4 EAOU T FB VDRP II N OC SET VD AC EA 5 Wire Analog Bus to Phase ICs CCP1 VI D 4 ISHARE R OC SET CF B VDAC 8 9 10 11 12 13 ROSC 14 RVD AC RF B1 RF B CVD AC VOSENSE+ VOSENSE- Re mote Se nse ORDERING INFORMATION Device IR3081AMTR IR3081AM Order Quantity 3000 per reel 100 piece strips Page 2 of 39 1/31/05 IR3081A ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150oC Storage Temperature Range………………….-65oC to 150oC ESD Rating………………………………………HBM Class 1C JEDEC standard PIN # 1 2-7 8, 9, 11,12 10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME OSCDS VID0-5 TRM1-4 VOSNSROSC VDAC OCSET IIN VDRP FB EAOUT BBFB VBIAS VCC LGND RMPOUT SS/DEL PWRGD N/C ENABLE VMAX 20V 20V Do Not Connect 0.5V 20V 20V 20V 20V 20V 20V 10V 20V 20V 20V n/a 20V 20V 20V n/a 20V VMIN -0.3V -0.3V Do Not Connect -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V n/a -0.3V ISOURCE 1mA 10mA Do Not Connect 10mA 1mA 1mA 1mA 1mA 5mA 1mA 10mA 1mA 1mA 1mA 50mA 1mA 1mA 1mA n/a 1mA ISINK 1mA 10mA Do Not Connect 10mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 1mA 1mA 50mA 1mA 1mA 1mA 20mA n/a 1mA Page 3 of 39 1/31/05 IR3081A ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ VCC ≤ 14V, 0 oC ≤ TJ ≤ 100 oC PARAMETER VDAC Reference System Set-Point Accuracy TEST CONDITION -0.3V ≤ VOSNS- ≤ 0.3V, Connect FB to EAOUT, Measure V(EAOUT) – V(VOSNS-) deviation from Table 1. Applies to all VID codes. RROSC = 41.9kΩ RROSC = 41.9kΩ 0V ≤ VID0-5 ≤ VCC MIN TYP 0.5 MAX UNIT % Source Current Sink Current VID Input Threshold VID Input Bias Current Regulation Detect Comparator Input Offset Regulation Detect to EAOUT Delay BBFB to FB Bias Current Ratio VID 11111x Blanking Delay VID Step Down Detect Blanking Time VID Down BB Clamp Voltage VID Down BB Clamp Current Error Amplifier Input Offset Voltage 68 47 500 -5 -5 80 55 600 0 0 130 92 63 700 5 5 200 1.05 µA µA mV µA mV ns µA/µA ns µs 0.95 Measure Time till PWRGD drives low Measure from VID inputs to EAOUT Percent of VDAC voltage 70 3.5 -3 1.00 800 1.7 75 6.2 4 80 12 8 % mA mV FB Bias Current DC Gain Gain-Bandwidth Product Source Current Sink Current Max Voltage Min Voltage IIN Precondition Reset Comparator Threshold VDRP Buffer Amplifier Input Offset Voltage Bandwidth (-3dB) Slew Rate IIN Bias Current IIN Precondition Set Comparator Threshold Offset IIN Precondition Pull Down Resistance Page 4 of 39 Connect FB to EAOUT, and measure V(EAOUT) – V(DAC). Applies to all VID codes from table 1 and -0.3V ≤ VOSNS≤ 0.3V. Note 2 RROSC = 41.9kΩ Note 1 Note 1 VBIAS–VEAOUT (referenced to VBIAS) Normal operation or Fault mode -31 90 4 0.4 0.7 125 30 450 -29.5 100 7 0.6 1.2 250 100 600 -28 105 0.8 1.7 375 150 750 µA dB MHz mA mA mV mV mV V(VDRP) – V(IIN), 0.8V ≤ V(IIN) ≤ 5.5V Note 1 Note 1 Difference of preconditioning active voltage and SS/DEL-FB offset voltage SS/DEL=0V. -13 1 -2.0 350 7.5 -2 6 10 -0.75 600 15 6 mV MHz V/µs µA mV KΩ 0 850 22.5 1/31/05 IR3081A PARAMETER Oscillator Switching Frequency Peak Voltage (5V typical, measured as % of VBIAS) Valley Voltage (1V typical, measured as % of VBIAS) VBIAS Regulator Output Voltage Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Over Current Discharge Current Over Current Delay Time Delay Comparator Threshold Delay Comparator Threshold Delay Comparator Hysteresis Over-Current Comparator Input Offset Voltage OCSET Bias Current PWRGD Output Output Voltage Leakage Current Enable Input Threshold voltage Bias Current VCC Under-Voltage Lockout Start Threshold Stop Threshold Hysteresis General VCC Supply Current VOSNS- Current TEST CONDITION RROSC = 41.9kΩ RROSC = 41.9kΩ RROSC = 41.9kΩ MIN 255 70 11 TYP 300 71 14 MAX 345 74 16 UNIT kHz % % -5mA ≤ I(VBIAS) ≤ 0 6.5 -30 0.85 40 4 10 3.5 6.8 -15 1.3 70 6 11.5 3.8 40 250 65 115 52 0 -29.5 150 0 7.1 -6 1.5 100 9 13 4.0 V mA V µA µA µA/µA V uA us mV mV mV mV µA mV µA mV µA V V mV mA mA With FB = 0V, adjust V(SS/DEL) until EAOUT drives high CSS/DEL=0.1uF. Note 1 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling 150 35 85 32 350 95 145 72 10 -28 400 10 700 5 10.2 9.4 1200 14 -3.5 1V ≤ V(OCSET) ≤ 5V RROSC = 41.9kΩ I(PWRGD) = 4mA V(PWRGD) = 5.5V -10 -31 0V ≤ V(ENABLE) ≤ VCC 500 -5 9.2 8.4 600 8 -5.5 600 0 9.7 8.9 800 11 -4.5 Start – Stop -0.3V ≤ VOSNS- ≤ 0.3V, All VID Codes Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors Page 5 of 39 1/31/05 IR3081A PIN DESCRIPTION PIN# 1 2-7 8, 9, 11,12 10 13 14 PIN SYMBOL OSCDS VID0-5 TRM1-4 VOSNSROSC VDAC 15 OCSET 16 IIN 17 18 VDRP FB 19 20 EAOUT BBFB 21 22 23 24 25 VBIAS VCC LGND RMPOUT SS/DEL 26 27 28 PWRGD N/C ENABLE PIN DESCRIPTION Apply a voltage greater than VBIAS to disable the oscillator. Used during factory testing & trimming. Ground or leave open for normal operation. Inputs to VID D to A Converter Used for precision post-package trimming of the VDAC voltage. Do not make any connection to these pins. Remote Sense Input. Connect to ground at the Load. Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents Regulated voltage programmed by the VID inputs. Current Sensing and PWM operation are referenced to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Over-current protection can be disabled by connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as improper operation will occur). Current Sense input from the Phase IC(s). To ensure proper operation bias to at least 250mV (don’t float this pin). The pin is clamped to ground during the early stage of soft start to disable current sharing function in the phase ICs. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an external resistor connected to the converter output voltage at the load and an internal current source. Output of the Error Amplifier Input to the Regulation Detect Comparator. Connect to converter output voltage and VDRP pin through resistor network to program recovery from VID step-down. Connect to ground to disable Body BrakingTM during transition to a lower VID code. 6.8V/5mA Regulated output used as a system reference voltage for internal circuitry and the Phase ICs. Power for internal circuitry Local Ground and IC substrate connection Oscillator Output voltage. Used by Phase ICs to program Phase Delay Controls Converter Softstart, Power Good, and Over-Current Delay Timing. Connect an external capacitor to LGND to program the timing. An optional resistor can be added in series with the capacitor to reduce the over-current delay time. Open Collector output that drives low during Softstart and any external fault condition. Connect external pull-up. No internal connection Enable Input. A logic low applied to this pin puts the IC into Fault mode. Page 6 of 39 1/31/05 IR3081A SYSTEM THEORY OF OPERATION XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control converters of any phase number where flexibility facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing. There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. POW ER GOOD PH ASE F AU LT VR H OT 12V GATE VOLTAGE REGULATOR EN ABLE VI D 5 VI D 0 VI D 1 VI D 2 VI D 3 VI D 4 IR3081A CONTROL IC PHASE FAULT >> BIAS VOLTAGE >> PHASE TIMING > PWM CONTROL >> VID VOLTAGE BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CC S RCS CI N VOU T SEN SE+ IR3086A PHASE IC VOU T+ 0. 1uF COUT VOU T- VOU T SEN SE- PHASE FAULT BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CC S RCS IR3086A PHASE IC 0. 1uF OC OC OC OC OC OC OC CONTROL BUS ADDITIONAL PHASES OC OC OC INPUT/OUTPUT Figure 1. System Block Diagram Page 7 of 39 1/31/05 IR3081A PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. VIN CONTROL IC BIASIN 50% DUTY CYCLE SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR + PHASE IC PWM LATCH S PWM COMPARATOR + ENABLE + RESET DOMINANT RAMP GENERATOR VPEAK RMPOUT RPHS1 RAMPIN+ - GATEH VOSNS+ VOUT COUT VVALLEY RAMPINEAIN R VBIAS GATEL GND + VBIAS REGULATOR RPHS2 VDAC VOSNS- RPW MRMP PWMRMP + VDAC - CPW MRMP SCOMP CSCOMP RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER BODY BRAKING COMPARATOR + - EAOUT ERROR AMP FB RVF B ISHARE 10K + 20mV R DRP X34 DACIN VDRP AMP VDRP IIN BIASIN RAMPIN+ RAMPINEAIN RPHS2 RPHS1 + SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR PHASE IC PWM LATCH S PWM COMPARATOR + ENABLE RESET DOMINANT R RPW MRMP SCOMP CPW MRMP CSCOMP RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER ISHARE 10K + 20mV X34 DACIN Figure 2. PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins, as shown in figure 2. Page 8 of 39 + - - + PWMRMP BODY BRAKING COMPARATOR + - CURRENT SENSE AMPLIFIER - IFB IROSC + - - VOSNS- + - + - X 0.91 + + - CURRENT SENSE AMPLIFIER CSIN+ CC S RCS CSIN- GATEH GATEL X 0.91 CSIN+ CC S RCS CSIN- 1/31/05 IR3081A 50% RAMP DUTY CYCLE SLOPE = 80mV / % DC RAMP (FROM CONTROL IC) VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz CLK1 CLK2 PHASE IC CLOCK PULSES CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 Figure 3. 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the nonoverlap time. When the PWMRMP voltage exceeds the Error Amplifier’s output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 4 depicts PWM operating waveforms under various conditions. Page 9 of 39 1/31/05 IR3081A PHASE IC CLOCK PULSE EAIN PWMRMP VDAC 91% VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID=11111X) STEADY-STATE OPERATION Figure 4. PWM Operating Waveforms Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amplifier’s output voltage drops below 91% of the VDAC voltage this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is, vC ( s ) = v L ( s ) R L + sL 1 = iL ( s ) 1 + sR CS C CS 1 + sR CS C CS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 10 of 39 1/31/05 IR3081A vL iL L RCS Current Sense Amp RL CCS c v CS VO CO CSOUT Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 5. Its gain decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the Control IC for voltage positioning and current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page 11 of 39 1/31/05 IR3081A IR3081A THEORY OF OPERATION Block Diagram The Block diagram of the IR3081A is shown in Fig. 6, and specific features are discussed in the following sections. VCC UVLO COMPARATOR VCC + 9.7V 8.9V ENABLE START STOP + FAULT LATCH SQ 0.2V DISCHARGE OVER COMPARATOR CURRENT SET DOMINANT PWRGD - + + + 0.6V VCHG 3.8V 65mV 115mV + - + - ON IDISCHG IDISCHG 6uA ICHGICHG 70uA SS/DEL VID5 VID0 VID1 VID2 VID3 VID4 BBFB VOSNSVBIAS IROSC IROSC IROSC IROSC VID CONTROL IROSC IROSC IROSC IROSC + 0.6V + - VID STEP-DOWN VID DAC OUTPUT IROSC 1.2V VDAC FB IROSC IFB VBIAS 50% DUTY CYCLE RAMP GENERATOR 5.0V IROSC CURRENT SOURCE GENERATOR RMPOUT ROSC Figure 6. IR3081A Block Diagram VID Control A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block diagram of the VID control circuitry can be found in Figure 7. The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system accuracy and has a wider tolerance. Page 12 of 39 - 1.0V + + VBIAS REGULATOR + 6.8V ROSC BUFFER AMPLIFIER + VID = 11111X + + - + OFF SS/DEL DISCHARGE PRECONDITION RESET COMPARATOR - RESET DOMINANT R SOFT START CLAMP 1.3V ERROR AMPLIFIER EAOUT DISABLE - - OCICHG SQ 10k + + - + - ENABLE COMPARATOR R DELAY COMPARATOR + IROSC OVER CURRENT COMPARATOR + SET THRESHOLD 0.7V (1.3-0.6V) PRECONDITION PRECONDITION SET COMPARATOR LATCH IOCSET OCSET IIN VDRP AMPLIFIER VDRP IDISCHG 40uA - + - + LGND 1/31/05 IR3081A The IR3081A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output back to the input. The IR3081A includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected by the VID step-down detect comparator which monitors the “fast” output of the DAC (plus 7mV for noise immunity) compared to the “slow” output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This triggers the Body BrakingTM function, which turns off both high side and low side drivers in the phase ICs. The converter’s output voltage needs to be monitored and compared to the VDAC voltage to determine when to resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network during the sudden decrease in the Error Amplifier’s output voltage so an additional pin BBFB is provided. The BBFB pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin and therefore provides an un-corrupted representation of converter output voltage. The regulation detect comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier’s output and allowing normal operation to resume. Body BrakingTM during a transition to a lower VID code can be disabled by connecting the BBFB pin to ground. 800ns BLANKING VID = 11111X DETECT VID5 VID0 VID1 VID2 VID3 VID4 VID INPUT COMPARATORS (1 OF 6 SHOWN) DIGITAL TO ANALOG CONVERTER VDAC BUFFER AMP "FAST" VDAC + - + ISOURCE "SLOW" VDAC VDAC 0.6V VOSNSEAOUT VID DOWN BB CLAMP TO ERROR AMP ENABLE + 7mV 75% S RESET DOMINANT 1.7us BLANKING VID STEP-DOWN DETECT COMPARATOR R REGULATION DETECT COMPARATOR Figure 7. VID Control Block Diagram Page 13 of 39 + BODY BRAKE LATCH - - + - + + - ISINK - + IBBFB BBFB IROSC (From Current Source Generator) 1/31/05 IR3081A Processor Pins (0 = low, 1 = high) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout (V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF4 OFF4 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 Processor Pins (0 = low, 1 = high) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout (V) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 Note: 3. Output disabled (Fault mode) Table 1. Voltage Identification (VID) Adaptive Voltage Positioning Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure 8. Resistor RFB is connected between the Error Amplifier’s inverting input pin FB and the converter’s output voltage. An internal current source whose value is programmed by the same external resistor that programs the oscillator frequency pumps current into the FB pin. The error amplifier forces the converter’s output voltage lower to maintain a balance at its inputs. RFB is selected to program the desired amount of fixed offset voltage below the DAC voltage. The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP. Since the Error Amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an additional current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the adaptive positioning voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and therefore independent of the VDAC voltage. Page 14 of 39 1/31/05 IR3081A Contr ol IC VD AC Phas e IC Curr ent Sens e A mplif ier 10k - EA OUT Vo ISHA RE VDA C FB IFB RFB R DRP V DRP A mplif ier + V DRP Phas e IC Curr ent Sens e A mplif ier CSIN+ CSIN- ... ... IIN ISHA RE VDA C 10k Figure 8. Adaptive voltage positioning Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. A similar network must be placed on the BBFB to ensure proper operation during a transition to a lower VID code with Body BrakingTM. Control IC VD AC Err or A mplif ier + EA OUT FB RFB RF B2 Rt Vo IF B AV P Amplif ier + RDRP V DRP IIN Figure 9. Temperature compensation of inductor DCR Remote Voltage Sensing To reduce the effect of impedance in the ground plane, the VOSNS- pin is used for remote sensing and connected directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed transients are fed directly into the error amplifier without delay. Page 15 of 39 + - + Err or A mplif ier + CSIN+ CSIN- - - 1/31/05 IR3081A Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3081A has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay and hiccup mode timing. A charge current of 70uA and discharge current of 6uA control the up slope and down slope of the voltage at the SS/DEL pin respectively Figure 10 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset until it reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.71V and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.8V, indicating the end of the soft start. Under Voltage Lock Out and VID=11111x faults as well as a low signal on the ENABLE input immediately sets the fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an overcurrent fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 90mV offset of the delay comparator, the Fault latch will be set pulling the error amplifier’s output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The SS/DEL capacitor will continue to discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup mode will begin. During hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. However, the hiccup frequency is determined by the load current and over-current set value. The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the series resistor should be 10KΩ or less to avoid interference with the soft start function. If SS/DEL pin is pulled below 0.9V, the converter can be disabled. Under Voltage Lockout (UVLO) The UVLO function monitors the IR3081A’s VCC supply pin and ensures that IR3081A has a high enough voltage to power the internal circuit. The IR3081A’s UVLO is set higher than the minimum operating voltage of compatible Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC exceeds 9.7V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides a simple 5V UVLO function. Over Current Protection (OCP) The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage, which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current protection is triggered. VID = 11111X Fault VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided to prevent a fault condition from occurring during Dynamic VID changes. Enable Input Pulling the ENABLE pin below 0.6V sets the Fault Latch. Page 16 of 39 1/31/05 IR3081A VCC (12V) 8.9V UVLO ENABLE SS/DEL 3.735V 3.685V 1.3V VOUT PWRGD OCP THRESHOLD IOUT START-UP (ENABLE GATES FAULT MODE) NORMAL OPERATION (VOUT CHANGES DUE TO LOAD OCP AND VID CHANGES) DELAY HICCUP OVER-CURRENT PROTECTION RE-START AFTER OCP POWER-DOWN (VCC GATES FAULT MODE) Figure 10. Operating Waveforms Power Good Output The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.71V. The PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage regulation within the design limits can logically be assured however, assuming no component failure in the system. Load Current Indicator Output The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage. System Reference Voltage (VBIAS) The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors. Precondition of IIN during Soft Start IIN pin is clamped during the early stage of soft start, which disables current sharing function in the phase ICs to prevent PWM ramp from pulling too low. When V(SS/DEL)