IR3084UMPBF

IR3084U XPHASE DESCRIPTION The IR3084U Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to implement a complete VR10, VR11, Opteron, or Athlon64 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3084U is based on the IR3084 VR10 Control IC, but incorporates the following modifications; • • • • • • • • Supports VR11 7-bit VID, VR10 7-bit extended VID, and Opteron/Athlon64 5-bit VID codes Supports both VR11 and legacy Opteron/Athlon64 start-up sequences VID Select pin sets the DAC to VR10, VR11, or Opteron/Athlon64 INTL_MD output pin indicates which DAC is selected – Intel or AMD VOSENS− float detection protects the CPU in the event that the VOSENS− trace is broken Enable Input Thresholds set by VID Select pin to either VR10, VR11 or Opteron/Athlon64 VID Input Thresholds set by VID Select pin to either 0.6V (VR10/VR11) or 1.24V (AMD) No-Load Setpoint Current changes polarity based on VID Select to accommodate VR10, VR11 (negative offset from DAC) or Opteron/Athlon64 (positive offset from DAC). TM Data Sheet No. PD94719 VR10, VR11 & OPTERON/ATHLON64 CONTROL IC FEATURES • • • • • • • • • • • • • • • 1 to X phase operation with matching Phase IC 7-bit VR 10/11 compatible VID with 0.5% overall system set point accuracy 5-bit Opteron/Athlon64 compatible VID with 1% overall system set point accuracy Programmable Dynamic VID Slew Rate +/-300mV Differential Remote Sense Programmable VID Offset Voltage at the Error Amplifier’s Non-Inverting Input allows Zero Offset Programmable 150kHz to 1MHz oscillator Programmable VID Offset and Load Line output impedance Programmable Hiccup Over-Current Protection with Delay to prevent false triggering Simplified VR Ready output provides indication of proper operation and avoids false triggering Operates from 12V input with 9.9V Under-Voltage Lockout 6.8V/6mA Bias Regulator provides System Reference Voltage Phase IC Gate Driver Bias Regulator / VRHOT Comparator Reduced Over-Current Detect Delay eliminates and external resistor in typical applications Small thermally enhanced 28L MLPQ package Page 1 of 47 9/14/2005 IR3084U TYPICAL APPLICATION CIRCUIT CCP1 100pF EA RT2 R117 4.7K, B=4450 1.21K +5.0V RCP 2.49K CCP 56nF R137 2K C204 0.1uF 27 15 19 20 C134 0.1uF C89 100pF VR_RDY ISHARE RMP VBIAS C135 1uF VREG_12V_FILTERED R1331 1 Q4 CJD200 VGDRIVE RFB1 162 VCC_SENSE RFB 348 CFB 12nF 17 FB 18 U5 VSS_SENSE C1009 1nF R DRP1 750 EAOUT VRRDY IIN RMPOUT VBIAS RDRP 750 IR3084UMTR Q5 16 VDRP REGDRV REGFB REGSET OUTEN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID_SEL VREG_12V_FILTERED 21 R30 10 C130 0.1uF 26 CSS/DEL 0.1uF VCC SS/DEL 28 9 8 7 6 5 4 3 1 ENABLE VID0 VID1 VID2 VID3 VID4 VID5 VID6 VIDSEL INTL_MD 24 23 25 2 RVGDRV 97.6K Q6 RVSETPT1 124 VSETPT OCSET VDAC 14 13 12 11 ROSC 30.1K RVSETPT 124 ROCSET 12.7K RVDAC 3.5 CVGDRV 10nF VDAC CVDAC 33nF VOSNS-- LGND ROSC 10 22 Page 2 of 47 9/14/2005 IR3084U ORDERING INFORAMATION DEVICE IR3084UMTRPBF IR3084UMPBF ORDER QUANTITY 3000 Tape and Reel 100 Piece Strip ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..0 to 150oC Storage Temperature Range………………….−65oC to 150oC ESD Rating………………………………………HBM Class 1B JEDEC standard Moisture Sensitivity Level………………………JEDEC Level 3 @ 260 oC PIN # 1 2 3-9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VIDSEL INTL_MD VID6−VID0 VOSNSROSC VDAC OCSET VSETPT IIN VDRP FB EAOUT RMPOUT VBIAS VCC LGND REGFB REGDRV REGSET SS/DEL VRRDY ENABLE VMAX 20V 20V 20V 0.5V 20V 20V 20V 20V 20V 20V 20V 10V 20V 20V 20V n/a 20V 20V 20V 20V 20V 20V VMIN -0.3V -0.3V -0.3V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 5mA 50mA 1mA 50mA 1mA 10mA 1mA 1mA 1mA 1mA ISINK 1mA 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 5mA 10mA 50mA 1mA 1mA 50mA 1mA 1mA 20mA 1mA Page 3 of 47 9/14/2005 IR3084U ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ VCC ≤ 16V, −0.3V ≤ VOSNS- ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, ROSC = 24kΩ, CSS/DEL = 0.1μF ±10% PARAMETER VDAC REFERENCE VR10/VR11 System Set-Point Accuracy (Deviation from Tables 1 & 2 per test circuit in Figure 1 which emulates in-VR operation) Opteron/Athlon64 System SetPoint Accuracy Source Current Sink Current VR10/VR11 VIDx Input Threshold Opteron/Athlon64 VIDx Input Threshold VIDx Input Bias Current VIDx 11111x Blanking Delay VIDSEL Pull up Voltage VIDSEL Pull up Resistor VIDSEL VR10/Opteron Threshold VIDSEL Opteron Voltage VIDSEL Opteron/VR11 Threshold ERROR AMPLIFIER Input Offset Voltage FB Bias Current VSETPT Bias Current VSETPT Bias Current DC Gain Gain Bandwidth Product Corner Frequency Slew Rate Source Current Sink Current Max Voltage Min Voltage Measure V(FB) – V(VSETPT) per test circuit in Figure 1. Applies to all VID codes. Note 2. VR10/VR11 Mode Opteron/Athlon64 Mode Note 1 Note 1 45 deg Phase Shift, Note 1 Note 1 −5 −1 48.5 −54 90 6 1.4 −1.2 0.5 150 30 0.0 −0.1 51 −47 100 10 200 3.2 −0.7 1.1 350 125 5 0.5 53.5 −39 110 400 5 −0.35 1.7 600 200 mV μA μA μA dB MHz Hz V/μs mA mA mV mV VID ≥ 1V, 10kΩ≤ROSC≤100kΩ, 25 oC ≤ TJ ≤ 100 oC 0.8V ≤ VID < 1V, 10kΩ≤ROSC≤100kΩ, 25 oC ≤ TJ ≤ 100 oC 25 oC ≤ TJ ≤ 100 oC Includes OCSET and VSETPT currents Includes OCSET and VSETPT currents −0.5 −5 −1 104 92 500 1.04 0V < VIDx < VCC Measure Time till VRRDY drives low VIDSEL Floating VIDSEL “LOW” 6.49K from VIDSEL to GND −5 0.5 1.95 2.25 0.5 0.9 1.8 113 100 600 1.24 0 1.3 2.4 4.5 0.6 1.3 1.95 0.5 +5 1 122 108 700 1.44 5 2.1 2.85 9 0.7 1.7 2.1 % mV % μA μA mV V μA μs V KΩ V V V TEST CONDITION MIN TYP MAX UNIT VBIAS–VEAOUT (referenced to VBIAS) Normal operation or Fault mode Page 4 of 47 9/14/2005 IR3084U PARAMETER CURRENT SENSE INPUT IIN BIAS CURRENT IIN Preconditioning Pull-Down Resistance IIN Preconditioning RESET Threshold IIN Preconditioning SET Threshold VDRP BUFFER AMPLIFIER Input Offset Voltage Source Current Sink Current Bandwidth (-3dB) Slew Rate VBIAS REGULATOR Output Voltage Current Limit Input Offset Voltage OCSET Bias Current SOFT START AND DELAY Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) DVID Slew Time & VRRDY Delay (TD4+TD5) PowerGood Delay OC Delay Time SS/DEL to FB Input Offset Voltage SS/DEL Charge Current SS/DEL Discharge Current Charge/Discharge Current Ratio OC Discharge Current Charge Voltage OC/VRRDY Delay Comparator Threshold OC/VRRDY Delay Comparator Threshold Delay Comparator Hysteresis VID Sample Delay Comparator Threshold SS/DEL Discharge Comparator Threshold Page 5 of 47 RDRP = ∞ RDRP = ∞, Time to reach 1.1V VR10/VR11 mode only VR10/VR11 mode only Opteron/Athlon64 mode. Measured from Vcore=1.1V to when VRRDY transitions HI. TEST CONDITION V(SS/DEL) > 0.85V, V(EAOUT) > 0.5V V(SS/DEL) < 0.35V V(EAOUT) V(SS/DEL) MIN −2.0 5.6 0.20 0.35 TYP −0.2 12.5 0.35 0.60 MAX 1.0 19.4 0.50 0.85 UNIT µA KΩ V V V(VDRP) – V(IIN), 0.5V < V(IIN) < 5V 0.5V < V(IIN) < 5V 0.5V < V(IIN) < 5V Note 1 Note 1 −5mA < I(VBIAS) < 0mA −10 −9.0 0.2 1 5 6.6 −35 −10 −53.5 1.2 0.8 0.2 0.5 0.7 150 −2 −6.8 0.85 6 10 6.9 −20 0 −51 1.8 1.8 1.0 1.3 2.3 250 1.3 70 6.5 11.2 40 3.85 80 100 20 3.10 215 6 −4.0 4.1 mV mA mA MHz V/μs V mA mV μA ms ms ms ms ms us V μA μA μA/μA μA V mV mV mV V mV 7.2 −6 10 −48.5 2.6 2.8 2.5 2.2 4.7 350 1.5 100 9 12.5 60 4.1 OVER-CURRENT COMPARATOR 1V < V(OCSET) < 5V With FB = 0V, adjust V(SS/DEL) until EAOUT drives high 0.85 40 4 9.5 Note 1 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling Note 1 VR10/VR11 mode only 20 3.6 9/14/2005 IR3084U PARAMETER VRRDY OUTPUT Output Voltage Leakage Current ENABLE INPUT VR10/11 Threshold Voltage VR10/11 Threshold Voltage VR10/11 Threshold Hysteresis Opteron/Athlon64 Threshold Voltage Opteron/Athlon64 Threshold Voltage Opteron/Athlon64 Threshold Hysteresis Input Resistance Blanking Time OSCILLATOR Switching Frequency Peak Voltage (4.8V typical, measured as % of VBIAS) Valley Voltage (0.9V typical, measured as % of VBIAS) INTL_MD OUTPUT Source Current Sink Current Max Voltage Min Voltage VOSNS− FLOAT DETECT Detect Voltage Detect Delay DRIVER BIAS REGULATOR REGSET Bias Current Input Offset Voltage Short Circuit Current Dropout Voltage 1.5V < V(REGSET) < VCC – 1.5V 1.5V < V(REGSET) < VCC – 1.5V, 100μA < I(REGDRV) < 10mA V(REGDRV) = 0V, 1.5V < V(REGSET) < VCC – 1.5V, Note 1 I(REGDRV) = 10mA, Note 1 −112 −12 10 0.4 −99 0 20 0.87 −85 12 50 1.33 μA mV mA V V(VOSNS−) with respect to V(LGND), Verify V(VRRDY) and V(EAOUT) are low. V(VOSNS-) 0V to 2.6V step, measure time when V(VRRDY) falls. Note 1 1.2 200 2 350 2.6 600 V ns V(INTL_MD)=2V, VR10 or VR11 mode V(INTL_MD)=2V, Opteron mode Pin Floating, V(VBIAS)−V(INTL_MD) Pin Floating, LGND referenced 100 250 50 200 750 170 400 300 1500 350 900 µA µA mV mV ROSC = 24KΩ 450 70 10 500 71 13 550 74 15 kHz % % ENABLE rising ENABLE falling ENABLE rising ENABLE falling 800 700 70 1.11 1.06 35 50 Noise Pulse < 250ns will not register an ENABLE state change. Note 1 75 850 750 100 1.23 1.17 60 100 250 900 800 130 1.35 1.29 85 200 400 mV mV mV V V mV KΩ ns I(VRRDY) = 4mA V(VRRDY) = 5.5V 150 0 300 10 mV μA TEST CONDITION MIN TYP MAX UNIT Page 6 of 47 9/14/2005 IR3084U PARAMETER VCC UNDER-VOLTAGE LOCKOUT Start Threshold Stop Threshold Hysteresis GENERAL VCC Supply Current VOSNS− Current −0.3V < VOSNS− < 0.3V, All VID Codes 9 −1.45 14 −1.1 18 −0.75 mA mA 9.3 8.5 550 9.9 9.1 800 10.3 9.5 1000 V V mV TEST CONDITION MIN TYP MAX UNIT Start – Stop Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors 200 OHM - VDAC BUFFER AMP ISOURCE ISINK + INTEL: +IOFFSET IROSC AMD: --IOFFSET + "FAST" VDAC Figure 1 – System Set Point Test Circuit Page 7 of 47 + - - CURRENT SOURCE GENERATOR ROSC BUFFER AMP + - IR3084U EAOUT ERROR AMP FB 200 OHM VSETPT OCSET VDAC IROSC IOCSET RVDAC SYSTEM SET POINT VOLTAGE CVDAC ROSC + ROSC 1.2V VOSNS- 9/14/2005 IR3084U PIN DESCRIPTIONS PIN# PIN SYMBOL DESCRIPTION Selects the DAC table and the type of Soft Start. There are 3 possible modes of operation: (1) GND selects VR10 DAC and VR11 type startup, (2) FLOAT (2.4V) selects VR11 DAC and VR11 type startup, (3) 6.49K to GND (1.3V) selects Opteron/Athlon64 DAC and legacy type startup. Additional details are provided in the Theory of Operation section. Output that indicates if the controller is in Intel Mode or AMD Mode. This pin will be Low when in AMD mode and High when in Intel mode. Inputs to the D to A Converter. Must be connected to an external pull up resistor. Negative Remote Sense Input. Connect to ground at the Load. Connect a resistor from this pin to VOSNS− to program the oscillator’s frequency, OCSET, VSETPT, REGSET, and VDAC bias currents. Regulated output voltage programmed by the VID inputs. Connect an external RC network to from this pin to VOSNS− to program the Dynamic VID slew rate and provide compensation for the internal Buffer Amplifier. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Over-current protection can be disabled by connecting a resistor from this pin to VDAC to program the threshold higher than the possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Error Amp non-inverting input. The converter’s output voltage can be decreased (Intel) or increased (AMD) from the VDAC voltage with an external resistor connected between VDAC and an internal current source. Current sensing and PWM operation are referenced to this pin. Current Sense input from the Phase IC(s). Prior to startup, when SS/DEL0.6V and EAOUT>0.35V, this pin is released and current balancing is enabled. If AVP or over-current protection is not required, connect this pin to VDAC. To ensure proper do not float this pin. Buffered IIN signal. Connect an external resistor from this pin to the FB pin to set the converter’s output impedance. Inverting input to the Error Amplifier. Output of the Error Amplifier. When Low, provides UVL function to the Phase ICs. Oscillator Output voltage. Used by the Phase ICs to program Phase Delay. 6.9V/6mA Regulated output used as a system reference voltage for internal circuitry and for phase timing at the Phase ICs. Power Input for the internal circuitry. Local Ground for internal circuitry and IC substrate connection Inverting input of the Bias Regulator Error Amp. Connect this pin to the collector of the Phase IC Gate Driver Bias transistor. Output of the Bias Regulator Error Amp. Non-inverting input of the Bias Regulator Error Amp. The output voltage of the Phase IC Gate Driver Bias Regulator is set by an internal current source supplying an external resistor connected from this pin to ground. Controls converter start-up and over-current timing. Connect an external capacitor from this pin to LGND to program the soft start and delay times. Open Collector output that drives low during start-up and when any external fault occurs. Connect external pull-up resistor. Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin has a 100K pull-down resistor to GND. 9/14/2005 1 VIDSEL 2 3-9 10 11 12 INTL_MD VID6−VID0 VOSNS− ROSC VDAC 13 OCSET 14 VSETPT 15 IIN 16 17 18 19 20 21 22 23 24 25 26 27 28 VDRP FB EAOUT RMPOUT VBIAS VCC LGND REGFB REGDRV REGSET SS/DEL VRRDY ENABLE Page 8 of 47 IR3084U SYSTEM THEORY OF OPERATION XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 2, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing. There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. VR READY PHASE FAULT VR HOT VR FAN 12V ENABLE VIDSEL PHASE FAULT VID6 VID5 VID4 VID3 >> PWM CONTROL VID2 >> VID VOLTAGE VID1 VID0 C CS R CS VOUT SENSE- IR3084 CONTROL IC CIN >> BIAS VOLTAGE >> PHASE TIMING