IR3087PBF

IR3087PBF DATA SHEET XPHASETM PHASE IC WITH OPTI-PHASETM, OVP, AND OVERTEMP DETECT DESCRIPTION The IR3087 Phase IC combined with an IR XPhaseTM Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3087 with Opti-PhaseTM is intended for applications demanding increased efficiency under medium to light load conditions. Both gate drivers will drive low at a programmable output current threshold. This effectively disconnects the phase from the load eliminating power losses due to switching and circulating currents. FEATURES • • • • • • • • • • • • • 2.5A Average Gate Drive Current Loss-Less Inductor Current Sense Internal Inductor DCR Temperature Compensation Programmable Phase Delay Programmable Feed-Forward Voltage Mode PWM Ramp Sub 100ns Minimum Pulse Width supports 1MHz per-phase operation Current Sense Amplifier drives a single wire Average Current Share Bus Current Share Amplifier reduces PWM Ramp slope to ensure sharing between phases Body BrakingTM disables Synchronous MOSFET for improved transient response and prevents negative output voltage at converter turn-off Opti-PhaseTM reduces the number of phases for improved light to medium load efficiency OVP comparator with 150ns response Programmable Phase Over-Temperature Detection Small thermally enhanced 20L MLPQ package APPLICATION CIRCUIT VGATE 12V VRHOT DAC RBIASI N 20k 20 19 18 17 ROP1 ROP2 RC SCCS+ CC SRCS+ 16 BIAS RPHASE1 DBST OPT I PH S BI ASI N DACI N CSIN+ CSI N - CBST CIN 1 5 Wire Analog Bus From Control IC RMPI N + RMPI N HOTSET VRHOT I SHARE SC OM P EAI N VCCH GATEH PGN D GATEL VC C L LGN D VC C 15 14 13 12 11 L RAMP 2 3 4 IR3087 PHASE IC PW MRMP VO CO ISHARE R PH ASE2 5 CVCCL RVC C RPWMRMP 6 7 8 9 CSCOMP CPWMRM P EA RPHASE3 10 CVCC Page 1 of 35 1/31/05 IR3087PBF ORDERING INFORMATION Device IR3087MTRPbF IR3087MPbF Order Quantity 3000 per reel 100 piece strips ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150oC Storage Temperature Range………………….-65oC to 150oC ESD Rating……………………………………..HBM Class 1C JEDEC standard PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN PWMRMP LGND VCC VCCL GATEL PGND GATEH VCCH CSIN+ CSINOPTIPHS DACIN BIASIN VMAX 20V 20V 20V 20V 20V 20V 20V 20V n/a 24V 27V 27V 0.3V 30V 30V 20V 20V 20V 20V 20V VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 1mA 1mA 1mA 50mA n/a n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 1mA 1mA 1mA 1mA 1mA ISINK 1mA 1mA 1mA 30mA 5mA 1mA 1mA 20mA n/a 50mA 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 1mA 1mA 1mA 1mA 1mA Page 2 of 35 1/31/05 IR3087PBF ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8.4V ≤ VCC ≤ 21V, 6V ≤ VCCH ≤ 28V, 6V ≤ VCCL ≤ 14V, and 0 oC ≤ TJ ≤ 125 oC, CGATEH = 3.3nF, CGATEL = 6.8nF PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time GATEL low to GATEH high delay GATEH low to GATEL high delay Disable Pull-Down Current Current Sense Amplifier CSIN+ Bias Current CSIN- Bias Current Input Offset Voltage Gain at TJ = 25 oC Gain at TJ = 125 oC Slew Rate TEST CONDITION VCCH = 12V, Measure 2V to 9V transition time VCCH = 12V, Measure 9V to 2V transition time VCCL = 12V, Measure 2V to 9V transition time VCCL = 12V, Measure 9V to 2V transition time VCCH = VCCL = 12V, Measure the time from GATEL falling to 1V to GATEH rising to 1V VCCH = VCCL = 12V, Measure the time from GATEH falling to 1V to GATEL rising to 1V Force GATEH or GATEL = 2V with BIASIN = 0V MIN TYP 22 22 50 50 MAX 50 50 75 75 50 UNIT ns ns ns ns ns 10 25 10 25 50 ns 15 25 40 µA CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN -0.5 -1 -3 32 27 -0.25 -0.4 0.5 34 29 12.5 0 0 5 36 31 µA µA mV V/V V/V V/µs Current Sense Amplifier output is an internal node. Slew rate at the ISHARE pin will be set by the internal 10kΩ resistor and any stray external capacitance -20 0 7.9 9.3 Force I(PWMRMP) = 500µA. Measure V(PWMRMP) – V(DACIN) -10 4 Differential Input Range Common Mode Input Range Rout at TJ = 25 oC Rout at TJ = 125 oC Ramp Discharge Clamp Clamp Voltage Clamp Discharge Current 10.5 12.4 5 8 100 4 13.1 15.5 20 mV V kΩ kΩ mV mA Page 3 of 35 1/31/05 IR3087PBF PARAMETER Ramp Comparator Input Offset Voltage Hysteresis RMPIN+, RMPIN- Bias Current Propagation Delay TEST CONDITION MIN 20 -10 -1 100 TYP 40 0 0 150 MAX 80 10 1 240 UNIT mV mV µA ns Note 1 VCCH = 12V. Measure time from RMPIN input (50mV overdrive) to GATEL transition to V(DACIN) (200mV overdrive) to GATEL transition to > BIAS VOLTAGE >> PHASE TIMING > PWM CONTROL >> VID VOLTAGE BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CC S RCS CIN VOU T SEN SE+ IR3087 PHASE IC VOU T+ 0. 1uF COUT VOU T- VOU T SEN SE- PHASE FAULT BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CC S RCS IR3087 PHASE IC 0. 1uF OC OC OC OC OC OC CONTROL BUS ADDITIONAL PHASES OC OC OC INPUT/OUTPUT Figure 1. System Block Diagram Page 7 of 35 1/31/05 IR3087PBF PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. VIN CONTROL IC BIASIN 50% DUTY CYCLE SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR + PHASE IC PWM LATCH S PWM COMPARATOR + ENABLE + RESET DOMINANT RAMP GENERATOR VPEAK RMPOUT RPHS1 RAMPIN+ - GATEH VOSNS+ VOUT COUT VVALLEY RAMPINEAIN R VBIAS GATEL GND + VBIAS REGULATOR RPHS2 VDAC VOSNS- RPW MRMP PWMRMP + VDAC - CPW MRMP SCOMP CSCOMP RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER BODY BRAKING COMPARATOR + - EAOUT ERROR AMP FB RVF B ISHARE 10K + 20mV R DRP X34 DACIN VDRP AMP VDRP IIN BIASIN RAMPIN+ RAMPINEAIN RPHS2 RPHS1 + SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR PHASE IC PWM LATCH S PWM COMPARATOR + ENABLE RESET DOMINANT R RPW MRMP SCOMP CPW MRMP CSCOMP RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER ISHARE 10K + 20mV X34 DACIN Figure 2. PWM Block Diagram Frequency and Phase Timing Control An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 4.6V and 0.9V respectively. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins, as shown in Figure 2. Page 8 of 35 + - - + PWMRMP BODY BRAKING COMPARATOR + - CURRENT SENSE AMPLIFIER - IFB IROSC + - - VOSNS- + - + - X 0.91 + + - CURRENT SENSE AMPLIFIER CSIN+ CC S RCS CSIN- GATEH GATEL X 0.91 CSIN+ CC S RCS CSIN- 1/31/05 IR3087PBF 50% RAMP DUTY CYCLE SLOPE = 80mV / % DC RAMP (FROM CONTROL IC) VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz CLK1 CLK2 PHASE IC CLOCK PULSES CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 Figure 3. 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the nonoverlap time. When the PWMRMP voltage exceeds the Error Amplifier’s output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 4 depicts PWM operating waveforms under various conditions. Page 9 of 35 1/31/05 IR3087PBF PHASE IC CLOCK PULSE EAIN PWMRMP VDAC 91% VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, VCCVID UV, OCP, VID=11111X) STEADY-STATE OPERATION Figure 4. PWM Operating Waveforms Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amplifier’s output voltage drops below 88% of the VDAC voltage this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a resistor and a capacitor in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is, vC ( s) = vL ( s) 1 RL + sL = iL ( s) 1 + sRCS CCS 1 + sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 10 of 35 1/31/05 IR3087PBF vL iL L RCS Current Sense Amp RL CCS c v CS VO CO CSOUT Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier This is a high speed differential current sense amplifier, as shown in Figure 5. Its gain decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current being delivered to the load and is used by the Control IC for voltage positioning and current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is smaller than the average current, the share adjust error amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page 11 of 35 1/31/05 IR3087PBF IR3087 THEORY OF OPERATION Block Diagram The Block diagram of the IR3087 is shown in Figure 6, and specific features are discussed in the following sections. RAMP COMPARATOR + - RMPIN+ RMPINEAIN CLOCK PULSE GENERATOR PWM LATCH S PWM COMPARATOR + RESET DOMINANT VCCH GATEH R - + SCOMP ISHARE 10K LGND SHARE ADJUST ERROR SCOMPMP A - X 0.88 + + 20mV ISHARE VDAC + VDAC VDAC X34 - OPTIPHS BIASIN SYSTEM BIASIN ENCE REFER VOLTAGE 400mV OPTI-PHASE COMPARATOR - + - Figure 6. IR3087 Block Diagram Tri-State Gate Drivers The gate drivers can deliver up to 3A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction. An Enable signal is provided by the Control IC to the Phase IC without the addition of a dedicated signal line. The Error Amplifier output of the Control IC drives low in response to any fault condition such as input under voltage or output overload. The IR3087 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state operation prevents negative inductor current and negative output voltage during power-down. The Gate Drivers revert to a high impedance “off” state if VCCL and VCCH supply voltages are below the normal operating range. An 80kΩ resistor is connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or other cause under these conditions. Over Voltage Protection (OVP) The IR3087 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET or connection of the converter output to an excessive output voltage. A comparator monitors the voltage at the CSIN- pin which is usually connected directly to the converter output. If the voltage exceeds the DACIN voltage plus 125mV typical (100mV minimum and 160mV maximum), the GATEL pin drives high. The OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain ON until the over-voltage condition ceases. Page 12 of 35 - OPTI-PHASE DISABLE COMPARATOR + - + VOLTAGE PROPORTIONAL TO ABSOLUTE TEMPERATURE + + - + - + + RAMP SLOPE ADJUST 0% DUTY CYCLE COMPARATOR - - OVP COMPARATOR CURRENT SENSE AMP + 125mV - RAMP DISCHARGE CLAMP + PWMRMP ENABLE - - ENABLE + GATE NON-OVERLAP COMPARATORS + 2V VCCL GATEL PGND + - INTERNAL CIRCUVCC IT BIAS VCC + DACIN CSIN+ CSINVRHOT COMPARATOR VRHOT HOTSET 1/31/05 IR3087PBF When designing for OVP the overall system must be considered. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible a fuse can be added in the input supply to the multiphase converter. One scenario to be careful of is where the input voltage to the multiphase converter may be pulled below the level where the ICs can provide adequate voltage to the low side MOSFET thus defeating OVP. Dynamic changes in the VID code to a lower output voltage may trigger OVP. For example; a 250mV decrease in output voltage combined with a light load condition will cause the low side MOSFETs to turn on and interfere with Body BrakingTM. This will not cause a problem, however, as Body BrakingTM will resume once the output voltage is less than 125mV above the VID voltage. Since CSIN- pin is also used as the inductor current sensing input, it is usually connected to the local converter output, which may be far away from the load of the multiphase converter. Excessive distribution impedance between the converter and load may trigger OVP during normal operation. If the voltage drop across the distribution impedance exceeds the minimum OVP comparator threshold of 100mV plus VID offset and voltage positioning, the IR3087 can not be used. The IR3088A Phase IC without OVP should be used instead in applications with excessive distribution impedance and very small or no AVP. For example, a converter having 25mV of VID offset, 125mV of AVP at full load, and 100mV of drop in the distribution path at full load would be OK, since 100mV + 25mV + 125mV = 250mV which is greater than the 100mV drop. However, a converter having 25mV of VID offset, no AVP, and 130mV of drop in the distribution path would require IR3088A, since 100mV + 25mV + 0mV = 125mV which is smaller than the 130mV drop. Converter with higher output voltage than VID voltage may also trigger OVP during normal operation, and IR3088A should be used to replace IR3087. Thermal Monitoring (VRHOT) The IR3087 senses its own die temperature and produces a voltage at the input of the VRHOT comparator that is proportional to temperature. An external resistor divider connected from VBIAS to the HOTSET pin and ground can be used to program the thermal trip point of the VRHOT comparator. The VRHOT pin is an open-collector output and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT output drives low. Opti-PhaseTM The number of phases chosen for a particular design is based upon meeting thermal requirements and minimizing the number of input and output capacitors at the maximum output current. At currents less than the maximum efficiency will increase if less phases are used. Turning off phases as the output current decreases increases efficiency by eliminating the gate charging losses, MOSFET switching losses, and circulating currents in the MOSFETS and output inductors. For each unique design there will be an optimal point were phases should be turned off, one after another, to achieve the maximum efficiency over the entire output current range. The IR3087 implements patent pending Opti-PhaseTM control allowing programmable shutdown of phases as a function of converter output current. The Opti-PhaseTM comparator monitors the voltage on the ISHARE pin less the voltage on the DACIN pin. This voltage provides a direct indication of converter output current. A resistor divider connected between the BIASIN, OPTIPHS, and LGND pins programs the threshold of the Opti-PhaseTM comparator. If the converter output current drops below the programmed level the GATEH and GATEL pins will both drive low turning off the MOSFETs and causing the inductor current to begin to decay. The output voltage will begin to sag causing the Control IC to immediately increase the duty cycle of the remaining phase(s) to compensate. The voltage on the ISHARE will remain constant as it represents the converter output current rather than the current in the individual phases. Opti-PhaseTM can be disabled by connecting the OPTIPHS pin to the BIASIN pin. This must be done on at least one phase IC per converter to ensure operation under zero load conditions. Page 13 of 35 1/31/05 IR3087PBF APPLICATIONS INFORMATION POWERGOOD VRHOT 12V RVCC 10 ohm QGATE VGATE RBI ASI N CVCC 0. 1uF RPHASE11 RGATE 20k 20 19 18 17 16 RCSCC S+ CCSRC S+ D BST DGA T E OPT I PH S BI ASI N DACI N CSI N + CSI N - CBST 15 14 13 12 11 L CI N 1 2 3 4 C SS/ D EL 0. 1uF 5 CFB RBBF B 24 23 22 RPHASE12 VOUT SENSE+ RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H IR3087 PHASE IC PW MR MP LGN D VC C GATEH PGN D GATEL VC C L VOUT+ DISTRIBUTION IMPEDANCE COUT ENABLE 28 27 26 VOUTCVC C L RVCC RPW MRMP 25 6 7 CPW M R M P 8 9 10 RFB1 RF B VOUT SENSE- EN ABLE PW R GD SS/ D EL N/ C LGN D RM POU T VC C 1 OSCDS VI D 5 VI D 0 VI D 1 VI D 2 VI D 3 VBI AS BBF B 21 20 19 18 17 16 15 R DRP1 CDR P RCP R BBDRP RPH ASE13 VID5 VID0 VID1 VID2 VID3 VID4 2 3 4 5 6 7 CSC OMP CVCC IR3081A CONTROL IC VOSN SROSC TR M 1 TR M 2 TR M 3 TR M 4 EAOU T FB VD R P IIN OC SET VD AC CCP ROP21 ROP22 RCSCC S+ CC P1 RBI ASI N RPH ASE21 20k 19 20 18 17 16 CCS- RC S+ DBST VI D 4 R DRP OPT I PH S BI ASI N DACI N CSI N + CSI N - 8 9 10 11 12 13 14 CBST 15 14 13 12 11 L ROC SET CI N 1 2 RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H ROSC 3 RVDAC RSHAR E 4 5 CVDAC RPH ASE22 IR3087 PHASE IC PWMRMP LGN D VC C GATEH PGN D GATEL VC C L CVC C L RVCC RPW MRMP 6 7 CPW M RM P 8 9 RPH ASE23 CSC OMP 10 CVCC ROP31 ROP32 RCSCC S+ RBI ASI N RPH ASE31 20k 19 20 18 17 16 CCS- RC S+ DBST OPT I PH S BI ASI N DAC I N CSI N + CSI N - CBST 15 14 13 12 11 L CI N 1 2 3 4 5 RPH ASE32 RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H IR3087 PHASE IC PW M R M P LGN D VC C GATEH PGN D GATEL VC C L CVC C L RVCC RPW MRMP 6 7 CPW M RM P 8 9 RPHASE33 CSC OMP 10 CVCC ROP41 ROP42 RCSCC S+ RBI ASI N RPHASE41 20k 20 19 17 18 16 CCS- RC S+ DBST OPT I PH S BI ASI N DAC I N CSI N + CSI N - CBST 15 14 13 12 11 L CI N 1 2 3 4 5 RPHASE42 RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H IR3087 PHASE IC PW M R M P LGN D VC C GATEH PGN D GATEL VC C L CVC C L RVCC RPW MRMP 6 7 CPWM RMP 8 9 R PH ASE43 CSC OMP 10 CVCC ROP51 ROP52 RCSCC S+ RBI ASI N RPH ASE51 20k 20 19 17 18 16 CCS- RC S+ RC S+ CBST 15 14 13 12 11 L DBST OPT I PH S BI ASI N DACI N CSI N + CSI N - CI N 1 2 3 4 5 RPH ASE52 RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H IR3087 PHASE IC PW M R M P LGN D VC C GATEH PGN D GATEL VC C L CVC C L RVCC RPW MRMP 6 7 CPW M R M P 8 9 RPHASE53 CSC OMP 10 CVCC ROP61 ROP62 RCSCC S+ RBI ASI N RPHASE61 20k 19 20 18 17 16 CCS- RC S+ RC S+ CBST 15 14 13 12 11 L DBST OPT I PH S BI ASI N DACI N CSI N + CSI N - CI N 1 2 3 4 5 RPHASE62 RMPI N + RMPI N HOTSET VRHOT ISH AR E SC OM P EAI N VC C H IR3087 PHASE IC PW MR MP LGN D VC C GATEH PGN D GATEL VC C L CVC C L RVCC RPW MRMP 6 7 CPW M R M P 8 9 RPH ASE63 CSC OMP 10 CVCC Figure 7. 6 Phase IR3081A/3087 VRM / EVRD 10 Converter Page 14 of 35 1/31/05 IR3087PBF DESIGN PROCEDURES - IR3081A AND IR3087 CHIPSET IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081A generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to the curve in Figure 13. Soft Start Capacitor CSS/DEL Because the capacitor CSS/DEL programs four different time parameters, i.e. soft start delay time, soft start time, over-current latch delay time, and power good delay time, they should be considered together while choosing CSS/DEL. The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. After the ENABLE pin voltage rises above 0.6V, there is a soft-start delay time tSSDEL, after which the error amplifier output is released to allow the soft start. The soft start time tSS represents the time during which converter voltage rises from zero to VO. tSS can be programmed by an external capacitor, which is determined by Equation (1). C SS / DEL = I CHG * t SS 70 * 10 −6 * t SS = VO VO (1) Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in Equations (2), (3) and (4) respectively. tSSDEL = tOCDEL = CSS / DEL *1.3 CSS / DEL *1.3 = I CHG 70 *10−6 CSS / DEL * 0.115 CSS / DEL * 0.115 = I OCDISCHG 40 *10− 6 (2) (3) tVccPG = CSS / DEL * (3.8 − 0.065 − VO − 1.3) CSS / DEL * (3.735 − VO − 1.3) = I CHG 70 *10− 6 (4) VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in Equation (5), where ISINK is the sink current of VDAC pin as shown in Figure 15. The resistor RVDAC is used to compensate VDAC circuit and is determined by Equation (6). The slew rate of VDAC up-slope SRUP is proportional to that of VDAC down-slope and is given by Equation (7), where ISOURCE is the source current of VDAC pin as shown in Figure15. CVDAC = I SINK SR DOWN (5) RVDAC = 0.5 + SRUP = 3.2 ∗ 10 −15 CVDAC 2 (6) I SOURCE CVDAC (7) Page 15 of 35 1/31/05 IR3087PBF Over Current Setting Resistor ROCSET The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation (8), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature T_ROOM respectively. R L _ MAX = R L _ ROOM ∗ [1 + 3850 * 10 −6 ∗ (T L _ MAX − TROOM )] (8) The current sense amplifier gain of IR3087 decreases with temperature at the rate of 1470 ppm/°C, which compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (9). GCS _ MIN = GCS _ ROOM ∗ [1 − 1470 * 10 −6 ∗ (TIC _ MAX − TROOM )] (9) The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset (VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current sense resistors RCS+ and RCS-. VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS + − I CSIN − ∗ RCS − (10) The over current limit is set by the external resistor ROCSET as defined in Equation (11), where ILIMIT is the required over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC and is determined by the curve in Figure 14. KP is the ratio of inductor peak current over average current in each phase and is calculated from Equation (12). ROCSET = [ KP = I LIMIT ∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET n (11) (VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2) IO / n (12) No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning further lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. RFB is not only determined by IFB, the current flowing out of FB pin as shown in Figure 14, but also affected by the adaptive voltage positioning resistor RDRP and total input offset voltage of current sense amplifiers. RFB and RDRP are determined by (13) and (14) respectively. R FB = R L _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO I FB ∗ R L _ MAX R FB ∗ R L _ MAX ∗ GCS _ MIN n ∗ RO (13) R DRP = (14) Body BrakingTM Related Resistors RBBFB and RBBDRP The body brakingTM during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is enabled, Resistors RBBFB and RBBDRP are needed to restore the feedback voltage of the error amplifier after Dynamic VID step down. Usually RBBFB and RBBDRP are chosen to match RFB and RDRP respectively. Page 16 of 35 1/31/05 IR3087PBF IR3087 EXTERNAL COMPONENTS PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VPWMRMP and the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation (15). To achieve feed-forward voltage mode control, the resistor RPWMRMP should be connected to the input of the converter. VO (15) RPWMRMP = VIN * f SW * CPWMRMP * [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )] Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSThe DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as follows. L RL (16) RCS + = C CS + The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting input and the converter output. The resistor RCS- is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. RCS − = I CSIN + ∗ RCS + I CSIN − (17) If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less than 2 kΩ and therefore a larger CCS+ value is needed. Over Temperature Setting Resistors RHOTSET1 and RHOTSET2 The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine the relationship between the die temperature of phase IC and the temperature of the power converter according to the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the allowed maximum temperature from Equation (18). VHOTSET = 4.73 *10−3 * TJ + 1.46 (18) There are two ways to set the over temperature threshold, central setting and local setting. In the central setting, only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows. RHOTSET 2 = Page 17 of 35 RHOTSET 1 ∗ VHOTSET VBIAS − VHOTSET (19) 1/31/05 IR3087PBF Phase Delay Timing Resistors RPHASE1 and RPHASE2 The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of phase IC, as shown in Figure 3. If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as: R PHASEx 2 = RAPHASEx ∗ R PHASEx1 1 − RAPHASEx (20) Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3 The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one resistor per phase. Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from Equation (18). If the over temperature setting voltage is lower than the phase delay setting voltage, VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2, and connect HOTSET pin between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1, RPHASEx 2 = RPHASEx3 = ( RAPHASEx ∗ VBIAS − VHOTSET ) * RPHASEx1 VBIAS ∗ (1 − RAPHASEx ) VHOTSET ∗ RPHASEx1 VBIAS * (1 − RAPHASEx ) (21) (22) If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect HOTSET pin between RPHASEx1 and RPHASEx2. and connect RMPIN+ or RMPIN- between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1, R PHASEx 2 = RPHASEx 3 = (V HOTSET − RAPHASEx ∗ V BIAS ) ∗ R PHASEx1 V BIAS − V HOTSET RAPHASEx ∗ VBIAS * RPHASEx1 VBIAS − VHOTSET (23) (24) Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC 0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs. Page 18 of 35 1/31/05 IR3087PBF Opti-Phase Resistors ROP1 and ROP2 A resistor divider is used to program OPTIPHS pin voltage, which represents the load current threshold below which the phase is shut down to reduce the switching loss. Pre-select ROP1, and calculate ROP2 according to Equation (25), where IO_OP is the Opti-Phase shedding current threshold. ROP 2 = ROP1 ∗ [( I O _ OP / n) ∗ RL + VCS _ TOFST ] * GCS VBIAS − [( I O _ OP / n) ∗ RL + VCS _ TOFST ] ∗ GCS (25) The connection of OPTIPHS pin to VBIAS pin disables this function and keeps the phase always on. VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Resistors RFB and RDRP are chosen according to Equations (13) and (14), and the selection of compensation types depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or ALPolymer capacitors and running at lower frequency, type II compensation shown in Figure 8(a) is usually enough. While for the applications using ceramic capacitors and running at higher frequency, type III compensation shown in Figure 8(b) is preferred. For applications where AVP is not required, the compensation is the same as for the regular voltage mode control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type III compensation is required as shown in Figure 8(b) with RDRP and CDRP removed. CCP1 CC P1 VO+ RFB RCP CC P RCP CC P RFB1 CFB FB - VO+ RF B FB EAOU T EAOU T EAOU T EAOU T VDRP RD RP VD AC + VDRP RD RP VD AC + CDRP (a) Type II compensation (b) Type III compensation Figure 8. Voltage loop compensation network Page 19 of 35 1/31/05 IR3087PBF Type II Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine RCP and CCP from Equations (26) and (27), where LE and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. (2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP (26) RCP = VO * 1 + (2π * fC * C * RC ) 2 C CP = 10 ∗ L E ∗ C E RCP (27) CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by Equations (28) and (29), where RLE is the equivalent resistance of inductor DCR. . f C1 = RDRP 2π * CE ∗ GCS * RFB ∗ RLE (28) π Choose the desired crossover frequency fc around fc1 estimated by Equation (28) or choose fc between 1/10 and 1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB /Dec around the crossover frequency. Choose resistor RFB1 according to Equation (30), and determine CFB and RDRP from Equations (31) and (32). R FB1 = 1 to R FB 2 1 = 4π ∗ fC ∗ RFB1 R FB1 = 2 R FB 3 (30) (31) θ C1 = 90 − A tan(0.5) ∗ 180 (29) CFB C DRP = ( R FB + R FB1 ) ∗ C FB R DRP (32) RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Determine RCP and CCP from Equations (33) and (34). RCP = (2π ∗ fC )2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP VO 10 ∗ L E ∗ C E RCP (33) C CP = (34) CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Page 20 of 35 1/31/05 IR3087PBF Type III Compensation for Non-AVP Applications Resistor RFB is chosen according to Equations (13), and resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin θc. Calculate K factor from Equation (35), and determine the component values based on Equations (36) to (40), πθ (35) K = tan[ ∗ ( C + 1.5)] 4 180 RCP = RFB ∗ CCP = CCP1 = CFB = R FB1 = ( 2π ∗ LE ∗ CE ∗ fC ) 2 ∗ VPWMRMP VO ∗ K (36) K 2π ∗ fC ∗ RCP 1 2π ∗ fC ∗ K ∗ RCP K 2π ∗ fC ∗ RFB 1 2π ∗ f C ∗ K ∗ C FB (37) (38) (39) (40) CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ground is usually enough for the share loop compensation. Choose the crossover frequency of current share loop (fCI) based on the crossover frequency of voltage loop (fC), and determine the CSCOMP, CSCOMP = 0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI VO ∗ 2π ∗ fCI *1.05 *106 (41) Where FMI is the PWM gain in the current share loop, FMI = RPWMRMP * CPWMRMP * f SW *V PWMRMP (VI − VPWMRMP − VDAC ) * (VI − VDAC ) (42) Page 21 of 35 1/31/05 IR3087PBF DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER SPECIFICATIONS Input Voltage: VI=12 V DAC Voltage: VDAC=1.35 V No Load Output Voltage Offset: VO_NLOFST=20 mV Output Current: IO=105 ADC Maximum Output Current: IOMAX=120 ADC Output Impedance: RO=0.91 mΩ VCC Ready to VCC Power Good Delay: tVccPG=0-10mS Soft Start Time: tSS=2 mS Over Current Delay: tOCDEL