IR3500

IR3500 DATA SHEET XPHASE3TM VR11.0 & AMD PVID CONTROL IC DESCRIPTION The IR3500 Control IC combined with an xPHASE3 Phase IC provides a full featured and flexible way to implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a TM multiphase converter. The XPhase3 architecture implements a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. TM FEATURES • • • • • • • • • • • • • • • • • 1 to X phase operation with matching Phase IC VID Select pin configures AMD 5 or 6 bit PVID, Intel VR11 with/out startup to 1.1V Boot voltage 0.5% overall system set point accuracy Programmable 250kHz to 9MHz Daisy-chain digital phase timing clock oscillator frequency provides a per phase switching frequency of 250kHz to 1.5MHz without external components Programmable Dynamic VID Slew Rate Programmable VID Offset or No Offset Programmable Load Line Output Impedance High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us Programmable converter current limit during soft start, hiccup with delay during normal operation Central over voltage detection with programmable threshold and communication to phase ICs Over voltage signal output to system with overvoltage detection during powerup and normal operation Detection and protection of open remote sense line and open control loop IC bias linear regulator control with programmable output voltage and UVLO Programmable VRHOT function monitors temperature of power stage through a NTC thermistor Remote sense amplifier with true converter voltage sensing and less than 50uA bias current Simplified VR Ready output provides indication of proper operation and avoids false triggering Small thermally enhanced 32L 5mm x 5mm MLPQ package Optional To Converter FUSE 12V Q1 RVCCLFB1 RVCCLDRV RVCCLFB2 CVCCL 4.7uF ROVP1 Q3 SCR Q2 ROVP2 VCCL VR READY VIDSEL 32 31 29 28 27 30 26 PHSOUT VRRDY VCCLDRV VCCLFB VIDSEL VCCL PHSIN CLKOUT 25 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 2 3 4 5 6 7 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 LGND 24 23 22 21 20 19 18 17 ROSC CSS/DEL RVDAC ROCSET RVSETPT CVDAC ROSC / OVP IR3500 CONTROL IC HOTSET VOSEN+ ENABLE SS/DEL VDAC OCSET VSETPT IIN VDAC 6 Wire Bus to Phase ICs VOSEN- VRHOT 10 11 12 13 14 15 ENABLE VRHOT RFB1 RTHERMISTOR2 RHOTSET2 RFB RTHERMISTOR1 RHOTSET1 16 9 EAOUT VID0 VDRP VO FB CFB CDRP RDRP RCP CCP CCP1 VCC SENSE + To Load VSS SENSE - Close to Power Stage VCCL RFB2 Figure 1 – Application Circuit Page 1 of 47 June 12, 2007 IR3500 ORDERING INFORMATION Device IR3500MTRPBF Package 32 Lead MLPQ (5 x 5 mm body) * IR3500MPBF *Samples only 32 Lead MLPQ (5 x 5 mm body) 100 piece strips Order Quantity 3000 per reel ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature…………….. 0 C to 150 C o o Storage Temperature Range………………….-65 C to 150 C ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C o o PIN # 1-8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP IIN VSETPT OCSET VDAC SS/DEL ROSC/OVP LGND CLKOUT PHSOUT PHSIN VCCL VCCLFB VCCLDRV VRRDY VIDSEL VMAX 7.5V 3.5V 7.5V 7.5V 1.0V 7.5V 7.5V 7.5V 7.5V 7.5V 7.5V 3.5V 7.5V 3.5V 7.5V 7.5V n/a 7.5V 7.5V 7.5V 7.5V 3.5V 10V VCCL + 0.3V 7.5V VMIN -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 5mA 5mA 1mA 25mA 35mA 100mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA ISINK 1mA 1mA 50mA 1mA 1mA 1mA 25mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA June 12, 2007 Page 2 of 47 IR3500 RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75K o o ≤ ROSC ≤ 50.0 K ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CSS/DEL = 0.1µF +/-10%. PARAMETER VDAC Reference System Set-Point Accuracy (Deviation from Tables 2 & 4 per test circuit in Fig.3 and Table 3 per test circuit in Fig.2) Source & Sink Currents VR11 VIDx Input Threshold AMD VIDx Input Threshold VR11 VIDx Input Bias Current AMD 6-bit VIDx Pull-down Resistance VIDx OFF State Blanking Delay VIDSEL Threshold between AMD 5-bit VID and AMD 6-bit VID VIDSEL Threshold between AMD 6-bit VID and VR11 with Boot Voltage VIDSEL Threshold between VR11 with/out Boot Voltage VIDSEL Float Voltage VIDSEL Pull-up Resistance Oscillator ROSC Voltage CLKOUT High Voltage CLKOUT Low Voltage PHSOUT Frequency PHSOUT Frequency PHSOUT Frequency PHSOUT High Voltage PHSOUT Low Voltage PHSIN Threshold Voltage TEST CONDITION VID ≥ 1V 0.8V ≤ VID < 1V 0.5V ≤ VID < 0.8V 0.3V ≤ VID < 0.5V Include OCSET and VSETPT currents Float VIDSEL or tie VIDSEL to VCCL R(VIDSEL) = 6.49k or connect VIDSEL to LGND. Float VIDSEL, or connect VIDSEL to VCCL or LGND. 0V≤V(VIDx)≤2.5V. R(VIDSEL) = 6.49k Measure time till VRRDY drives low Note 3. MIN -0.5 -5 -8 -8 30 500 0.85 -1 100 0.5 0.48 TYP MAX 0.5 5 8 8 58 700 1.15 1 250 2.1 0.75 UNIT % mV mV mV µA mV V µA k µs V 44 600 1.00 0 175 1.3 0.6 Relative to VIDSEL float voltage. Note 3. Note 3. Relative to VIDSEL Threshold between VR11 with/out Boot Voltage 84 87 90 % 2.97 77 2.5 0.570 3.30 83 3.5 0.595 3.63 89 4.5 0.620 1 1 275 550 1.65 1 1 70 V % K V V V kHz kHz MHz V V % I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT)= 10 mA ROSC = 50.0 K ROSC = 24.5 K ROSC = 7.75 K I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT)= 1 mA Compare to V(VCCL) 225 450 1.35 250 500 1.50 30 50 Page 3 of 47 June 12, 2007 IR3500 PARAMETER Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) VRRDY Delay (TD4 + TD5) OC Delay Time SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Delay Comparator Threshold Delay Comparator Threshold TEST CONDITION MIN 1.0 0.8 0.3 0.5 75 0.7 35.0 2.5 10 3.6 50 85 10 2.8 150 3.0 -3 0.5 2 2 TYP 2.9 2.2 1.2 1.2 125 1.4 52.5 4.5 12 4.0 80 120 30 3.0 200 6.4 0 1.0 12 4 30 30 0.5 MAX 3.5 3.25 3.0 2.3 300 1.9 70.0 6.5 16 4.2 125 160 60 3.2 250 9.0 3 1.7 18 8 50 50 5.5 1 250 1 1 25.50 120 40 20 1.00 12 UNIT ms ms ms ms us V µA µA µA/µA V mV mV mV V mV MHz mV mA mA V/us uA uA V V mV mV µA µA dB MHz V/µs mA mA To reach 1.1V V(IIN) – V(OCSET) = 500 mV With FB = 0V, adjust V(SS/DEL) until EAOUT drives high Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling Delay Comparator Hysteresis VID Sample Delay Comparator Threshold Discharge Comp. Threshold Remote Sense Differential Amplifier Unity Gain Bandwidth Note 1 Input Offset Voltage 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Source Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Sink Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Slew Rate 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Note1 VOSEN+ Bias Current 0.5 V < V(VOSEN+) < 1.6V VOSEN- Bias Current -0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes VOSEN+ Input Voltage Range V(VCCL)=7V High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Error Amplifier Input Offset Voltage Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current ROSC= 24.5 K DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current -1 -1 23.00 100 20 7 0.40 5 0 0 24.25 110 30 12 0.85 8 Page 4 of 47 June 12, 2007 IR3500 PARAMETER Minimum Voltage Maximum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input VR 11 Threshold Voltage VR 11 Threshold Voltage VR 11 Hysteresis AMD Threshold Voltage AMD Threshold Voltage AMD Hysteresis Bias Current Blanking Time TEST CONDITION Measure V(VCCL) – V(EAOUT) Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUT) = V(VCCL) to VRRDY = low. ENABLE rising ENABLE falling ENABLE rising ENABLE falling 0V ≤ V(ENABLE) ≤ 3.3V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 MIN 500 125 TYP 120 780 300 MAX 250 950 600 UNIT mV mV mV 8 Pulses 825 775 25 1.1 1.05 30 -5 75 850 800 50 1.2 1.14 50 0 250 875 825 75 1.3 1.23 80 5 400 mV mV mV V V mV µA ns Over-Current Comparator Input Offset Voltage 1V ≤ V(OCSET) ≤ 3.3V OCSET Bias Current ROSC= 24.5 K Over-Current Delay Counter ROSC = 7.75 K (PHSOUT=1.5MHz) Over-Current Delay Counter ROSC = 15.0 K (PHSOUT=800kHZ) Over-Current Delay Counter ROSC = 50.0 K (PHSOUT=250kHz) Over-Current Limit Amplifier Input Offset Voltage Transconductance Note 1 Sink Current Unity Gain Bandwidth Over Voltage Protection (OVP) Comparators Threshold at Power-up Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(IIN) transition to > 0.9 * V(VCCL). IIN Pull-up Resistance Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP) Page 5 of 47 -30 23.25 -13 24.50 4096 2048 1024 0 1.00 55 2.00 1.73 125 3 1.73 50 90 0 25.75 mV µA Cycle Cycle Cycle mV mA/V uA kHz V mV mV V mV ns -10 0.50 35 0.75 1.60 105 -13 1.70 25 10 1.75 75 3.00 1.83 145 20 1.75 75 180 5 90 15 300 ns 0 0 1.2 0.2 V V June 12, 2007 IR3500 PARAMETER VDRP Buffer Amplifier Input Offset Voltage Source Current Sink Current Unity Gain Bandwidth Slew Rate IIN Bias Current VRRDY Output Output Voltage Leakage Current Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents VRHOT Comparator Threshold Voltage HOTSET Bias Current Hysteresis Output Voltage VRHOT Leakage Current VCCL Regulator Amplifier Reference Feedback Voltage VCCLFB Bias Current VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis General VCCL Supply Current TEST CONDITION V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN) ≤ 3.3V Note 1 Note 1 MIN -7 2 0.2 TYP 0 0.4 8 4.7 0 150 0 150 V(VO) < [V(VOSEN+) – V(LGND)] / 2 Compare to V(VCCL) 35 87.5 0.36 V(VO) = 100mV 200 200 60 90.0 0.40 500 MAX 7 30 0.6 UNIT mV mA mA MHz V/µs µA mV µA mV mV % V uA -1 I(VRRDY) = 4mA V(VRRDY) = 5.5V 1 300 10 250 85 92.5 0.44 700 1.584 -1 75 I(VRHOT) = 30mA V(VRHOT) = 5.5V 1.15 -1 10 90 82 7 3.0 1.600 0 100 150 0 1.19 0 30 94 86 8.25 6.5 1.616 1 125 400 10 1.23 1 98 90 9.5 10.0 V µA mV mV µA V uA mA % % % mA Compare to V(VCCL) Compare to V(VCCL) Compare to V(VCCL) Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors Note 3: See VIDSEL Functionality Table Page 6 of 47 June 12, 2007 IR3500 SYSTEM SET POINT TEST IR3500 VDAC BUFFER AMPLIFIER + ERROR AMPLIFIER EAOUT 1k + FB VSETPT VDAC RVDAC OCSET ROCSET FAST VDAC ISOURCE ISINK - IVDAC IVSETPT IROSC IROSC IOCSET CVDAC IROSC REMOTE SENSE AMPLIFIER VOSEN+ VOSEN+ - Figure 2 - System Set Point Test Circuit for VR11 VID IR3500 FAST VDAC ISOURCE ISINK IVDAC IVSETPT IROSC IROSC IROSC REMOTE SENSE AMPLIFIER VOSEN+ VOSEN+ - Figure 3 - System Set Point Test Circuit for AMD VIDs (VDAC shifted +50 mV) Page 7 of 47 June 12, 2007 + CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER 0.6V LGND - + - VDAC BUFFER AMPLIFIER + + - CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER 0.6V LGND ROSC VO ROSC EAOUT SYSTEM SET POINT VOSNSVOLTAGE ERROR AMPLIFIER EAOUT 1k FB VSETPT R VSETPT VDAC OCSET ROCSET RVDAC - IOCSET CVDAC ROSC VO ROSC EAOUT SYSTEM SET POINT VOSNSVOLTAGE IR3500 PIN DESCRIPTION PIN# 1-8 9 10 11 12 13 14 15 16 17 18 19 PIN SYMBOL VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP IIN VSETPT PIN DESCRIPTION Inputs to VID D to A Converter. Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin as the logic state will be undefined. Open collector output of the VRHOT comparator which drives low if HOTSET pin voltage is lower than 1.6V. Connect external pull-up. A resistor divider including thermistor senses the temperature, which is used for VRHOT comparator. Remote sense amplifier input. Connect to ground at the load. Remote sense amplifier input. Connect to output at the load. Remote sense amplifier output. Inverting input to the error amplifier. Output of the error amplifier. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance. Average current input from the phase IC(s). This pin is also used to communicate over voltage condition to phase ICs. Error amplifier non-inverting input. Converter output voltage can be decreased from the VDAC voltage with an external resistor connected between VDAC and this pin (there is an internal sink current at this pin). Programs the constant converter output current limit and hiccup over-current thresholds through an external resistor tied to VDAC and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC to program the threshold higher than the possible signal into the IIN pin from the phase ICs but no greater than VCCL – 2V (do not float this pin as improper operation will occur). Regulated voltage programmed by the VID inputs. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. Programs converter startup and over current protection delay timing. It is also used to compensate the constant output current loop during soft start. Connect an external capacitor to LGND to program. Connect a resistor to LGND to program oscillator frequency and OCSET, VSETPT and VDAC bias currents. Oscillator frequency equals switching frequency per phase. The pin voltage is 0.6V during normal operation and higher than 1.6V if over-voltage condition is detected. Local Ground for internal circuitry and IC substrate connection. Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of phase ICs. Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first phase IC. Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC. Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. 20 OCSET 21 VDAC 22 SS/DEL 23 ROSC/OVP 24 25 26 27 28 29 LGND CLKOUT PHSOUT PHSIN VCCL VCCLFB Page 8 of 47 June 12, 2007 IR3500 30 31 32 VCCLDRV VRRDY VIDSEL Output of the VCCL regulator error amplifier to control external transistor. The pin senses 12V power supply through a resistor. Open collector output that drives low during startup and under any external fault condition. Connect external pull-up. The pin configures VIDs for AMD 6-bit, Intel VR11 8-bit with 1.1V Boot voltage, Intel VR11 8-bit without 1.1V Boot voltage or AMD 5-bit Opteron. SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the XPhase3 architecture is shown in Figure 4. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. TM GATE DRIVE VOLTAGE VIN PHSOUT CONTROL IC CLOCK GENERATOR CLKOUT PHASE IC CLKIN CLK Q D 1 2 1 RESET DOMINANT D R Q 4 5 VCC VCCH GATEH SW COUT CBST PHSOUT PHSIN PHSIN VOSNS+ VOUT PWM COMPARATOR EAIN 2 + CLK Q 3 VCCL GND GATEL PWM LATCH VID6 VO LDO AMPLIFIER VDAC LGND ERROR AMPLIFIER + + 2 1 2 + 3 + REMOTE SENSE AMPLIFIER ENABLE RAMP DISCHARGE CLAMP BODY BRAKING COMPARATOR + - PGND VOSNS- + EAOUT RCOMP CCOMP1 CCOMP RFB1 RFB 3K + CFB FB RVSETPT DACIN PHSOUT RDRP RDRP1 IVSETPT IROSC + - VDRP AMP VSETPT CDRP PHASE IC CLKIN CLK Q D VDRP IIN PHSIN 1 RESET DOMINANT D R Q 4 5 PWM COMPARATOR EAIN ENABLE CLK Q PWM LATCH VID6 + RAMP DISCHARGE CLAMP BODY BRAKING COMPARATOR + - SHARE ADJUST ERROR AMPLIFIER ISHARE 3K VID6 VID6 + - CURRENT SENSE AMPLIFIER CSIN+ + + VID6 VID6 + DACIN Figure 4 - PWM Block Diagram Page 9 of 47 - VID6 VID6 + + - - - ISHARE + VDAC - + - - SHARE ADJUST ERROR AMPLIFIER VID6 VID6 + - CURRENT SENSE AMPLIFIER CSIN+ CCS RCS CSIN- VCC VCCH GATEH CBST SW VCCL GATEL PGND CCS RCS CSIN- June 12, 2007 IR3500 Frequency and Phase Timing Control The oscillator and system clock frequency is programmable from 250kHz to 9MHZ by an external resistor (ROSC). The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 5 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC as shown in Figure 23. The clock frequency equals the number of phase times the switching frequency. Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 5 - Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set; the PWM ramp voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage the PWM latch is reset. This turns off the high side driver, then turns on the low side driver after the non-overlap time, and activates the ramp discharge clamp. The ramp discharge clamp quickly discharges the PWM ramp capacitor to the output voltage of the share adjust amplifier in the phase IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of Page 10 of 47 June 12, 2007 IR3500 most systems. The inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 6 depicts PWM operating waveforms under various conditions. The error amplifier is a high speed amplifier with 110 dB of open loop gain. It is not unity gain stable. PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID FAULT) STEADY-STATE OPERATION Figure 6 - PWM Operating Waveforms Body Braking TM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. This patented method is referred to as “body braking” and is accomplished through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is, Page 11 of 47 June 12, 2007 IR3500 vC ( s ) = vL ( s ) 1 RL + sL = iL ( s ) 1 + sRCS CCS 1 + sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. vL iL L RCS Current Sense Amp RL CCS c vCS VO CO CSOUT Figure 7 - Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is nominally 32.5 and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3K resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the current sense error. The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This calibration algorithm creates ripple on ISHARE bus with a frequency of fsw / 896 in a multiphase architecture. Page 12 of 47 June 12, 2007 IR3500 Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. IR3500 THEORY OF OPERATION Block Diagram The Block diagram of the IR3500 is shown in Figure 8, and specific features are discussed in the following sections. VID Control The AMD 6-bit VID, VR11 8-bit VID, and AMD Opteron 5-bit VID are shown in Tables 2 to 4 respectively, and are selected by different connections of VIDSEL pin shown in Table 1. The VID pins require an external bias voltage and should not be floated. The VID input comparators monitor the VID pins and control the Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error amplifier and remote sense differential amplifier are post-package trimmed to provide 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system accuracy, which has a wider tolerance. VIDs of less than 0.5V are not supported. The IR3500 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. Adaptive Voltage Positioning Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 9. The output voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference voltage can be programmed to have a constant DC offset bellow the VDAC by connecting RSETPT between VDAC and VSETPT. The IVSETPT is controlled by the ROSC as shown in Figure 24. The voltage at the VDRP pin is a buffered version of the share bus IIN and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP. Since the error amplifier will force the loop to maintain FB to be equal to the VSETPT, an additional current will flow into the FB pin equal to (VDRP-VSETPT) / RDRP. When the load current increases, the adaptive positioning voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and therefore independent of the VDAC voltage. Inductor DCR Temperature Compensation A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. Page 13 of 47 June 12, 2007 VCCL ENABLE VBIAS ENABLE COMPARATOR + VCCL REGULATOR AMPLIFIER + 80mV 120mV 4.0V SAMPLE DELAY VCCLFB 1.19V 0.94 0.86 VCCL OUTPUT COMPARATOR + - VCCL UVLO 3.5k VIDSEL VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID2 VID1AMD 1.0V VID0INTEL 0.6V VID1 VID0 FAST VDAC S OV FAULT R Q VCCL UVLO CLKOUT VID0 CLKOUT PHSOUT PHSIN PHSOUT PHSIN LGND OV@OPERATION FAULT 50mV VCCL-1.2V IROSC IROSC + VO VDAC BUFFER AMPLIFIER ISOURCE ISINK OPEN SENSE LINE DETECT COMPARATORS + - 25k 0.6V VCCLDRV OV@START ROSC BUFFER AMPLIFIER + ROSC/OVP VDAC VO - CURRENT SOURCE GENERATOR SS RESET + + 200mV OPEN SENSE LINE + - + OPEN DAISY CHAIN DYNAMIC VID DETECT COMPARATOR - - VID3 SAMPLE DELAY 3.2V OVER 130mV VOLTAGE 3mV COMPARATOR DETECTION PULSE + 1.6V REMOTE SENSE AMPLIFIER 25k 60mV VIDSEL DETECTION VCCL PULSE + VID7 INPUT VID VID6 COMPARATORS VID5 (1/8 SHOWN) + VID SAMPLE DELAY FAULT LATCH1 COMPARATOR + IDCHG 4.5uA IROSC OV@OPERATION S Q SET DOMINANT R VCCL UVLO POWER-UP OV 1.73V COMPARATOR 25k 25k + IVOSEN+ IVOSENIVOSENVCCL OPEN SENSE LINE DETECT COMPARATORS VCCL*0.9 ENABLE 0.4V + + + DIS - + VIDSEL 1.3uS VID FAULT BLANKING DIGITAL VID7 VIDSEL VBOOT TO ANALOG LATCH VID6 CONVERTER VID5 VBOOT Q S VIDSEL(1.1V) SET VBOOT VID4 DOMINANT DVID VID3 INTERNAL R VID2 VDAC VR11 NoBOOT VR11 BOOT S SOFT START 1.4V CLAMP DISABLE EAOUT FB VSETPT ISETPT OV FAULT LATCH OV FAULT - VIDSEL VIDSEL COMPARATORS 3.3V VIDSEL AMD 6-BIT R Q SET DOMINANT ERROR AMPLIFIER + 0.86 AMD 5-BIT - Float Voltage 0.6V LATCH VID FAULT VIDSEL VID FAULT LATCH OC LIMIT AMPLIFIER - SS/DEL + - VCCLDRV + - - - Page 14 of 47 Figure 8 - Block Diagram June 12, 2007 INTEL 850mV 800mV 250nS BLANKING DELAY COMPARATOR POWER OK LATCH S Q RESET DOMINANT OC after VRRDY DISABLE VID FAULT VID FAULT LATCH VCCL UVLO OC before VRRDY SS CLEARED FAULT LATCH1 S Q POWER NOT OK FAULT LATCH1 FAULT LATCH2 OV FAULT VRRDY AMD 1.2V 1.14V SS RESET SET DOMINANT R VRHOT COMPARATOR IROSC HOTSET VRHOT DISCHARGE COMPARATOR + R OC DELAY RESET 8-Pulse Delay OC DELAY PHSOUT COUNTER OC OPEN SENSE LINE OPEN DAISY CHAIN OPEN VOLTAGE LOOP UV CLEARED FAULT LATCH2 S Q + SS RESET 0.2V 1.08V + VCCL EAOUT OC LIMIT COMPARATOR VCCL UVLO SET DOMINANT R 1.6V 1.5V OV@START OV@OPERATION VCCL IIN OCSET IROSC VDRP AMPLIFIER VDRP IOCSET OV@START VOSEN+ VOSEN- IR3500 IR3500 TABLE 1 - VIDSEL FUNCTIONALITY VIDSEL Connection LGND ( 1.73V Page 25 of 47 June 12, 2007 IR3500 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT VOLTAGE (VOSEN+) 1.73V VID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V