IR3500AMTRPBF

IR3500A DATA SHEET XPHASE3TM VR11.0 & AMD PVID CONTROL IC DESCRIPTION The IR3500A Control IC combined with an xPHASE3 Phase IC provides a full featured and flexible way to implement a complete VR11.0 or AMD PVID power solution. The Control IC provides overall system control and interfaces with any number of Phase ICs which each drive and monitor a single phase of a TM multiphase converter. The XPhase3 architecture implements a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. TM FEATURES • • • • • • • • • • • • • • • • • • 1 to X phase operation with matching Phase IC VID Select pin configures AMD 5 or 6 bit PVID, Intel VR11 with/out startup to 1.1V Boot voltage 0.5% overall system set point accuracy Programmable 250kHz to 9MHz Daisy-chain digital phase timing clock oscillator frequency provides a per phase switching frequency of 250kHz to 1.5MHz without external components Programmable Dynamic VID Slew Rate Programmable VID Offset or No Offset Programmable Load Line Output Impedance High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us Programmable converter current limit during soft start, hiccup with delay during normal operation Central over voltage detection with programmable threshold and communication to phase ICs Over voltage signal output to system with overvoltage detection during powerup and normal operation Detection and protection of open remote sense line and open control loop IC bias linear regulator control with programmable output voltage and UVLO Programmable VRHOT function monitors temperature of power stage through a NTC thermistor Remote sense amplifier with true converter voltage sensing and less than 50uA bias current Simplified PGOOD output provides indication of proper operation and avoids false triggering Small thermally enhanced 32L 5mm x 5mm MLPQ package RoHS Compliant Optional To Converter F USE 12V Q1 RVCCLFB1 RVCCLDRV RVCCLFB2 CVCCL 4.7uF ROVP1 Q3 SCR Q2 ROVP2 VCCL PGOOD VIDSEL 32 31 30 29 28 27 VCCLDRV VCCLFB VIDSEL VCCL 26 PHSOUT CLKOUT PGOOD PHSIN 25 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 2 3 4 5 6 7 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 LGND 24 23 22 21 20 19 18 17 ROSC CSS/DEL RVDAC ROCSET RVSETPT CVDAC ROSC / OVP IR3500A CONTROL IC HOTSET VOSEN+ ENABLE SS/DEL VDAC OCSET VSETPT IIN VDAC 6 Wire Bus to Phase ICs VOSEN- VRHOT 9 10 11 12 13 14 15 ENABLE VRHOT RHOTSET2 RFB1 RFB RHOTSET1 VCC SENSE + CFB CDRP RDRP RCP CCP 16 EAOUT VID0 VDRP VO FB CCP1 To Load VSS SENSE - RFB2 RTHERMISTOR1 RTHERMISTOR2 Close to Power Stage Figure 1 – Application Circuit Page 1 of 48 July 28, 2009 IR3500A ORDERING INFORMATION Device IR3500A MTRPBF Package 32 Lead MLPQ (5 x 5 mm body) * IR3500A MPBF *Samples only 32 Lead MLPQ (5 x 5 mm body) 100 piece strips Order Quantity 3000 per reel ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature…………….. 0 C to 150 C o o Storage Temperature Range………………….-65 C to 150 C ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C o o PIN # 1-8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP IIN VSETPT OCSET VDAC SS/DEL ROSC/OVP LGND CLKOUT PHSOUT PHSIN VCCL VCCLFB VCCLDRV PGOOD VIDSEL VMAX 7.5V 3.5V 7.5V 7.5V 1.0V 7.5V 7.5V 7.5V 7.5V 7.5V 7.5V 3.5V 7.5V 3.5V 7.5V 7.5V n/a 7.5V 7.5V 7.5V 7.5V 3.5V 10V VCCL + 0.3V 7.5V VMIN -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 5mA 5mA 1mA 25mA 35mA 100mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA ISINK 1mA 1mA 50mA 1mA 1mA 1mA 25mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA July 28, 2009 Page 2 of 48 IR3500A RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75K o o ≤ ROSC ≤ 50.0 K ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CSS/DEL = 0.1µF +/-10%. PARAMETER VDAC Reference System Set-Point Accuracy (Deviation from Tables 2 & 4 per test circuit in Fig.3 and Table 3 per test circuit in Fig.2) Source & Sink Currents VR11 VIDx Input Threshold AMD VIDx Input Threshold VR11 VIDx Input Bias Current AMD 6-bit VIDx Pull-down Resistance VIDx OFF State Blanking Delay VIDSEL Threshold between AMD 5-bit VID and AMD 6-bit VID VIDSEL Threshold between AMD 6-bit VID and VR11 with Boot Voltage VIDSEL Threshold between VR11 with/out Boot Voltage VIDSEL Float Voltage VIDSEL Pull-up Resistance Oscillator ROSC Voltage CLKOUT High Voltage CLKOUT Low Voltage PHSOUT Frequency PHSOUT Frequency PHSOUT Frequency PHSOUT High Voltage PHSOUT Low Voltage PHSIN Threshold Voltage TEST CONDITION VID ≥ 1V 0.8V ≤ VID < 1V 0.5V ≤ VID < 0.8V 0.3V ≤ VID < 0.5V Include OCSET and VSETPT currents Float VIDSEL or tie VIDSEL to VCCL R(VIDSEL) = 6.49k or connect VIDSEL to LGND. Float VIDSEL, or connect VIDSEL to VCCL or LGND. 0V≤V(VIDx)≤2.5V. R(VIDSEL) = 6.49k Measure time till PGOOD drives low Note 3. MIN -0.5 -5 -8 -8 30 500 0.85 -1 100 0.5 0.48 TYP MAX 0.5 5 8 8 58 700 1.15 1 250 2.1 0.75 UNIT % mV mV mV µA mV V µA k µs V 44 600 1.00 0 175 1.3 0.6 Relative to VIDSEL float voltage. Note 3. Note 3. Relative to VIDSEL Threshold between VR11 with/out Boot Voltage 84 87 90 % 2.97 77 3.0 0.570 3.30 83 4.0 0.595 3.63 89 5.0 0.620 1 1 275 550 1.65 1 1 70 V % K V V V kHz kHz MHz V V % I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT)= 10 mA ROSC = 50.0 K ROSC = 24.5 K ROSC = 7.75 K I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT)= 1 mA Compare to V(VCCL) 225 450 1.35 250 500 1.50 30 50 Page 3 of 48 July 28, 2009 IR3500A PARAMETER Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Delay Comparator Threshold Delay Comparator Threshold TEST CONDITION MIN 1.0 0.8 0.3 0.5 75 0.7 35.0 2.5 10 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling TYP 2.9 2.2 1.2 1.2 125 1.4 52.5 4.5 12 3.75 80 110 30 3.0 150 3.0 -3 0.5 2 2 200 6.4 0 1.0 12 4 30 30 0.5 275 9.0 3 1.7 18 8 50 50 5.5 1 250 1 1 25.50 120 40 20 1.00 12 250 950 MAX 3.5 3.25 3.0 2.3 300 1.9 70.0 6.5 16 UNIT Ms Ms Ms Ms us V µA µA µA/µA V mV mV mV V mV MHz mV mA mA V/us uA uA V V mV mV µA µA dB MHz V/µs mA mA mV mV To reach 1.1V V(IIN) – V(OCSET) = 500 mV With FB = 0V, adjust V(SS/DEL) until EAOUT drives high Delay Comparator Hysteresis VID Sample Delay Comparator Threshold Discharge Comp. Threshold Remote Sense Differential Amplifier Unity Gain Bandwidth Note 1 Input Offset Voltage 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Source Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Sink Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Slew Rate 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Note1 VOSEN+ Bias Current 0.5 V < V(VOSEN+) < 1.6V VOSEN- Bias Current -0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes VOSEN+ Input Voltage Range V(VCCL)=7V High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Error Amplifier Input Offset Voltage Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current ROSC= 24.5 K DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current Minimum Voltage Maximum Voltage Measure V(VCCL) – V(EAOUT) -1 -1 23.00 100 20 7 0.40 5 500 0 0 24.25 110 30 12 0.85 8 120 780 Page 4 of 48 July 28, 2009 IR3500A PARAMETER Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input VR 11 Threshold Voltage VR 11 Threshold Voltage VR 11 Hysteresis AMD Threshold Voltage AMD Threshold Voltage AMD Hysteresis Bias Current Blanking Time TEST CONDITION Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUT) = V(VCCL) to PGOOD = low. ENABLE rising ENABLE falling ENABLE rising ENABLE falling 0V ≤ V(ENABLE) ≤ 3.3V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 MIN 125 TYP 300 MAX 600 UNIT mV 8 Pulses 825 775 25 1.1 1.05 30 -5 75 850 800 50 1.2 1.14 50 0 250 875 825 75 1.3 1.23 80 5 400 mV mV mV V V mV µA ns Over-Current Comparator Input Offset Voltage 1V ≤ V(OCSET) ≤ 3.3V OCSET Bias Current ROSC= 24.5 K Over-Current Delay Counter ROSC = 7.75 K (PHSOUT=1.5MHz) Over-Current Delay Counter ROSC = 15.0 K (PHSOUT=800kHZ) Over-Current Delay Counter ROSC = 50.0 K (PHSOUT=250kHz) Over-Current Limit Amplifier Input Offset Voltage Transconductance Note 1 Sink Current Unity Gain Bandwidth Over Voltage Protection (OVP) Comparators Threshold at Power-up Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(IIN) transition to > 0.9 * V(VCCL). IIN Pull-up Resistance Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP) Page 5 of 48 -30 23.25 -13 24.50 4096 2048 1024 0 1.00 55 2.00 1.73 130 3 1.73 50 90 0 25.75 mV µA Cycle Cycle Cycle mV mA/V uA kHz V mV mV V mV ns -10 0.50 35 0.75 1.60 110 -13 1.70 25 10 1.75 75 3.00 1.83 150 20 1.75 75 180 5 90 15 180 ns 0 0 1.2 0.2 V V July 28, 2009 IR3500A PARAMETER TEST CONDITION MIN VDRP Buffer Amplifier Input Offset Voltage V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V -5 Source Current 0.5V ≤ V(IIN) ≤ 3.3V 2 Sink Current 0.5V ≤ V(IIN) ≤ 3.3V 0.2 Unity Gain Bandwidth Note 1 Slew Rate Note 1 IIN Bias Current -1 PGOOD Output Output Voltage I(PGOOD) = 4mA Leakage Current V(PGOOD) = 5.5V Under Voltage Threshold-VO Reference to VDAC -380 decreasing Under Voltage Threshold-VO Reference to VDAC -315 increasing Under Voltage Threshold 25 Hysteresis VCCL_DRV Activation I(PG)=4mA, V(PG)