IR3500VMPBF

IR3500V DATA SHEET XPHASE3TM VR11.1 CPU VTT CONTROL IC DESCRIPTION The IR3500V Control IC combined with one or more xPhase3 MOSFET driver functions for a VR11.1 CPU VTT power supply. TM Phase IC implement the control and FEATURES • • • • • • • • • • • • • • • • 12V RVCCLFB1 RVCCLDRV RVCCLFB2 CVCCL 4.7uF 1 to X phase operation with matching Phase IC 0.7% overall system set point accuracy Programmable 250kHz to 9MHz Daisy-chain digital phase timing clock oscillator frequency provides a per phase switching frequency of 250kHz to 1.5MHz without external components Programmable Dynamic VID Slew Rate Programmable Load Line Output Impedance High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 12V/us Programmable converter current limit during soft start, hiccup with delay during normal operation Central over voltage detection with programmable threshold and communication to phase IC(s) Over voltage signal output to system with overvoltage detection during powerup and normal operation Detection and protection of open remote sense line and open control loop IC bias linear regulator control with programmable output voltage and UVLO Programmable VRHOT function monitors temperature of power stage through a NTC thermistor Remote sense amplifier with true converter voltage sensing and less than 50uA bias current Simplified PGOOD output provides indication of proper operation and avoids false triggering Small thermally enhanced 32L 5mm x 5mm MLPQ package RoHS Compliant PGOOD 28 31 27 26 PHSOUT 32 30 29 25 CLKOUT VCCLDRV VCCLFB VIDSEL PGOOD VCCL 1 2 3 PHSIN VID7 VID6 VID5 VID4 VID3 VID2 VID1 LGND 24 23 22 21 20 19 18 17 1 2 3 4 ROSC CSS/DEL RVDAC 16 15 ROCSET CVDAC 14 CSIN+ 13 VCC ROSC / OVP SS/DEL VID4 VID3 VID2 4 5 6 7 8 IR3500V VDAC OCSET VSETPT IIN C SIN- EAIN CIN SW 12 11 CBST2 10 9 COUT DISTRIBUTION IMPEDANCE L RCS CCS ISHARE DACIN LGND PHSIN PHSOUT CLKIN PGND VOUT SENSE+ VOUT+ VOSEN+ ENABLE VOSEN- VRHOT EAOUT VID0 HOTSET VDRP IR3505 GATEH BOOST GATEL VCCL VO 14 10 11 12 13 15 FB ENABLE VRHOT 16 9 5 6 7 RHOTSET2 RFB1 RFB CFB RDRP RCP CCP 8 VOUTCVCCL CCP1 RHOTSET1 VOUT SENSE- RFB2 RTHERMISTOR1 RTHERMISTOR2 Close to Power Stage Figure 1 – Single Phase VR11.1 CPU VTT Application Circuit Page 1 of 34 July 28, 2008 IR3500V ORDERING INFORMATION Device IR3500V MTRPBF Package 32 Lead MLPQ (5 x 5 mm body) * IR3500V MPBF *Samples only 32 Lead MLPQ (5 x 5 mm body) 100 piece strips Order Quantity 3000 per reel ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature…………….. 0 C to 150 C o o Storage Temperature Range………………….-65 C to 150 C ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C PIN # 1-8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP IIN VSETPT OCSET VDAC SS/DEL ROSC/OVP LGND CLKOUT PHSOUT PHSIN VCCL VCCLFB VCCLDRV PGOOD VIDSEL VMAX 7.5V 3.5V 7.5V 7.5V 1.0V 7.5V 7.5V 7.5V 7.5V 7.5V 7.5V 3.5V 7.5V 3.5V 7.5V 7.5V n/a 7.5V 7.5V 7.5V 7.5V 3.5V 10V VCCL + 0.3V 7.5V VMIN -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 5mA 5mA 1mA 25mA 35mA 100mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA ISINK 1mA 1mA 50mA 1mA 1mA 1mA 25mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA o o Page 2 of 34 July 28, 2008 IR3500V RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75K o o ≤ ROSC ≤ 50.0 K ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CSS/DEL = 0.1µF +/-10%. PARAMETER VDAC Reference System Set-Point Accuracy Source & Sink Currents VR11 VIDx Input Threshold VR11 VIDx Input Bias Current VIDSEL Pull-up Resistance Oscillator ROSC Voltage CLKOUT High Voltage TEST CONDITION Deviation from Table 1 per test circuit in Figure 2 Include OCSET and VSETPT currents Float VIDSEL Float VIDSEL. 0V ≤ V(VIDx) ≤ 2.5V. MIN -0.7 30 500 -1 3.0 0.570 44 600 0 4.0 0.595 TYP MAX 0.7 58 700 1 5.0 0.620 1 1 275 550 1.65 1 1 70 9.0 3 1.7 18 8 50 50 5.5 1 250 880 830 75 5 400 UNIT % µA mV µA K V V V kHz kHz MHz V V % MHz mV mA mA V/us uA uA V V mV mV mV mV µA ns I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). CLKOUT Low Voltage I(CLKOUT)= 10 mA PHSOUT Frequency ROSC = 50.0 K PHSOUT Frequency ROSC = 24.5 K PHSOUT Frequency ROSC = 7.75 K PHSOUT High Voltage I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) PHSOUT Low Voltage I(PHSOUT)= 1 mA PHSIN Threshold Voltage Compare to V(VCCL) Remote Sense Differential Amplifier Unity Gain Bandwidth Note 1 Input Offset Voltage 1V≤ V(VOSEN+) - V(VOSEN-) Source Current 1V≤ V(VOSEN+) - V(VOSEN-) Sink Current 1V≤ V(VOSEN+) - V(VOSEN-) Slew Rate 1V≤ V(VOSEN+) - V(VOSEN-) Note1 VOSEN+ Bias Current 1 V < V(VOSEN+) VOSEN- Bias Current -0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes VOSEN+ Input Voltage Range V(VCCL)=7V High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Enable Input VR 11 Threshold Voltage ENABLE rising VR 11 Threshold Voltage ENABLE falling VR 11 Hysteresis Bias Current 0V ≤ V(ENABLE) ≤ 3.3V Blanking Time Noise Pulse < 100ns will not register an ENABLE state change. Note 1 225 450 1.35 250 500 1.50 30 3.0 -3 0.5 2 2 50 6.4 0 1.0 12 4 30 30 0.5 830 780 25 -5 75 855 805 50 0 250 Page 3 of 34 July 28, 2008 IR3500V PARAMETER Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Delay Comparator Threshold Delay Comparator Threshold Delay Comparator Hysteresis VID Sample Delay Comparator Threshold Discharge Comp. Threshold Error Amplifier Input Offset Voltage FB Bias Current VSETPT Bias Current DC Gain Bandwidth Slew Rate Sink Current Source Current Minimum Voltage Maximum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Over-Current Comparator Input Offset Voltage OCSET Bias Current Over-Current Delay Counter Over-Current Delay Counter Over-Current Delay Counter Over-Current Limit Amplifier Input Offset Voltage Transconductance Sink Current Unity Gain Bandwidth Page 4 of 34 TEST CONDITION MIN 1.0 0.8 0.3 0.5 75 0.7 35.0 2.5 10 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling TYP 2.9 2.2 1.2 1.2 125 1.4 52.5 4.5 12 3.75 80 110 30 3.0 150 Measure V(FB) – V(VSETPT). Note 2 ROSC= 24.5 K Note 1 Note 1 Note 1 -1 -1 23.00 100 20 7 0.40 5 500 125 200 0 0 24.25 110 30 12 0.85 8 120 780 300 8 275 1 1 25.50 120 40 20 1.00 12 250 950 600 MAX 3.5 3.25 3.0 2.3 300 1.9 70.0 6.5 16 UNIT ms ms ms ms us V µA µA µA/µA V mV mV mV V mV mV µA µA dB MHz V/µs mA mA mV mV mV Pulses To reach 1.1V V(IIN) – V(OCSET) = 500 mV With FB = 0V, adjust V(SS/DEL) until EAOUT drives high Measure V(VCCL) – V(EAOUT) Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUT) = V(VCCL) to PGOOD = low. 1V ≤ V(OCSET) ≤ 3.3V ROSC= 24.5 K ROSC = 7.75 K (PHSOUT=1.5MHz) ROSC = 15.0 K (PHSOUT=800kHZ) ROSC = 50.0 K (PHSOUT=250kHz) -30 23.25 -13 24.50 4096 2048 1024 0 1.00 55 2.00 0 25.75 mV µA Cycle Cycle Cycle mV mA/V uA kHz Note 1 Note 1 -10 0.50 35 0.75 10 1.75 75 3.00 July 28, 2008 IR3500V PARAMETER TEST CONDITION Over Voltage Protection (OVP) Comparators Threshold at Power-up Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(IIN) transition to > 0.9 * V(VCCL). IIN Pull-up Resistance Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage V(VCCLDRV)=1.8V. Measure V(VCCL)V(ROSC/OVP) VDRP Buffer Amplifier Input Offset Voltage V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V Source Current 0.5V ≤ V(IIN) ≤ 3.3V Sink Current 0.5V ≤ V(IIN) ≤ 3.3V Unity Gain Bandwidth Note 1 Slew Rate Note 1 IIN Bias Current PGOOD Output Output Voltage I(PGOOD) = 4mA Leakage Current V(PGOOD) = 5.5V Under Voltage Threshold-VO Reference to VDAC decreasing Under Voltage Threshold-VO Reference to VDAC increasing Under Voltage Threshold Hysteresis VCCL_DRV Activation I(PG)=4mA, V(PG) 1.73V Page 21 of 34 July 28, 2008 IR3500V 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT VOLTAGE (VOSEN+) 1.73V VID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V