IR3502A

IR3502A DATA SHEET XPHASE3TM CONTROL IC DESCRIPTION The IR3502A control IC combined with an XPHASE3TM Phase IC provides a full featured and flexible way to implement a complete VR11.0 and VR11.1 power solution. The IR3502A provides overall system control and interfaces with any number of Phase ICs, each driving and monitoring a single phase. The XPhase3TM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. FEATURES                      1 to X phase operation with matching Phase IC 0.5% overall system set point accuracy Daisy-chain digital phase timing provides accurate phase interleaving without external components Programmable 250kHz to 9MHz clock oscillator frequency provides per phase switching frequency of 250kHz to 1.5MHz Programmable Dynamic VID Slew Rate Programmable VID Offset or No Offset Programmable Load Line Output Impedance High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 10V/us Programmable constant converter output current limit during soft start Hiccup over current protection with delay during normal operation Central over voltage detection and latch with programmable threshold and communication to phase ICs Over voltage signal output to system with overvoltage detection during powerup and normal operation Load current reporting Single NTC thermistor compensation for correct current reporting, OC Threshold, and Droop Detection and protection of open remote sense line Open control loop protection IC bias linear regulator controller Programmable VRHOT function monitors temperature of power stage through a NTC thermistor Remote sense amplifier with true converter voltage sensing Small thermally enhanced 32L 5mm x 5mm MLPQ package RoHS Compliant ORDERING INFORMATION Device IR3502AMTRPBF * IR3502AMPBF  Samples only Package 32 Lead MLPQ (5 x 5 mm body) 32 Lead MLPQ (5 x 5 mm body) Order Quantity 3000 per reel 100 piece strips Page 1 of 38 December 17, 2009 IR3502A APPLICATION CIRCUIT +12V Q2 12V VCCL CVCCL RVCCLDRV IIN PHSIN PGOOD IOUT 32 30 29 28 RMON CMON 31 27 26 25 PHSOUT CLKOUT VCCLDRV PGOOD VCCL RMON1 VOSEN1 2 3 4 5 6 7 8 IMON IIN PHSIN PHSOUT CLKOUT VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID7 VID6 VID5 VID4 VID3 VID2 VID1 GND ROSC 24 23 22 21 20 19 18 17 ROSC CSS/DEL RVDAC RVSETPT RTCMP3 CVDAC VDAC SS/DEL IR3502A VDAC VSETPT VDAC_BUFF VN HOTSET VOSEN+ ENABLE VOSEN- VRHOT EAOUT VID0 VDRP RTCMP1 VO RTHERM FB 10 11 12 13 14 15 ENABLE VRHOT 16 RTCMP2 RDRP RHOTSET1 RHOTSET3 9 CHOTSET RHOTSET2 RFB1 RFB CFB1 REA CEA1 CEA EAOUT VOSEN+ VOSEN- Figure 1: IR3502A Application Circuit IR3502A FAST VDAC ISOURCE ISINK - IVDAC IVSETPT IROSC IROSC IROSC REMOTE SENSE AMPLIFIER VOSEN+ + VOSEN- Figure 2 –System-set point measurements. Page 2 of 38 + CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER 0.6V LGND - + FB VSETPT VDAC VDAC BUFFER AMPLIFIER + ERROR AMPLIFIER EAOUT 1k RVDAC OCSET ROCSET IOCSET CVDAC ROSC VO ROSC EAOUT SYSTEM SET POINT VOSNSVOLTAGE December 17, 2009 IR3502A ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature……………..0 to 150oC Storage Temperature Range………………….-65oC to 150oC ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 Reflow Temperature…………………………….260oC PIN # 1-8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP VN VDAC_BUFF VSETPT VDAC SS/DEL ROSC/OVP LGND CLKOUT PHSOUT PHSIN VCCL IIN VCCLDRV PGOOD IMON VMAX 7.5V 3.5V 7.5V 7.5V 1.0V 7.5V 7.5V 7.5V 7.5V 7.5V 7.5V 3.5V 3.5V 3.5V 7.5V 7.5V n/a 7.5V 7.5V 7.5V 7.5V 7.5V 10V VCCL + 0.3V 3.5V VMIN -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.5V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 5mA 35mA 1mA 35mA 35mA 1mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 25mA ISINK 1mA 1mA 50mA 1mA 1mA 1mA 5mA 1mA 5mA 1mA 1mA 35mA 1mA 1mA 1mA 1mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA Page 3 of 38 December 17, 2009 IR3502A ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V ≤ VOSEN- ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ, CSS/DEL = 0.1F +/-10%. PARAMETER VDAC Reference System Set-Point Accuracy TEST CONDITION VID ≥ 1V 0.8V ≤ VID < 1V 0.5V ≤ VID < 0.8V Include OCSET and VSETPT currents MIN -0.5 -5 -8 30 500 -1 0.5 0.570 TYP MAX 0.5 +5 +8 58 700 1 2.1 0.620 1 1 275 550 1.65 1 1 70 9 0.6 20 UNIT % mV mV A mV A s V V V kHz kHz MHz V V % mV mA mA MHz V/s mV mA mA MHz V/s 67 mV Source & Sink Currents VIDx Input Threshold VIDx Input Bias Current 0V≤V(VIDx)≤2.5V. VIDx OFF State Blanking Delay Measure time till PGOOD drives low Oscillator ROSC Voltage CLKOUT High Voltage I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). CLKOUT Low Voltage I(CLKOUT)= 10 mA PHSOUT Frequency ROSC = 50.0 KΩ PHSOUT Frequency ROSC = 24.5 KΩ PHSOUT Frequency ROSC = 7.75 KΩ PHSOUT High Voltage I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) PHSOUT Low Voltage I(PHSOUT)= 1 mA PHSIN Threshold Voltage Compare to V(VCCL) VDAC Buffer Amplifier Input Offset Voltage V(VDAC_BUFF) – V(VDAC), 0.5V ≤ V(VDAC) ≤ 1.6V, < 1mA load Source Current 0.5V ≤ V(VDAC) ≤ 1.6V Sink Current 0.5V ≤ V(VDAC) ≤ 1.6V Unity Gain Bandwidth Note 1 Slew Rate Note 1 Thermal Compensation Amplifier Output Offset Voltage 0V ≤ V(IIN) – V(VDAC) ≤ 1.6V, 0.5V ≤ V(VDAC) ≤ 1.6V, Req/R2 = 2 Source Current 0.5V ≤ V(VDAC) ≤ 1.6V Sink Current 0.5V ≤ V(VDAC) ≤ 1.6V Unity Gain Bandwidth Note 1, Req/R2 = 2 Slew Rate Note 1 Current Report Amplifier Output Offset Voltage V(VDRP)–V(VDAC) = 0,225,450,900mV 44 600 0 1.3 0.595 225 450 1.35 250 500 1.50 30 -5 0.3 3.5 50 0 0.44 13 3.5 1.5 0 8 0.4 4.5 5.5 52 -10 3 0.3 2 10 15 0.5 7 37 Page 4 of 38 December 17, 2009 IR3502A PARAMETER TEST CONDITION Source Current 0.5V ≤ V(IMON) ≤ 0.9V Sink Resistance 0.5V ≤ V(IMON) ≤ 0.9V Unity Gain Bandwidth Note 1 Input Filter Time Constant Max Output Voltage Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time V(VDRP) – V(DACBUFF) = 1.67 mV SS/DEL to FB Input Offset With FB = 0V, adjust V(SS/DEL) until Voltage EAOUT drives high Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Relative to Charge Voltage, SS/DEL rising Delay Comparator Threshold Relative to Charge Voltage, SS/DEL falling Delay Comparator Threshold Delay Comparator Input Filter Delay Comparator Hysteresis VID Sample Delay Comparator Threshold Discharge Comp. Threshold Remote Sense Differential Amplifier Unity Gain Bandwidth Note 1 Input Offset Voltage 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Sink Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Source Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Slew Rate 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V VOSEN+ Bias Current 0.5 V < V(VOSEN+) < 1.6V VOSEN- Bias Current -0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Error Amplifier Input Offset Voltage Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current ROSC= 24.5 KΩ DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current Maximum Voltage Measure V(VCCL) – V(EAOUT) Page 5 of 38 MIN 5 5 TYP 9 10 1 1 1.09 2.9 2.2 1.2 1.2 125 1.4 52.5 4.5 12 4.0 80 120 5 30 3.0 200 6.4 0 1 9 4 160 2 MAX 15 17 UNIT mA kΩ MHz s V ms ms ms ms us V A A A/A V mV mV s mV V mV MHz mV mA mA V/us uA uA V mV mV A A dB MHz V/s mA mA mV 1.04 1.0 0.8 0.3 0.5 75 0.7 35.0 2.5 10 3.6 50 85 10 2.8 150 3.0 -3 0.4 3 2 1.145 3.5 3.25 3.0 2.3 300 1.9 70.0 6.5 16 4.2 125 160 60 3.2 275 9.0 3 2 20 8 100 275 2.5 50 1 1 25.50 120 40 20 1.00 12 950 1.5 -1 -1 23.00 100 20 7 0.40 5 500 0 0 24.25 110 30 12 0.85 8 780 December 17, 2009 IR3502A PARAMETER Minimum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input VR 11 Threshold Voltage VR 11 Threshold Voltage VR 11 Hysteresis Bias Current Blanking Time TEST CONDITION Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUT) = V(VCCL) to PGOOD = low. ENABLE rising ENABLE falling 0V ≤ V(ENABLE) ≤ 3.3V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 MIN 125 TYP 120 300 MAX 250 600 UNIT mV mV 8 Pulses 825 775 25 -5 75 850 800 50 0 250 875 825 75 5 400 mV mV mV A ns Over-Current Comparator Input Offset Voltage 1V ≤ V(IIN) ≤ 3.3V Input Filter Time Constant Over-Current Threshold VDRP-VDAC_BUFF Over-Current Delay Counter ROSC = 7.75 KΩ (PHSOUT=1.5MHz) Over-Current Delay Counter ROSC = 15.0 KΩ (PHSOUT=800kHz) Over-Current Delay Counter ROSC = 50.0 KΩ (PHSOUT=250kHz) Over-Current Limit Amplifier Input Offset Voltage Transconductance Note 1 Sink Current Unity Gain Bandwidth Note 1 Over Voltage Protection (OVP) Comparators Threshold at Power-up Measure at 1.5V VCCLDRV Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(IIN) transition to > 0.9 * V(VCCL). IIN Pull-up Resistance Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage ROSC = 7.75 KΩ. Measure V(VCCLDRV)-V(ROSC/OVP) @ 1.5V OVP Power-up High Voltage ROSC = 24.5 KΩ. Measure V(VCCLDRV)-V(ROSC/OVP) @ 1.5V Page 6 of 38 -40 1.07 -25 2 1.17 4096 2048 1024 0 1.00 55 2.00 1.21 125 3 1.73 50 90 -10 1.27 mV S V Cycle Cycle Cycle mV mA/V uA kHz V mV mV V mV nS -10 0.50 35 0.75 1.1 105 -13 1.70 25 10 1.75 75 3.00 1.30 145 20 1.75 75 180 5 90 15 180 Ω nS 0 .100 0 .240 1.2 .375 0.2 V V December 17, 2009 IR3502A PARAMETER PGOOD Output Output Voltage Leakage Current Under Voltage Threshold-VO decreasing Under Voltage Threshold-VO increasing Under Voltage Threshold Hysteresis VCCL_DRV Activation Threshold Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents VRHOT Comparator Threshold Voltage HOTSET Bias Current Hysteresis Output Voltage VRHOT Leakage Current VCCL Regulator Amplifier VCCL Output Voltage VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis General VCCL Supply Current TEST CONDITION I(PGOOD) = 4mA V(PGOOD) = 5.5V Reference to VDAC Reference to VDAC MIN TYP 150 0 -350 -290 25 I(PG)=4mA, V(PG) 1.73V 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT VOLTAGE (VOSEN+) 1.73V V ID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 16 Over-voltage protection with pre-charging converter output VID + 0.13V