IR3502MPBF

IR3502 DATA SHEET XPHASE3TM CONTROL IC DESCRIPTION The IR3502 control IC combined with an XPHASE3 Phase IC provides a full featured and flexible way to implement a complete VR11.0 and VR11.1 power solution. The IR3502 provides overall system control TM and interfaces with any number of Phase ICs, each driving and monitoring a single phase. The XPhase3 architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. TM FEATURES • • • • • • • • • • • • • • • • • • • • • • 1 to X phase operation with matching Phase IC 0.5% overall system set point accuracy Daisy-chain digital phase timing provides accurate phase interleaving without external components Programmable 250kHz to 9MHz clock oscillator frequency provides per phase switching frequency of 250kHz to 1.5MHz Programmable Dynamic VID Slew Rate Programmable VID Offset or No Offset Programmable Load Line Output Impedance High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 10V/us Programmable constant converter output current limit during soft start Hiccup over current protection with delay during normal operation Central over voltage detection and latch with programmable threshold and communication to phase ICs Over voltage signal output to system with overvoltage detection during powerup and normal operation Load current reporting Single NTC thermistor compensation for correct current reporting, OC Threshold, and Droop Detection and protection of open remote sense line Open control loop protection IC bias linear regulator controller Programmable VRHOT function monitors temperature of power stage through a NTC thermistor Remote sense amplifier with true converter voltage sensing Simplified VR Ready (VRRDY) output provides indication of proper operation Small thermally enhanced 32L 5mm x 5mm MLPQ package RoHS compliant ORDERING INFORMATION Device IR3502MTRPBF * IR3502MPBF • Samples only Package 32 Lead MLPQ (5 x 5 mm body) 32 Lead MLPQ (5 x 5 mm body) Order Quantity 3000 per reel 100 piece strips Page 1 of 39 July 28, 2009 IR3502 APPLICATION CIRCUIT 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 PHSOUT 25 CLKOUT VCCLDRV VCCLDRV VIDSEL VCCL VRRDY VCCLFB PHSOUT VRRDY PHSIN VCCL CLKOUT 1 2 3 4 5 6 7 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 LGND 24 23 22 21 20 19 18 17 PHSIN IMON IIN 1 2 3 4 5 6 7 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 GND ROSC 24 23 22 21 20 19 18 17 ROSC / OVP SS/DEL SS/DEL IR3500 VDAC OCSET VSETPT IIN IR3502 VDAC VSETPT VDAC_BUFF VN HOTSET VOSEN+ VOSEN+ ENABLE ENABLE VOSEN- VOSEN- VRHOT VRHOT EAOUT 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 Figure 1 – PIN difference between IR3500 and IR3502 16 EAOUT VID0 VDRP VID0 HOTSET VDRP VO VO FB FB +12V Q2 12V VCCL CVCCL RVCCLDRV IIN PHSIN VRRDY IOUT 32 30 29 28 27 26 PHSOUT RMON CLKOUT 31 25 CLKOUT CMON VRRDY VCCLDRV VCCL IIN PHSIN IMON VOSENVID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 2 3 4 5 6 7 8 VID7 VID6 VID5 VID4 VID3 VID2 VID1 PHSOUT RMON1 GND ROSC 24 23 22 21 20 19 18 17 ROSC CSS/DEL RVDAC RVSETPT RTCMP3 CVDAC VDAC SS/DEL IR3502 VDAC VSETPT VDAC_BUFF VN HOTSET VOSEN+ ENABLE VOSEN- VRHOT EAOUT VID0 VDRP RTCMP1 RTHERM VO FB 10 11 12 13 14 15 ENABLE VRHOT 16 RTCMP2 RDRP RHOTSET1 RHOTSET3 9 CHOTSET RFB1 RHOTSET2 RFB CFB1 REA CEA1 CEA EAOUT VOSEN+ VOSEN- Figure 2 – IR3502 Application Circuit Page 2 of 39 July 28, 2009 IR3502 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature……………..0 to 150 C o o Storage Temperature Range………………….-65 C to 150 C ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C o PIN # 1-8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NAME VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP VN VDAC_BUFF VSETPT VDAC SS/DEL ROSC/OVP LGND CLKOUT PHSOUT PHSIN VCCL IIN VCCLDRV VRRDY IMON VMAX 7.5V 3.5V 7.5V 7.5V 1.0V 7.5V 7.5V 7.5V 7.5V 7.5V 7.5V 3.5V 3.5V 3.5V 7.5V 7.5V n/a 7.5V 7.5V 7.5V 7.5V 7.5V 10V VCCL + 0.3V 3.5V VMIN -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.5V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA 1mA 5mA 5mA 35mA 1mA 35mA 35mA 1mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 25mA ISINK 1mA 1mA 50mA 1mA 1mA 1mA 5mA 1mA 5mA 1mA 1mA 35mA 1mA 1mA 1mA 1mA 1mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA Page 3 of 39 July 28, 2009 IR3502 ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V ≤ VOSEN- ≤ o o 0.3V, 0 C ≤ TJ ≤ 100 C, 7.75K ≤ ROSC ≤ 50.0 K , CSS/DEL = 0.1µF +/-10%. PARAMETER VDAC Reference System Set-Point Accuracy TEST CONDITION VID ≥ 1V 0.8V ≤ VID < 1V 0.5V ≤ VID < 0.8V VSETPT connected to VDAC MIN -0.5 -5 -8 30 500 -1 0.5 0.570 TYP MAX 0.5 +5 +8 58 700 1 2.1 0.620 1 1 275 550 1.65 1 1 70 9 0.6 20 UNIT % mV mV µA mV µA µs V V V kHz kHz MHz V V % mV mA mA MHz V/µs 10 15 0.5 7 mV mA mA MHz V/µs 67 mV Source & Sink Currents VIDx Input Threshold VIDx Input Bias Current 0V≤V(VIDx)≤2.5V. VIDx OFF State Blanking Delay Measure time till VRRDY drives low Oscillator ROSC Voltage CLKOUT High Voltage I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). CLKOUT Low Voltage I(CLKOUT)= 10 mA PHSOUT Frequency ROSC = 50.0 K PHSOUT Frequency ROSC = 24.5 K PHSOUT Frequency ROSC = 7.75 K PHSOUT High Voltage I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) PHSOUT Low Voltage I(PHSOUT)= 1 mA PHSIN Threshold Voltage Compare to V(VCCL) VDAC Buffer Amplifier Input Offset Voltage V(VDAC_BUFF) – V(VDAC), 0.5V ≤ V(VDAC) ≤ 1.6V, < 1mA load Source Current 0.5V ≤ V(VDAC) ≤ 1.6V Sink Current 0.5V ≤ V(VDAC) ≤ 1.6V Unity Gain Bandwidth Note 1 Slew Rate Note 1 Thermal Compensation Amplifier Output Offset Voltage 0V ≤ V(IIN) – V(VDAC) ≤ 1.6V, 0.5V ≤ V(VDAC) ≤ 1.6V, Req/R2 = 2 Source Current 0.5V ≤ V(VDAC) ≤ 1.6V Sink Current 0.5V ≤ V(VDAC) ≤ 1.6V Unity Gain Bandwidth Note 1, Req/R2 = 2 Slew Rate Note 1 Current Report Amplifier Output Offset Voltage V(VDRP)–V(VDAC) = 0,225,450,900mV 44 600 0 1.3 0.595 225 450 1.35 250 500 1.50 30 -5 0.3 3.5 50 0 0.44 13 3.5 1.5 0 8 0.4 4.5 5.5 52 -10 3 0.3 2 37 Page 4 of 39 July 28, 2009 IR3502 PARAMETER TEST CONDITION Source Current 0.5V ≤ V(IMON) ≤ 0.9V Sink Resistance 0.5V ≤ V(IMON) ≤ 0.9V Unity Gain Bandwidth Note 1 Input Filter Time Constant Max Output Voltage Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) VRRDY Delay (TD4 + TD5) OC Delay Time V(VDRP) – V(DACBUFF) = 1.67 mV SS/DEL to FB Input Offset W ith FB = 0V, adjust V(SS/DEL) until Voltage EAOUT drives high Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Relative to Charge Voltage, SS/DEL rising Delay Comparator Threshold Relative to Charge Voltage, SS/DEL falling Delay Comparator Threshold Delay Comparator Input Filter Delay Comparator Hysteresis VID Sample Delay Comparator Threshold Discharge Comp. Threshold Remote Sense Differential Amplifier Unity Gain Bandwidth Note 1 Input Offset Voltage 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Sink Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Source Current 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V Slew Rate 0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.6V VOSEN+ Bias Current 0.5 V < V(VOSEN+) < 1.6V VOSEN- Bias Current -0.3V ≤ VOSEN- ≤ 0.3V, All VID Codes High Voltage V(VCCL) – V(VO) Low Voltage V(VCCL)=7V Error Amplifier Input Offset Voltage Measure V(FB) – V(VSETPT). Note 2 FB Bias Current VSETPT Bias Current ROSC= 24.5 K DC Gain Note 1 Bandwidth Note 1 Slew Rate Note 1 Sink Current Source Current Maximum Voltage Measure V(VCCL) – V(EAOUT) Page 5 of 39 MIN 5 5 TYP 9 10 1 1 1.09 2.9 2.2 1.2 1.2 125 1.4 52.5 4.5 12 4.0 80 120 5 30 3.0 200 6.4 0 1 9 4 160 2 MAX 15 17 UNIT mA k MHz µs V ms ms ms ms us V µA µA µA/µA V mV mV µs mV V mV MHz mV mA mA V/us µA µA V mV mV µA µA dB MHz V/µs mA mA mV 1.04 1.0 0.8 0.3 0.5 75 0.7 35.0 2.5 10 3.6 50 85 10 2.8 150 3.0 -3 0.4 3 2 1.145 3.5 3.25 3.0 2.3 300 1.9 70.0 6.5 16 4.2 125 160 60 3.2 275 9.0 3 2 20 8 100 275 2.5 50 1.5 -1 -1 23.00 100 20 7 0.40 5 500 0 1 0 1 24.25 25.50 110 120 30 40 12 20 0.85 1.00 8 12 780 950 July 28, 2009 IR3502 PARAMETER Minimum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input VR 11 Threshold Voltage VR 11 Threshold Voltage VR 11 Hysteresis Bias Current Blanking Time TEST CONDITION Measure V(VCCL)- V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUT) = V(VCCL) to VRRDY = low. ENABLE rising ENABLE falling 0V ≤ V(ENABLE) ≤ 3.3V Noise Pulse < 100ns will not register an ENABLE state change. Note 1 MIN 125 TYP 120 300 8 MAX 250 600 UNIT mV mV Pulses 825 775 25 -5 75 850 800 50 0 250 875 825 75 5 400 mV mV mV µA ns Over-Current Comparator Input Offset Voltage 1V ≤ V(IIN) ≤ 3.3V Input Filter Time Constant Over-Current Threshold VDRP-VDAC_BUFF Over-Current Delay Counter ROSC = 7.75 K (PHSOUT=1.5MHz) Over-Current Delay Counter ROSC = 15.0 K (PHSOUT=800kHz) Over-Current Delay Counter ROSC = 50.0 K (PHSOUT=250kHz) Over-Current Limit Amplifier Input Offset Voltage Transconductance Note 1 Sink Current Unity Gain Bandwidth Note 1 Over Voltage Protection (OVP) Comparators Threshold at Power-up Measure at 1.5V VCCLDRV Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(IIN) transition to > 0.9 * V(VCCL). IIN Pull-up Resistance Propagation Delay to OVP Measure time from V(VO) > V(VDAC) (250mV overdrive) to V(ROSC/OVP) transition to >1V. OVP High Voltage Measure V(VCCL)-V(ROSC/OVP) OVP Power-up High Voltage ROSC = 7.75 K . Measure V(VCCLDRV)-V(ROSC/OVP) @ 1.5V OVP Power-up High Voltage ROSC = 24.5 K . Measure V(VCCLDRV)-V(ROSC/OVP) @ 1.5V Page 6 of 39 -40 1.07 -25 2 1.17 4096 2048 1024 0 1.00 55 2.00 1.21 125 3 1.73 50 90 -10 1.27 mV µs V Cycle Cycle Cycle mV mA/V uA kHz V mV mV V mV ns -10 0.50 35 0.75 1.1 105 -13 1.70 25 10 1.75 75 3.00 1.30 145 20 1.75 75 180 5 90 15 180 ns 0 .100 0 .240 1.2 .375 0.2 V V July 28, 2009 IR3502 PARAMETER VRRDY Output Output Voltage Leakage Current Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents VRHOT Comparator Threshold Voltage HOTSET Bias Current Hysteresis Output Voltage VRHOT Leakage Current VCCL Regulator Amplifier VCCL Output Voltage VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis General VCCL Supply Current TEST CONDITION I(VRRDY) = 4mA V(VRRDY) = 5.5V 150 V(VO) < [V(VOSEN+) – V(LGND)] / 2 Compare to V(VCCL) 30 87.5 0.36 V(VO) = 100mV 200 MIN TYP 150 0 200 55 90.0 0.40 500 MAX 300 10 250 80 92.5 0.44 700 UNIT mV µA mV mV % V uA 1.584 -1 75 I(VRHOT) = 30mA V(VRHOT) = 5.5V 6.576 10 6.12 5.168 0.85 4 1.600 0 100 150 0 6.8 30 6.392 5.44 0.95 8 1.616 1 125 400 10 7.031 6.664 5.712 1.05 12 V µA mV mV µA V mA V V V mA Compare to V(VCCL) Compare to V(VCCL) Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offsets errors Page 7 of 39 July 28, 2009 IR3502 PIN DESCRIPTION PIN# 1-8 9 10 11 12 13 14 15 16 17 18 19 20 PIN SYMBOL VID7-0 ENABLE VRHOT HOTSET VOSENVOSEN+ VO FB EAOUT VDRP VN VDAC_BUFF VSETPT PIN DESCRIPTION Inputs to VID D to A Converter. Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float this pin as the logic state will be undefined. Open collector output of the VRHOT comparator which drives low if HOTSET pin voltage is lower than 1.6V. Connect external pull-up. A resistor divider including thermistor senses the temperature, which is used for VRHOT comparator. Remote sense amplifier input. Connect to ground at the load. Remote sense amplifier input. Connect to output at the load. Remote sense amplifier output. Used for OV detection Inverting input to the Error Amplifier. Output of the error amplifier. Buffered, scaled and thermally compensated IIN signal. Connect an external RC network to FB to program converter output impedance. Node for DCR thermal compensation network. Buffered VDAC. Error amplifier non-inverting input. Converter output voltage can be decreased from the VDAC voltage with an external resistor connected between VDAC and this pin (there is an internal sink current at this pin). Regulated voltage programmed by the VID inputs. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. Programs converter startup and over current protection delay timing. It is also used to compensate the constant output current loop during soft start. Connect an external capacitor to LGND to program. Connect a resistor to LGND to program oscillator frequency and VSETPT bias current. Oscillator frequency equals switching frequency per phase. The pin voltage is 0.6V during normal operation and higher than 1.6V if an over-voltage condition is detected. Local Ground for internal circuitry and IC substrate connection. Clock frequency is the switching frequency multiplied by phase number. Connect to CLKIN pins of phase ICs. Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first phase IC. Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC. Voltage regulator and IC power input. Connect a decoupling capacitor to LGND. Average current input from the phase IC(s). This pin is also used to communicate over voltage condition to phase ICs. Output of the VCCL regulator error amplifier to control external transistor. The pin senses 12V power supply through a resistor. Open collector output that drives low during startup and under any external fault condition. Connect external pull-up. Voltage at this pin is proportional to load current. July 28, 2009 21 VDAC 22 SS/DEL 23 ROSC/OVP 24 25 26 27 28 29 30 31 32 LGND CLKOUT PHSOUT PHSIN VCCL IIN VCCLDRV VRRDY IMON Page 8 of 39 IR3502 SYSTEM THEORY OF OPERATION System Description The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three analog buses, i.e., VDAC, EA, IIN. The digital buses are responsible for switching frequency determination and accurate phase timing control without any external component. The analog buses are used for PWM control and current sharing among interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by each phase of the converter, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, Phase disable circuit, current sensing and sharing, etc. GATE DRIVE VOLTAGE VIN PHSOUT CONTROL IC CLOCK GENERATOR CLKOUT PHASE IC CLKIN CLK Q D 1 2 RESET U246 DOMINANT D Q R VCC VCCH GATEH VID6 OFF SW COUT CBST PHSOUT PHSIN PHSIN VOSNS+ VOUT PWM COMPARATOR EAIN CLK Q 3 + DFFRH VCCL GND GATEL VID6 OFF PWM LATCH VID6 VO VDAC LGND SHARE ADJUST ERROR AMPLIFIER ISHARE RCOMP RFB1 RFB + 2 + REMOTE SENSE AMPLIFIER ENABLE RAMP DISCHARGE CLAMP BODY BRAKING COMPARATOR PGND VOSNS- + EAOUT 3K + FB RVSETPT CCOMP CFB DACIN PHSOUT RDRP RDRP1 IROSC IVSETPT VSETPT CDRP PHASE IC CLKIN CLK Q D 1 RESET U248 DOMINANT D Q R IMON VDAC PHSIN VDRP AMP Thermal Compensation + VDRP VN RTHRM PWM COMPARATOR EAIN ENABLE VID6 OFF SW VCCL GATEL VID6 OFF + - CLK Q 3 + DFFRH PWM LATCH VID6 + IIN RAMP DISCHARGE CLAMP BODY BRAKING COMPARATOR SHARE ADJUST ERROR AMPLIFIER ISHARE 3K VID6 VID6 + - CURRENT SENSE AMPLIFIER CSIN+ + + VID6 VID6 + DACIN Figure 3 System Block Diagram PWM Control Method TM The PWM block diagram of the XPhase3 architecture is shown in Figure 3. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the control IC is used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. Frequency and Phase Timing Control The oscillator is located in the control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an external resistor. The control IC system clock signal CLKOUT is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output PHSOUT is Page 9 of 39 July 28, 2009 - VID6 VID6 + + ERROR AMPLIFIER - - + VDAC + - - - + - - + - PSI PSI - VID6 VID6 + CURRENT SENSE AMPLIFIER CSIN+ CCS RCS CSIN- VCC VCCH GATEH CBST PGND PSI PSI CCS RCS CSIN- IR3502 connected to the phase clock input PHSIN of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. The PHSOUT of the last phase IC is connected back to PHSIN of the control IC. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency equals the number of phase times the switching frequency. Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) P hase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 4 Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. With the PHSIN voltage high, upon receiving the falling edge of a clock pulse, the PWM latch is set. The PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is turned on after the non-overlap time. When the PWMRMP voltage exceeds the error amplifier’s output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time. Along with that, it activates the ramp discharge clamp, which quickly discharges the PWMRMP capacitor to the output voltage of share adjust amplifier in phase IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate, given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. The error amplifier is a high speed amplifier with wide bandwidth and fast slew rate incorporated in the control IC. It is not unity gain stable. This control method is designed to provide “single cycle transient response,” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in the ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 5 depicts PWM operating waveforms under various conditions. Page 10 of 39 July 28, 2009 IR3502 PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCCLUV, OCP, VID=11111X) STEADY-STATE OPERATION Body Braking TM Figure 5 PWM Operating Waveforms In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = L * ( I MAX − I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = L * ( I MAX − I MIN ) VO + VBODYDIODE Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. This patented technique is referred to as “body braking” and is accomplished through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver, enabling the bottom FET body diode to take over. There is 100mV upslope and 200mV down slope hysteresis for the body braking comparator. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 6. The equation of the sensing network is, vC ( s ) = vL ( s ) 1 RL + sL = iL ( s ) 1 + sRCS CCS 1 + sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen, such that, the time constant of Rcs and Ccs equals the time constant of the inductor, which is the inductance L over the inductor DCR RL. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense Page 11 of 39 July 28, 2009 IR3502 resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. vL iL L RC S RL CC S VO CO Current Sense Amp c vC S CSOUT Figure 6 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 6. Its gain is nominally 33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the VDAC voltage and sent to the control IC and other phases through an on-chip 3K resistor connected to the IIN pin. The IIN pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/1mV in order to reduce the current sense error. The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This calibration algorithm creates ripple on IIN bus with a frequency of fsw/(32*28) in a multiphase architecture. Average Current Share Loop Current sharing between the phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated; such that, the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. Page 12 of 39 July 28, 2009 IR3502 IR3502 THEORY OF OPERATION Block Diagram The block diagram of the IR3502 is shown in Figure 7, and specific features are discussed in the following sections. VID Control The control IC allows the processor voltage to be set by a parallel eight bit digital VID bus. The VID codes set the VDAC as shown in Table 1. The VID pins require an external bias voltage and should not be floated. The VID input comparators monitor the VID pins and control the Digital-to-Analog Converter (DAC), whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error amplifier and remote sense differential amplifier are post-package trimmed to achieve 0.5% system set-point accuracy for VID range between 1V to 1.6V. A set-point accuracy of ±5mV and ±8mV is achieved for VID ranges of 0.8V-1V and 0.5V-0.8V respectively. The actual VDAC voltage does not determine the system accuracy, which has a wider tolerance. The IR3502 can accept changes in the VID code while operating and vary the VDAC voltage accordingly. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. Adaptive Voltage Positioning Adaptive voltage positioning is needed to optimize the output voltage deviations during load transients and the power dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 8. The output voltage is set by the reference voltage VSETPT at the positive input to the error amplifier. This reference voltage can be programmed to have a constant DC offset below the VDAC by connecting RSETPT between VDAC and VSETPT. The IVSETPT is controlled by the ROSC. The average load current information for all the phases is fed back to the control IC through the IIN pin. As shown in Figure 8, this information is thermally compensated with some gain by a set of buffer and thermal compensation amplifiers to generate the voltage at the VDRP pin. The VDRP pin is connected to the FB pin through the resistor RDRP. Since the error amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an additional current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the VDRP voltage increases accordingly. More current flows through the feedback resistor RFB and causes the output to have more droop. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and therefore independent of the VDAC voltage. Inductor DCR Temperature Compensation A negative temperature coefficient (NTC) thermistor should be used for inductor DCR temperature compensation. The thermistor and tuning resistor network connected between the VN and VDRP pins provides a single NTC thermal compensation. The thermistor should be placed close to the power stage to accurately reflect the thermal performance of the inductor DCR. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. Remote Voltage Sensing VOSEN+ and VOSEN- are used for remote sensing and connected directly to the load. The remote sense differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and fast transient response. There is finite input current at both pins VOSEN+ and VOSEN- due to the internal resistor of the differential amplifier. This limits the size of the resistors that can be used in series with these pins for acceptable regulation of the output voltage. Page 13 of 39 July 28, 2009 IR3502 Figure 7 Block Diagram Page 14 of 39 July 28, 2009 IR3502 TABLE 1 VR11 VID TABLE (PART1) Hex (VID7:VID0) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Dec (VID7:VID0) 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 00001001 00001010 00001011 00001100 00001101 00001110 00001111 00010000 00010001 00010010 00010011 00010100 00010101 00010110 00010111 00011000 00011001 00011010 00011011 00011100 00011101 00011110 00011111 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 Voltage Fault Fault 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 Hex (VID7:VID0) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Dec (VID7:VID0) 01000000 01000001 01000010 01000011 01000100 01000101 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 01001111 01010000 01010001 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01011010 01011011 01011100 01011101 01011110 01011111 01100000 01100001 01100010 01100011 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 Voltage 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 Page 15 of 39 July 28, 2009 IR3502 TABLE 1 VR11 VID TABLE (PART 2) Hex (VID7:VID0) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Dec (VID7:VID0) 10000000 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001 10010010 10010011 10010100 10010101 10010110 10010111 10011000 10011001 10011010 10011011 10011100 10011101 10011110 10011111 10100000 10100001 10100010 10100011 10100100 10100101 10100110 10100111 10101000 10101001 10101010 10101011 10101100 10101101 10101110 10101111 10110000 10110001 10110010 10110011 10110100 10110101 10110110 10110111 10111000 10111001 10111010 10111011 10111100 10111101 10111110 10111111 Voltage 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS Hex (VID7:VID0) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Dec (VID7:VID0) 11000000 11000001 11000010 11000011 11000100 11000101 11000110 11000111 11001000 11001001 11001010 11001011 11001100 11001101 11001110 11001111 11010000 11010001 11010010 11010011 11010100 11010101 11010110 11010111 11011000 11011001 11011010 11011011 11011100 11011101 11011110 11011111 11100000 11100001 11100010 11100011 11100100 11100101 11100110 11100111 11101000 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 11110001 11110010 11110011 11110100 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 Voltage TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS TBS FAULT FAULT Page 16 of 39 July 28, 2009 IR3502 Control IC + EAOUT VDAC1 + FB IOUT Error Amplifier Phase IC CSIN+ RFB RDRP VDAC VDAC 3k - CSIN- Current Sense Amplifier 100k 200k IIN VDAC Buffer + Thermal Comp Amplifier + VDRP VN RTCMP1 RTHERM - RTCMP2 Phase IC + IOUT DAC_BUFF CSIN+ 3k RTCMP3 - CSIN- VO VDAC Current Sense Amplifier Remote Sense Amplifier + VOSEN+ - VOSEN- Figure 8 Adaptive voltage positioning with thermal compensation. Start-up Sequence The IR3502 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down slope of the voltage at the SS/DEL pin respectively. Figure 9 depicts start-up sequence of converter with VR 11.1 VID. If there is no fault, as the ENABLE is asserted, the SS/DEL pin will start charging. The error amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the 1.1V boot voltage. The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay comparator. The VID set inputs are then activated and VDAC pin transitions to the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows the VRRDY signal to be asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start. The remote sense amplifier has a very low operating range of 50 mV in order to achieve a smooth soft start of output voltage without bump. The VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The VRRDY pin also drives low and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive VRRDY low. However, the latches can only be reset by cycling VCCL power. Page 17 of 39 July 28, 2009 IR3502 VCC (12V) ENABLE VID 1.1V VDAC 4.0V 3.92V 3V 1.4V SS/DEL EAOUT VOUT VRRDY START DELAY (TD1) SOFT START TIME (TD2) VID SAMPLE TIME (TD3) VRRDY DELAY TIME (TD4+TD5) TD4 TD5 NORMAL OPERATION Figure 9 Start-up sequence of converter with boot voltage Current Monitor (IMON) The control IC generates a current monitor signal IMON using the VDRP voltage and the VDAC reference, as shown in Figure 10. This voltage is thermally compensated for the inductor DCR variation. The voltage at this pin reports the average load current information without being referenced to VDAC. The slope of the IMON signal with respect to the load current can be adjusted with the resistors RTCMP2 and RTCMP3. The IMON signal is clamped at 1.03V in order to facilitate direct interfacing with the CPU. Control IC VDAC Buffer + VDAC - 100k 200k - DAC_BUFF VDRP Buffer Thermal Comp Amplifier + + IIN From Phase ICs RTCMP1 RTHERM VDRP - RTCMP2 VN RTCMP3 DAC_BUFF 200k 200k 1.03 0 IMON VDRP 200k + 200k 50mV Figure 10 Current report signal (IMON) implementation Page 18 of 39 July 28, 2009 IR3502 Constant Over-Current Control during Soft Start The over current limit is fixed by 1.17V above the VDAC. If the VDRP pin voltage, which is proportional to the average current plus VDAC voltage, exceeds (VDAC+1.17V) during soft start, the constant over-current control is activated. Figure 11 shows the constant over-current control with delay during soft start. The delay time is set by the ROSC resistor, which sets the number of switching cycles for the delay counter. The delay is required since overcurrent conditions can occur as part of normal operation due to inrush current. If an over-current occurs during soft start (before VRRDY is asserted), the SS/DEL voltage is regulated by the over current amplifier to limit the output current below the threshold set by OC limit voltage. If the over-current condition persists after delay time is reached, the fault latch will be set pulling the error amplifier’s output low and inhibiting switching in the phase ICs. The SS/DEL capacitor will discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle, the constant over-current control actions will repeat and the converter will be in hiccup mode. The delay time is controlled by a counter which is triggered by clock. The counter values vary with switching frequency per phase in order to have a similar delay time for different switching frequencies. ENABLE INTERNAL OC DELAY 4.0V 3.92V 3.88V 1.1V SS/DEL EA VOUT VRRDY OCP THRESHOLD =VDAC_BUFF+1.17V IOUT HICCUP OVER-CURRENT PROTECTION (OUTPUT SHORTED) NORMAL START-UP OCP DELAY OVER-CURRENT NORMAL NORMAL PROTECTION START-UP OPERATION POWER-DOWN (OUTPUT SHORTED) START-UP WITH OUTPUT SHORTED (OUTPUT NORMAL OPERATION SHORTED) Figure 11 Constant over-current control waveforms during and after soft start. Over-Current Hiccup Protection after Soft Start The over current limit is fixed at 1.17V above the VDAC. Figure 11 shows the constant over-current control with delay after VRRDY is asserted. The delay is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions. If the VDRP pin voltage, which is proportional to the average current plus VDAC voltage, exceeds (VDAC+1.17V) after VRRDY is asserted, it will initiate the discharge of the capacitor at SS/DEL. The magnitude of the discharge current is proportional to the voltage difference between VDRP and (VDAC+1.17V) and has a maximum nominal value of 55uA. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 120mV offset of the delay comparator, the fault latch will be set pulling the error amplifier’s output low and inhibiting switching in the phase ICs and de-asserting the VRRDY signal. The output current is not controlled during the delay time. The SS/DEL capacitor will discharge until it reaches 200 mV and the fault latch is reset allowing a normal soft Page 19 of 39 July 28, 2009 IR3502 start to occur. If an over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. Linear Regulator Output (VCCL) The IR3502 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The voltage of VCCL is fixed at 6.8V with the feedback resistive divider internal to the IC. The regulator output powers the gate drivers of the phase ICs and circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a function of the number of phases used in the multiphase architecture and their switching frequency. Figure 12 shows the stability plots for the linear regulator with 5 phases switching at 750 kHz. VCCL Under Voltage Lockout (UVLO) The IR3502 has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage instead, which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up, the fault latch will be reset if VCCL is above 94% of 6.8V. If VCCL voltage drops below 80% of 6.8V, the fault latch will be set. Figure 12 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz. Over Voltage Protection (OVP) Output over-voltage happens during normal operation if a high side MOSFET short occurs or if output voltage is out of regulation. The over-voltage protection comparator monitors VO pin voltage. If VO pin voltage exceeds VDAC by 130mV after SS, as shown in Figure 13, IR3502 raises ROSC/OVP pin voltage above to V(VCCL) - 1V, which sends over voltage signal to system. During startup, the threshold is 130 mV above last VID and reverts back to VBOOT+130mV during boot mode. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit, which pulls the converter input low in over voltage conditions. The over voltage condition also sets the over voltage fault latch, which pulls error amplifier output low to turn off the converter output. At the same time IIN pin (IIN of phase ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure 13. In each phase IC, the OVP circuit overrides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain on until IIN pin voltage drops below V(VCCL) - 800mV, which signals the end of over voltage condition. An over voltage fault condition is latched in the IR3502 and can only be cleared by cycling power to the IR3502 VCCL. Page 20 of 39 July 28, 2009 IR3502 OUTPUT VOLTAGE (VO) OVP THRESHOLD 130mV VCCL-800 mV IIN (ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER OUTPUT (EAOUT) VDAC NORMAL OPERATION OVP CONDITION AFTER OVP Figure 13 Over-voltage protection during normal operation 12V VCC VCCL+0.7V V CCL+0.7V 12V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ROSC/OVP 1.6V Figure 14 Over-voltage protection during power-up. Page 21 of 39 July 28, 2009 IR3502 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT VOLTAGE (VOSEN+) 1.8V 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 15 Over-voltage protection with pre-charging converter output Vo > 1.73V 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT VOLTAGE (VOSEN+) 1.73V VID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 16 Over-voltage protection with pre-charging converter output VID + 0.13V