IR3519

IR3519 FEATURES Synchronous MOSFET Gate Driver IC DESCRIPTION The IR3519 is extended voltage range high-speed gate driver optimized for switching power supply applications. Performance is achieved by 7V/2A gate source and 5-A sink drive capability and is capable of operating at frequencies of up to 2MHz. The 0.4-Ω impedance of the lower gate driver holds the gate of the Synchronous MOSFET below its threshold to prevent shoot-through current during high dv/dt phase node transitions. The IR3519 includes a two-way enable/under voltage power good signal. Systems without 3-state featured controllers can use the EN/UV input/output to hold both outputs low during converter shut down. 7V/2A gate drivers (5A GATEL sink current) 15ns adaptive non-overlap control Integrated boot-strap synchronous PFET Supports 3.3V and 5V PWM input signals Tri-State PWM input for power stage shutdown Sub 50ns minimum pulse width supports 2MHz perphase operation Dual function EN/UV pin provides Enable input and power good output Small thermally enhanced 8L SON & 3 x 3mm MLPD packages RoHS compliant APPLICATION CIRCUIT ORDER INFORMATION Device IR3519MTRPBF * IR3519MPBF IR3519STRPBF * IR3519SPBF * Samples only Package 8 Lead MLPD (3 x 3 mm body) 8 Lead MLPD (3 x 3 mm body) 8 Lead SON 8 Lead SON Order Quantity 3000 per reel 100 piece strips 2500 per reel 95 per tube Page 1 of 10 www.irf.com 8/15/08 IR3519 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings (Referenced to GND) BOOT Voltage: ................................................ 40 V PH Voltage: ..............-5V(100ns),-0.3V(DC) to 35 V UGATE Voltage: ......-5V(100ns),-0.3V(DC) to 40 V LGATE Voltage: .........-5V(100ns),-0.3V(DC) to 8 V BOOT - PH Voltage: ............................ -0.3V to 8 V UGATE - PH Voltage: .......................... -0.3V to 8 V VDD: .................................................................. 8 V GND: .................................................. -0.3V to 0.3V All other pins ........................................ -0.3V to 8 V Operating Junction Temperature .. -10°C to +150oC MSL Rating .................................................. Level 2 Reflow Temperature …................................260oC Storage Temperature Range .......... -65oC to 150oC ESD Rating ......... HBM Class 1C JEDEC Standard Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. RECOMMENDED OPERATING CONDITIONS o o 6.5V≤ VDD ≤ 7.5V, 0 C ≤ TJ ≤ 125 C ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CUGATE = 3.3nF, CLGATE = 6.8nF (unless otherwise specified). PARAMETER Gate Drivers UGATE Source Resistance UGATE Sink Resistance LGATE Source Resistance LGATE Sink Resistance UGATE Source Current UGATE Sink Current LGATE Source Current LGATE Sink Current UGATE Rise Time UGATE Fall Time LGATE Rise Time LGATE Fall Time TEST CONDITION BOOT – PH = 7V. Note 1 BOOT – PH = 7V. Note 1 VDD –GND = 7V. Note 1 VDD – GND = 7V. Note 1 BOOT=7V, UGATE=3.5V, SW=0V. Note 1 BOOT=7V, UGATE=3.5V, SW=0V. Note 1 VDD=7V, LGATE=3.5V, GND=0V. Note 1 VDD=7V, LGATE=3.5V, GND=0V. Note 1 BOOT – PH = 7V, measure 1V to 4V transition time. BOOT - PH = 7V, measure 4V to 1V transition time. VDD – GND = 7V, Measure 1V to 4V transition time. VDD – GND = 7V, Measure 4V to 1V transition time. MIN TYP 1.0 1.0 1.0 0.4 2.0 2.0 2.0 5.0 5 5 10 5 MAX 2.5 2.5 2.5 1.0 UNIT Ω Ω Ω Ω A A A A ns ns ns ns Page 2 of 10 www.irf.com 8/15/08 IR3519 PARAMETER LGATE low to UGATE high delay TEST CONDITION BOOT = VDD = 7V, PH =0V GND = 0V, measure time from LGATE falling to 1V to UGATE rising to 1V. BOOT = VDD = 7V, PH =0V GND = 0V, measure time from UGATE falling to 1V to LGATE rising to 1V. Note 1 MIN 5 TYP 15 MAX UNIT ns UGATE low to LGATE high delay 5 15 ns Minimum Pulse Width Passive Gate Pull-Down Resistance PH Bias Current 30 20 -2 50 ns kΩ μA Measure with PWM=Tri-state, PH=1V -10 VDD Under Voltage Lockout Comparator (VUVLO) Start Threshold Stop Threshold Hysteresis Start – Stop PWM Input UGATE Threshold Voltage, PWM rising VUGATE TH UGATE Threshold Voltage, PWM falling VUGATE TH UGATE Threshold Hysteresis LGATE Threshold Voltage, PWM falling VLGATE TH LGATE Threshold Voltage, PWM rising VLGATE TH LGATE Threshold Hysteresis Tri-State Bias voltage, VPWM TRI Input Bias Current V(PWM) = 0V V(PWM) = 3.3V V(PWM) = 5V Tri-State Time Constant CPWM = 20pF, Measure time from V(PWM) = 0V release to LGATE < 1V. Note 1 CPWM = 20pF, Measure time from V(PWM) = 3.3V release to HGATE < 1V. Note 1 CPWM = 20pF, Measure time from V(PWM) = 5V release to HGATE < 1V. Note 1 5.65 5.4 6.0 5.7 6.3 6.1 0.4 2.4 2.3 170 1.0 1.1 170 1.8 -160 270 570 V V V V V mV V V mV V μA μA μA ns 2.0 1.9 30 0.6 0.74 30 1.2 -260 140 370 2.2 2.1 90 0.8 0.9 90 1.6 -210 200 460 190 270 ns 380 ns Page 3 of 10 www.irf.com 8/15/08 IR3519 PARAMETER EN/UV Input/Output Threshold Voltage, VEN TH Hysteresis Pull-down Resistance Sink Current Bootstrap PFET Forward Voltage General VDD Supply Current VDD Supply Current TEST CONDITION EN/UV rising, UV FET off EN/UV falling, UV FET off MIN 1.1 0.6 350 600 200 450 TYP 1.75 1.1 650 1000 350 660 50 700 MAX 2.0 1.4 800 1400 500 750 100 1000 UNIT V V mV Ω μA mV uA uA VDD = 2.5V, V(EN/UV) = 0.6V I(BOOT) = 30mA, VDD = 7V EN = 0, PWM = Tri-State EN = 3.3 V, PWM = Tri-State Note 1: Guaranteed by design, but not tested in production Page 4 of 10 www.irf.com 8/15/08 IR3519 IC PIN ORDER AND DESCRIPTION NAME UGATE BOOT PWM GND LGATE VDD EN/UV NUMBER 1 2 3 4 5 6 7 I/O LEVEL VIN + VDD VIN +VDD Up to 5V Reference IC VDD Typical 7V 3.3V DESCRIPTION High-side driver output and input to GATEL non-overlap comparator Bootstrapped gate drive supply – connect a capacitor to PHASE Logic input Power return – connect to source of synchronous MOSFET Lower gate drive for synchronous MOSFET IC bias supply PH 8 VIN Bias this pin to > 2V to enable and < 0.6V to disable the IC (both gate outputs held low). If VDD is below the under voltage lockout threshold this pin is internally pulled low and provides an input Power Good indicator function. If the Power Good and Enable functions are not required this pin can be connected to the VDD pin. Do not float this pin as incorrect operation could occur. Return for high-side driver, reference for GATEL non-overlap comparator, and input to the diode emulation comparator. Page 5 of 10 www.irf.com 8/15/08 IR3519 BLOCK DIAGRAM Page 6 of 10 www.irf.com 8/15/08 IR3519 FUNCTIONAL DESCRIPTION IR3519 switches the LGATE and UGATE signals when VDD is greater than VUVLO and EN/UV voltage is greater than VEN TH. The gate drive logic features adaptive dead time which prevents simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below approximately 1V after PWM goes HIGH and before the upper MOSFET can be gated on. Also the upper gate voltage, the different voltage between UGATE and PH, must be below approximately 1V after PWM goes LOW and before the lower MOSFET can be gated on. The internal logic will evaluate the PWM voltage level. The PWM is considered HIGH when its level is greater than VUGATE TH. PWM is considered LOW when its level is below VLGATE TH. In the middle voltage region of VUGATE TH and VLGATE TH, the PWM will be in tri-state mode. In the absence of external drive, the PWM pin is pulled to this middle region by a VPWM TRI source through an internal resistor. After a short time delay in this middle region, IR3519 is forced into a low power state. The UGATE logic evaluates its input logic signal and generates a PH referenced to drive the UGATE pin, which turns on/off the external high side MOSFET. PH pin is to be connected to the source of the upper MOSFET, the buck inductor, and to the drain of the lower MOSFET. To turn on the upper N channel MOSFET, a bootstrap circuit is required. This is accomplished by charging a capacitor (connected BOOT to PH) after the lower MOSFET conducts and the PH pin is substantially at GND. VDD provides the charging current through an internal BOOTSTRAP diode. The minimum boot capacitor value is calculated below. The boot capacitor starts the cycle fully charged to a voltage of VB(0). An equivalent gate drive capacitance is calculated by consulting the high side MOSFET data sheet and taking the ratio of total gate charge at the VDD voltage, QG(VDD), to the VDD voltage. QG(VDD)/VDD is the equivalent gate drive capacitance Cg which will be used in the following calculations. The voltage of the capacitor pair CB and Cg after Cg becomes charged at CB’s expense will be VB(0)-ΔV. Choose a sufficiently small ΔV such that VB(0)-ΔV exceeds the maximum gate threshold voltage to turn on the high side MOSFET. Since total charge QT is conserved, we can write the following equation. VB (0) ⋅ C B = Q T = V(t on ) ⋅ (C B + C g ) After rearranging this equation, it becomes the equation below. ⎛ V (0) ⎞ CB = C g ⋅ ⎜ B ⎜ ΔV − 1⎟ ⎟ ⎝ ⎠ Choose a boot capacitor value larger than the calculated CB. The voltage rating of this part needs to be larger than VB(0) plus the desired derating voltage. Its ESR and ESL needs to be low in order to allow it to deliver the large current and di/dt’s which drive MOSFETs most efficiently. In support of these requirements a ceramic capacitor should be chosen. The LGATE logic evaluates its input signal and generates a GND referenced to drive the LGATE pin, which turns on/off the external low side MOSFET. The LGATE logic uses VDD source to turn on the low side MOSFET because the source of low side MOSFET is reference to GND. LAYOUT RECOMMENDATION One 1uF high quality ceramic capacitor is required to place near VDD pin as possible. Other end of capacitor is recommended to tie to GND pin plan as close to as IC possible. This GND island plan can be via or directly connect to the main GND plan or layer. If the connection of GND pin to the source of low side MOSFET through an internal layer, it is recommended connecting through at least 2 vias by build a small island of next to GND pin. The boot capacitor needs to place close to BOOT and PH pins to reduce the impedance during the turn-on process of high side MOSFET. The main function of boot capacitor is to supply the energy for turning on high side MOSFET. It is recommended to add zero Ohm resistor in series with boot capacitor as place holder. When connecting the trace for UGATE and LGATE signals, one needs to keep in mind that the signal return path is as an important as signal path. The return path contains both AC and DC current. DC current takes the least resistance path. AC current takes the least impedance path. The return path is exits whether or not provide it. If the designer is overlooked the return path, the AC current will cause the more noise in the system. Therefore, it is recommended to place LGATE signal path on top next to the source of low side MOSFET path and place UGATE signal path on top of PH signal path. When connecting PHASE signal path to power stage area, PHASE signal needs to chose quite area. Figure 1 shows the location of connection from power stage to IR3519 PHASE pin less noise sensitive than Figure 2. 8/15/08 Page 7 of 10 www.irf.com IR3519 PH PH Figure 1: Phase Node Sense with Less Noise PH PH Figure 2: Phase Node Sense with More Noise Page 8 of 10 www.irf.com 8/15/08 IR3519 PACKAGE INFORMATION 3 X 3MM MLPD Page 9 of 10 www.irf.com 8/15/08 IR3519 8L SON Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 05/07 Page 10 of 10 www.irf.com 8/15/08