IR3529

IR3529 DATA SHEET XPHASE3TM PHASE IC DESCRIPTION The IR3529 Phase IC combined with an IR XPhase3 Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a TM multiphase converter. The XPhase3 architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3529 provides two types of current sense outputs; ILL which contains average power supply current, information which can be used for voltage positioning and ISHARE which contains average active phase current information since current sense amplifiers of respective phases are disabled when in power savings mode. Higher efficiency can be expected due to increased driver capability along with reduced non-overlap durations. Turbo is included to improve load turn-on response. A SHIFT pin now communicates to the control IC a change in phase IC on-line status resulting in controlled phase timing during PSI and Phase Shedding. The IR3529 also implements cycle-by-cycle over current protection to resolve high repetition rate load transients. TM FEATURES • • • • • • • • • • • • • • • • • • • • • Reduced dead time 7V gate drivers (6A GATEL sink current, 4A GATEH sink current) Turbo Mode load turn-on response enhancement Programmable cycle-by-cycle over current limit protection Phase status communicated to control IC for controlled phase timing during PSI and Phase Shedding Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads. Anti-bias circuitry Support converter output voltage up to 5.1 V (Limited to VCCL-1.8V) Loss-less inductor current sensing Phase delay DFF bypassed during PSI assertion mode to improve output ripple performance Over-current protection during PSI assertion mode operation Feed-forward voltage mode control Integrated boot-strap synchronous PFET Only four external components per phase 3 wire analog bus connects Control and Phase ICs (VID, Error Amp, Average Power Supply Current) 3 wire digital bus for accurate daisy-chain phase timing control without external components Debugging function isolates phase IC from the converter Self-calibration of PWM ramp, current sense amplifier, and current share amplifier Single-wire bidirectional average current sharing Small thermally enhanced 20L 4 X 4mm MLPQ package RoHS compliant Page 1 of 22 February 12, 2010 IR3529 APPLICATION CIRCUIT 12V VCCL EAIN 18 19 20 17 16 ISHARE ROCSET C OCSET RCS SW GATEH 15 14 13 12 11 CVCCL1 VOUTCBST COUT L VOUT+ CCS ISHARE CSIN+ CSIN- ILL PSI# DACIN 1 2 3 4 5 ILL PSI# DACIN LGND EAIN IR3529 PHSOUT VCC BOOST VCCL GATEL 10 OCSET PHSIN SHIFT CLKIN 8 PHSIN 6 7 SHIFT PHSOUT CLKIN 9 Figure 1 Single Phase Application Circuit ORDERING INFORMATION Part Number IR3529MTRPBF * IR3529MPBF * Samples only Package 20 Lead MLPQ (4 x 4 mm body) 20 Lead MLPQ (4 x 4 mm body) Order Quantity 3000 per reel 100 piece strips Page 2 of 22 PGND February 12, 2010 IR3529 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature…………….. 0 to 150 C o o Storage Temperature Range………………….-65 C to 150 C MSL Rating………………………………………2 o Reflow Temperature…………………………….260 C PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: 1. 2. 3. 4. PIN NAME ILL PSI# DACIN LGND PHSIN SHIFT PHSOUT CLKIN PGND GATEL OCSET VCCL BOOST GATEH SW VCC CSIN+ CSINEAIN ISHARE Maximum Maximum Maximum Maximum VMAX 7.5V 7.5V 3.3V n/a 7.5V 7.5V 7.5V 7.5V 0.3V 7.5V 25V 7.5V 40V 40V 34V 25V 7.5V 7.5V 7.5V 7.5V VMIN -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V DC, -5V for 100ns -0.3V -0.3V -0.3V -0.3V DC, -5V for 100ns -0.3V DC, -5V for 100ns -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA n/a 1mA 2mA 2mA 1mA 5A for 100ns, 200mA DC 5A for 100ns, 200mA DC 1mA n/a 1A for 100ns, 100mA DC 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC n/a 1mA 1mA 1mA 1mA ISINK 1mA 1mA 1mA n/a 1mA 2mA 2mA 1mA n/a 5A for 100ns, 200mA DC 1mA 5A for 100ns, 200mA DC 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC n/a 10mA 1mA 1mA 1mA 1mA o GATEH – SW = 8V BOOST – GATEH = 8V OCSET = VCC SW – VCC = 9V Page 3 of 22 February 12, 2010 IR3529 RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 8.0V ≤ VCC ≤ 16V, 4.75V ≤ VCCL ≤ 7.5V, 0 C ≤ TJ ≤ 125 C. 0.5V ≤ V(DACIN) ≤ 1.6V, 500kHz ≤ CLKIN ≤ 9MHz, 250kHz ≤ PHSIN ≤1.5MHz. o o ELECTRICAL CHARACTERISTICS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified) PARAMETER Gate Drivers GATEH Source Resistance GATEH Sink Resistance GATEL Source Resistance GATEL Sink Resistance GATEH Source Current GATEH Sink Current GATEL Source Current GATEL Sink Current GATEL low to GATEH high delay GATEH low to GATEL high delay PWM Comparator PWM Ramp Slope EAIN Bias Current Minimum Pulse Width Minimum GATEH Turn-off Time Daisy Chain Timing CLKIN Bias Current CLKIN Phase Delay PHSIN Pull-Down Resistance PHSOUT High Voltage PHSOUT Low Voltage Down SHIFT Pulse width Up SHIFT Pulse width SHIFT Resistance to Rails Current Sense Amplifier CSIN+/- Bias Current TEST CONDITION BOOST – SW = 7V. BOOST – SW = 7V. VCCL – PGND = 7V. VCCL – PGND = 7V. BOOST=7V, GATEH=2.5V, SW=0V. BOOST=7V, GATEH=2.5V, SW=0V. VCCL=7V, GATEL=2.5V, PGND=0V. VCCL=7V, GATEL=2.5V, PGND=0V. BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEL falling to 1V to GATEH rising to 1V BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEH falling to 1V to GATEL rising to 1V Vin=12V 0 ≤ EAIN ≤ 3V Note 1 MIN TYP 670 670 670 300 3 4 4 6 5 15 25 MAX UNIT m m m m A A A A ns 5 15 25 ns 42 -25 20 52.5 -15 55 80 0.0 75 100 0.6 0.4 50 50 50 57 -5 70 160 0.5 125 170 mV/ %DC µA ns ns CLKIN = V(VCCL) Measure time from CLKIN1V -0.5 40 30 µA ns k V I(PHSOUT)=-10mA, measure VCCL– PHSOUT I(PHSOUT) = 10mA 47pF load, 27% VCCL 47pF load, 77% VCCL 1 25 25 20 1 75 75 80 V ns ns k I(CSINM) measured with I(CSINM) sink turned off (i.e. within 8us of CLKIN fall and EAIN above Body Brake Threshold and CSINM above 75% DACIN) -200 0 200 nA Page 4 of 22 February 12, 2010 IR3529 PARAMETER SW Floating Voltage TEST CONDITION Measured in the application with the converter not switching. Measure after 50us of CLKIN=0 with CSINM shorted to SW CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN. Note1 0.5V ≤ V(DACIN) < 1.6V 0.8V ≤ V(DACIN) ≤ 1.6V, Note 1 0.5V ≤ V(DACIN) < 0.8V, Note 1 Note 1 MIN 10 -450 31.0 -10 -5 0 3.6 3.6 I(CSINM) measured with I(CSINM) sink turned off (i.e. within 8us of CLKIN fall and EAIN above Body Brake Threshold and CSINM above 75% DACIN) Measured in the application with the converter not switching. Measure after 50us of CLKIN=0 with CSINM shorted to SW CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN. Note1 0.5V ≤ V(DACIN) < 1.6V 0.8V ≤ V(DACIN) ≤ 1.6V, Note 1 0.5V ≤ V(DACIN) < 0.8V, Note 1 Note 1 4.7 4.7 32.5 TYP 100 MAX 250 +450 34.5 50 50 VCCL – 2.5V 5.4 5.4 UNIT mV Calibrated Input Offset Voltage GAIN Differential Input Range Differential Input Range Common Mode Input Range ILL Rout at TJ = 125 ºC ISHARE Rout at TJ =125 ºC Current Sense Amplifier CSIN+/- Bias Current µV V/V mV mV V k k -200 0 200 nA SW Floating Voltage 10 -450 31.0 -10 -5 0 3.6 100 250 +450 mV Calibrated Input Offset Voltage Gain Differential Input Range Differential Input Range Common Mode Input Range o ILL Rout at TJ = 125 C ISHARE Rout at TJ =125 C Share Adjust Amplifier Maximum PWM Ramp Floor Voltage Minimum PWM Ramp Floor Voltage Body Brake Comparator Threshold Voltage with EAIN decreasing Threshold Voltage with EAIN increasing Hysteresis Body Brake Comparator Threshold Voltage with EAIN decreasing Threshold Voltage with EAIN increasing Hysteresis Page 5 of 22 o µV V/V mV mV V k k 32.5 34.5 50 50 VCCL – 2.5V 5.4 5.4 4.7 4.7 3.6 ISHARE = DACIN – 200mV. Measure relative to floor voltage. ISHARE = DACIN + 200mV. Measure relative to floor voltage. Measure relative to Floor Voltage Measure relative to Floor Voltage 120 -220 180 -160 240 -100 mV mV -300 -200 70 -200 -100 105 -110 -10 130 mV mV mV Measure relative to Floor Voltage Measure relative to Floor Voltage -300 -200 70 -200 -100 105 -110 -10 130 mV mV mV February 12, 2010 IR3529 PARAMETER OVP Comparator OVP Threshold Propagation Delay TEST CONDITION Step V(ILL) up until GATEL drives high. Compare to V(VCCL) V(VCCL)=5V, Step V(ILL) up from V(DACIN) to V(VCCL). Measure time to V(GATEL)>4V. MIN -1.0 15 TYP -0.8 40 MAX -0.4 70 UNIT V ns Synchronous Rectification Disable Comparator Threshold Voltage Over Current Comparator IOCSET Sink Current The ratio of V(CSIN-) / V(DACIN), below which V(GATEL) is always low. 0C, 100mV